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sparc.h: Remove dead code.
* config/sparc/sparc.h: Remove dead code. * config/sparc/sparc.c (sparc_compute_frame_size): Use FIRST_PARM_OFFSET for the size of the register window area. (emit_save_regs): Rename into emit_save_or_restore_regs. Add 'action' parameter. Use 4095 as upper bound for the offset. Pass 'action' to save_or_restore_regs. (emit_restore_regs): Delete. (sparc_expand_prologue): Call emit_save_or_restore_regs. (sparc_expand_epilogue): Likewise. * config/sparc/sparc.md (mode macro P): Move. (movdi_insn_sp32_v9, movdi_insn_sp32): Swap. (mov<V32:mode> expander): Move to the top of the V32 section. (movdf_insn_sp32_v9_no_fpu, movdf_insn_sp32_v9): Swap. (movtf_insn_sp64_hq, movtf_insn_sp64): Swap. (sibcall_epilogue): Move. From-SVN: r99609
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
fa2c88a05b
commit
f8ece00085
@ -1,3 +1,21 @@
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2005-05-12 Eric Botcazou <ebotcazou@libertysurf.fr>
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* config/sparc/sparc.h: Remove dead code.
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* config/sparc/sparc.c (sparc_compute_frame_size): Use
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FIRST_PARM_OFFSET for the size of the register window area.
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(emit_save_regs): Rename into emit_save_or_restore_regs.
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Add 'action' parameter. Use 4095 as upper bound for the offset.
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Pass 'action' to save_or_restore_regs.
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(emit_restore_regs): Delete.
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(sparc_expand_prologue): Call emit_save_or_restore_regs.
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(sparc_expand_epilogue): Likewise.
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* config/sparc/sparc.md (mode macro P): Move.
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(movdi_insn_sp32_v9, movdi_insn_sp32): Swap.
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(mov<V32:mode> expander): Move to the top of the V32 section.
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(movdf_insn_sp32_v9_no_fpu, movdf_insn_sp32_v9): Swap.
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(movtf_insn_sp64_hq, movtf_insn_sp64): Swap.
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(sibcall_epilogue): Move.
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2005-05-12 Richard Earnshaw <richard.earnshaw@arm.com>
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PR target/21501
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@ -318,8 +318,7 @@ static int set_extends (rtx);
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static void emit_pic_helper (void);
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static void load_pic_register (bool);
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static int save_or_restore_regs (int, int, rtx, int, int);
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static void emit_save_regs (void);
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static void emit_restore_regs (void);
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static void emit_save_or_restore_regs (int);
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static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
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static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
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#ifdef OBJECT_FORMAT_ELF
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@ -3508,10 +3507,9 @@ sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
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/* Make sure nothing can clobber our register windows.
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If a SAVE must be done, or there is a stack-local variable,
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the register window area must be allocated.
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??? For v8 we apparently need an additional 8 bytes of reserved space. */
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the register window area must be allocated. */
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if (! leaf_function_p || size > 0)
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actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
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actual_fsize += FIRST_PARM_OFFSET (current_function_decl);
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return SPARC_STACK_ALIGN (actual_fsize);
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}
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@ -3623,14 +3621,14 @@ save_or_restore_regs (int low, int high, rtx base, int offset, int action)
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/* Emit code to save call-saved registers. */
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static void
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emit_save_regs (void)
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emit_save_or_restore_regs (int action)
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{
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HOST_WIDE_INT offset;
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rtx base;
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offset = frame_base_offset - apparent_fsize;
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if (offset < -4096 || offset + num_gfregs * 4 > 4096)
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if (offset < -4096 || offset + num_gfregs * 4 > 4095)
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{
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/* ??? This might be optimized a little as %g1 might already have a
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value close enough that a single add insn will do. */
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@ -3648,34 +3646,8 @@ emit_save_regs (void)
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else
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base = frame_base_reg;
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offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
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save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
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}
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/* Emit code to restore call-saved registers. */
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static void
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emit_restore_regs (void)
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{
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HOST_WIDE_INT offset;
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rtx base;
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offset = frame_base_offset - apparent_fsize;
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if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
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{
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base = gen_rtx_REG (Pmode, 1);
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emit_move_insn (base, GEN_INT (offset));
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emit_insn (gen_rtx_SET (VOIDmode,
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base,
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gen_rtx_PLUS (Pmode, frame_base_reg, base)));
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offset = 0;
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}
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else
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base = frame_base_reg;
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offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
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save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
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offset = save_or_restore_regs (0, 8, base, offset, action);
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save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, action);
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}
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/* Generate a save_register_window insn. */
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@ -3814,9 +3786,8 @@ sparc_expand_prologue (void)
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
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}
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/* Call-saved registers are saved just above the outgoing argument area. */
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if (num_gfregs)
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emit_save_regs ();
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emit_save_or_restore_regs (SORR_SAVE);
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/* Load the PIC register if needed. */
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if (flag_pic && current_function_uses_pic_offset_table)
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@ -3824,12 +3795,7 @@ sparc_expand_prologue (void)
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}
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/* This function generates the assembly code for function entry, which boils
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down to emitting the necessary .register directives.
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??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
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an 8-byte block of memory. If any fpu reg is used in the function, we
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allocate such a block here, at the bottom of the frame, just in case it's
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needed." Could this explain the -8 in emit_restore_regs? */
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down to emitting the necessary .register directives. */
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static void
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sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
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@ -3847,7 +3813,7 @@ void
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sparc_expand_epilogue (void)
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{
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if (num_gfregs)
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emit_restore_regs ();
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emit_save_or_restore_regs (SORR_RESTORE);
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if (actual_fsize == 0)
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/* do nothing. */ ;
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@ -906,9 +906,6 @@ extern int sparc_mode_class[];
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/* Specify the registers used for certain standard purposes.
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The values of these macros are register numbers. */
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/* SPARC pc isn't overloaded on a register that the compiler knows about. */
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/* #define PC_REGNUM */
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM 14
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@ -1375,16 +1372,12 @@ extern char leaf_reg_remap[];
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If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
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first local allocated. Otherwise, it is the offset to the BEGINNING
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of the first local allocated. */
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/* This allows space for one TFmode floating point value. */
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/* This allows space for one TFmode floating point value, which is used
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by SECONDARY_MEMORY_NEEDED_RTX. */
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#define STARTING_FRAME_OFFSET \
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(TARGET_ARCH64 ? -16 \
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: (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
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/* If we generate an insn to push BYTES bytes,
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this says how many the stack pointer really advances by.
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On SPARC, don't define this because there are no push insns. */
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/* #define PUSH_ROUNDING(BYTES) */
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/* Offset of first parameter from the argument pointer register value.
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!v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
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even if this function isn't going to use it.
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@ -68,14 +68,13 @@
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(UNSPECV_SAVEW 6)
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])
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(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
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;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this
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;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name
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;; is a bit of a misnomer as it covers all 64 fp regs. The corresponding
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;; constraint letter is 'e'. To avoid any confusion, 'e' is used instead of
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;; 'f' for all DF/TFmode values, including those that are specific to the v8.
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;; Attribute for cpu type.
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;; These must match the values for enum processor_type in sparc.h.
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(define_attr "cpu"
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@ -300,6 +299,7 @@
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(define_delay (eq_attr "type" "return")
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[(eq_attr "eligible_for_return_delay" "true") (nil) (nil)])
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;; Include SPARC DFA schedulers
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(include "cypress.md")
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@ -309,6 +309,7 @@
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(include "ultra1_2.md")
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(include "ultra3.md")
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;; Operand and operator predicates.
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(include "predicates.md")
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@ -329,8 +330,6 @@
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;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc
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;; insns that actually require more than one machine instruction.
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;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
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(define_expand "cmpsi"
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[(set (reg:CC 100)
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(compare:CC (match_operand:SI 0 "compare_operand" "")
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@ -1694,7 +1693,10 @@
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}
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[(set_attr "type" "branch")
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(set_attr "branch_type" "reg")])
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(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
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;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
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;; value subject to a PC-relative relocation. Operand 2 is a helper function
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;; that adds the PC value at the call point to operand 0.
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@ -1716,8 +1718,9 @@
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(if_then_else (eq_attr "delayed_branch" "true")
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(const_int 3)
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(const_int 4)))])
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;; Move instructions
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;; Integer move instructions
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(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand" "")
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@ -2121,6 +2124,30 @@
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;; (reg:DI 2 %g2))
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;;
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(define_insn "*movdi_insn_sp32"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
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(match_operand:DI 1 "input_operand"
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" J,U,T,r,o,i,r, f, T, o, f, f"))]
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"! TARGET_V9
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&& (register_operand (operands[0], DImode)
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|| register_operand (operands[1], DImode))"
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"@
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#
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std\t%1, %0
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ldd\t%1, %0
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#
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#
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#
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#
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std\t%1, %0
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ldd\t%1, %0
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#
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#
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#"
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[(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
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(set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
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(define_insn "*movdi_insn_sp32_v9"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
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@ -2150,34 +2177,6 @@
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(set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
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(set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
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(define_insn "*movdi_insn_sp32"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
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(match_operand:DI 1 "input_operand"
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" J,U,T,r,o,i,r, f, T, o, f, f"))]
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"! TARGET_V9
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&& (register_operand (operands[0], DImode)
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|| register_operand (operands[1], DImode))"
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"@
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#
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std\t%1, %0
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ldd\t%1, %0
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#
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#
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#
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#
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std\t%1, %0
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ldd\t%1, %0
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#
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#
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#"
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[(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
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(set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
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;; We don't define V1SI because SI should work just fine.
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(define_mode_macro V64 [DF V2SI V4HI V8QI])
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(define_mode_macro V32 [SF V2HI V4QI])
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(define_insn "*movdi_insn_sp64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b")
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(match_operand:DI 1 "input_operand" "rI,N,m,rJ,e,W,e,J"))]
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@ -2552,6 +2551,72 @@
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;; Floating point and vector move instructions
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;; We don't define V1SI because SI should work just fine.
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(define_mode_macro V32 [SF V2HI V4QI])
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;; Yes, you guessed it right, the former movsf expander.
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(define_expand "mov<V32:mode>"
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[(set (match_operand:V32 0 "general_operand" "")
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(match_operand:V32 1 "general_operand" ""))]
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"<V32:MODE>mode == SFmode || TARGET_VIS"
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{
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/* Force constants into memory. */
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if (GET_CODE (operands[0]) == REG && CONSTANT_P (operands[1]))
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{
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/* emit_group_store will send such bogosity to us when it is
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not storing directly into memory. So fix this up to avoid
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crashes in output_constant_pool. */
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if (operands [1] == const0_rtx)
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operands[1] = CONST0_RTX (<V32:MODE>mode);
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if ((TARGET_VIS || REGNO (operands[0]) < 32)
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&& const_zero_operand (operands[1], <V32:MODE>mode))
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goto movsf_is_ok;
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/* We are able to build any SF constant in integer registers
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with at most 2 instructions. */
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if (REGNO (operands[0]) < 32
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&& <V32:MODE>mode == SFmode)
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goto movsf_is_ok;
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operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
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operands[1]));
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}
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/* Handle sets of MEM first. */
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if (GET_CODE (operands[0]) == MEM)
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{
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if (register_or_zero_operand (operands[1], <V32:MODE>mode))
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goto movsf_is_ok;
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if (! reload_in_progress)
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{
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operands[0] = validize_mem (operands[0]);
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operands[1] = force_reg (<V32:MODE>mode, operands[1]);
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}
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}
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/* Fixup PIC cases. */
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if (flag_pic)
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{
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if (CONSTANT_P (operands[1])
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&& pic_address_needs_scratch (operands[1]))
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operands[1] = legitimize_pic_address (operands[1], <V32:MODE>mode, 0);
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if (symbolic_operand (operands[1], <V32:MODE>mode))
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{
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operands[1] = legitimize_pic_address (operands[1],
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<V32:MODE>mode,
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(reload_in_progress ?
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operands[0] :
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NULL_RTX));
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}
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}
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movsf_is_ok:
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;
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})
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(define_insn "*movsf_insn"
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[(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,*r,f,m,m")
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(match_operand:V32 1 "input_operand" "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
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@ -2676,68 +2741,7 @@
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[(set (match_dup 0) (high:SF (match_dup 1)))
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(set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
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;; Yes, you guessed it right, the former movsf expander.
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(define_expand "mov<V32:mode>"
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[(set (match_operand:V32 0 "general_operand" "")
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(match_operand:V32 1 "general_operand" ""))]
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"<V32:MODE>mode == SFmode || TARGET_VIS"
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{
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/* Force constants into memory. */
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if (GET_CODE (operands[0]) == REG && CONSTANT_P (operands[1]))
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{
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/* emit_group_store will send such bogosity to us when it is
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not storing directly into memory. So fix this up to avoid
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crashes in output_constant_pool. */
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if (operands [1] == const0_rtx)
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operands[1] = CONST0_RTX (<V32:MODE>mode);
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if ((TARGET_VIS || REGNO (operands[0]) < 32)
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&& const_zero_operand (operands[1], <V32:MODE>mode))
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goto movsf_is_ok;
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/* We are able to build any SF constant in integer registers
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with at most 2 instructions. */
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if (REGNO (operands[0]) < 32
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&& <V32:MODE>mode == SFmode)
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goto movsf_is_ok;
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operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
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operands[1]));
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}
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||||
|
||||
/* Handle sets of MEM first. */
|
||||
if (GET_CODE (operands[0]) == MEM)
|
||||
{
|
||||
if (register_or_zero_operand (operands[1], <V32:MODE>mode))
|
||||
goto movsf_is_ok;
|
||||
|
||||
if (! reload_in_progress)
|
||||
{
|
||||
operands[0] = validize_mem (operands[0]);
|
||||
operands[1] = force_reg (<V32:MODE>mode, operands[1]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Fixup PIC cases. */
|
||||
if (flag_pic)
|
||||
{
|
||||
if (CONSTANT_P (operands[1])
|
||||
&& pic_address_needs_scratch (operands[1]))
|
||||
operands[1] = legitimize_pic_address (operands[1], <V32:MODE>mode, 0);
|
||||
|
||||
if (symbolic_operand (operands[1], <V32:MODE>mode))
|
||||
{
|
||||
operands[1] = legitimize_pic_address (operands[1],
|
||||
<V32:MODE>mode,
|
||||
(reload_in_progress ?
|
||||
operands[0] :
|
||||
NULL_RTX));
|
||||
}
|
||||
}
|
||||
|
||||
movsf_is_ok:
|
||||
;
|
||||
})
|
||||
(define_mode_macro V64 [DF V2SI V4HI V8QI])
|
||||
|
||||
;; Yes, you again guessed it right, the former movdf expander.
|
||||
(define_expand "mov<V64:mode>"
|
||||
@ -2840,23 +2844,6 @@
|
||||
[(set_attr "type" "load,store,*,*,*")
|
||||
(set_attr "length" "*,*,2,2,2")])
|
||||
|
||||
(define_insn "*movdf_insn_sp32_v9_no_fpu"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
|
||||
(match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))]
|
||||
"! TARGET_FPU
|
||||
&& TARGET_V9
|
||||
&& ! TARGET_ARCH64
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| register_or_zero_operand (operands[1], DFmode))"
|
||||
"@
|
||||
ldd\t%1, %0
|
||||
std\t%1, %0
|
||||
stx\t%r1, %0
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "load,store,store,*,*")
|
||||
(set_attr "length" "*,*,*,2,2")])
|
||||
|
||||
;; We have available v9 double floats but not 64-bit integer registers.
|
||||
(define_insn "*movdf_insn_sp32_v9"
|
||||
[(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
|
||||
@ -2881,6 +2868,23 @@
|
||||
(set_attr "length" "*,*,*,*,*,*,*,2,2,2")
|
||||
(set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
|
||||
|
||||
(define_insn "*movdf_insn_sp32_v9_no_fpu"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
|
||||
(match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))]
|
||||
"! TARGET_FPU
|
||||
&& TARGET_V9
|
||||
&& ! TARGET_ARCH64
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| register_or_zero_operand (operands[1], DFmode))"
|
||||
"@
|
||||
ldd\t%1, %0
|
||||
std\t%1, %0
|
||||
stx\t%r1, %0
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "load,store,store,*,*")
|
||||
(set_attr "length" "*,*,*,2,2")])
|
||||
|
||||
;; We have available both v9 double floats and 64-bit integer registers.
|
||||
(define_insn "*movdf_insn_sp64"
|
||||
[(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
|
||||
@ -3217,6 +3221,17 @@
|
||||
"#"
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
(define_insn "*movtf_insn_sp64"
|
||||
[(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
|
||||
(match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
|
||||
"TARGET_FPU
|
||||
&& TARGET_ARCH64
|
||||
&& ! TARGET_HARD_QUAD
|
||||
&& (register_operand (operands[0], TFmode)
|
||||
|| register_or_zero_operand (operands[1], TFmode))"
|
||||
"#"
|
||||
[(set_attr "length" "2")])
|
||||
|
||||
(define_insn "*movtf_insn_sp64_hq"
|
||||
[(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r")
|
||||
(match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
|
||||
@ -3235,17 +3250,6 @@
|
||||
[(set_attr "type" "*,fpmove,fpload,fpstore,*,*")
|
||||
(set_attr "length" "2,*,*,*,2,2")])
|
||||
|
||||
(define_insn "*movtf_insn_sp64"
|
||||
[(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
|
||||
(match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
|
||||
"TARGET_FPU
|
||||
&& TARGET_ARCH64
|
||||
&& ! TARGET_HARD_QUAD
|
||||
&& (register_operand (operands[0], TFmode)
|
||||
|| register_or_zero_operand (operands[1], TFmode))"
|
||||
"#"
|
||||
[(set_attr "length" "2")])
|
||||
|
||||
(define_insn "*movtf_insn_sp64_no_fpu"
|
||||
[(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
|
||||
(match_operand:TF 1 "input_operand" "orG,rG"))]
|
||||
@ -3373,8 +3377,9 @@
|
||||
gen_df_reg (set_src, 1)));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; SPARC V9 conditional move instructions.
|
||||
|
||||
|
||||
;; SPARC-V9 conditional move instructions.
|
||||
|
||||
;; We can handle larger constants here for some flavors, but for now we keep
|
||||
;; it simple and only allow those constants supported by all flavors.
|
||||
@ -3865,7 +3870,7 @@
|
||||
[(set_attr "length" "2")])
|
||||
|
||||
|
||||
;;- zero extension instructions
|
||||
;; Zero-extension instructions
|
||||
|
||||
;; These patterns originally accepted general_operands, however, slightly
|
||||
;; better code is generated by only accepting register_operands, and then
|
||||
@ -3981,7 +3986,6 @@
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "us3load_type" "3cycle")])
|
||||
|
||||
|
||||
;; ??? Write truncdisi pattern using sra?
|
||||
|
||||
(define_expand "zero_extendsidi2"
|
||||
@ -4145,7 +4149,8 @@
|
||||
"andcc\t%1, 0xff, %0"
|
||||
[(set_attr "type" "compare")])
|
||||
|
||||
;;- sign extension instructions
|
||||
|
||||
;; Sign-extension instructions
|
||||
|
||||
;; These patterns originally accepted general_operands, however, slightly
|
||||
;; better code is generated by only accepting register_operands, and then
|
||||
@ -4330,7 +4335,8 @@
|
||||
ldsw\t%1, %0"
|
||||
[(set_attr "type" "shift,sload")
|
||||
(set_attr "us3load_type" "*,3cycle")])
|
||||
|
||||
|
||||
|
||||
;; Special pattern for optimizing bit-field compares. This is needed
|
||||
;; because combine uses this as a canonical form.
|
||||
|
||||
@ -4367,7 +4373,8 @@
|
||||
return "andcc\t%0, %1, %%g0";
|
||||
}
|
||||
[(set_attr "type" "compare")])
|
||||
|
||||
|
||||
|
||||
;; Conversions between float, double and long double.
|
||||
|
||||
(define_insn "extendsfdf2"
|
||||
@ -4447,7 +4454,8 @@
|
||||
"TARGET_FPU && TARGET_HARD_QUAD"
|
||||
"fqtod\t%1, %0"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
|
||||
|
||||
;; Conversion between fixed point and floating point.
|
||||
|
||||
(define_insn "floatsisf2"
|
||||
@ -4621,7 +4629,8 @@
|
||||
"TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
|
||||
"emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
|
||||
|
||||
;; Integer Addition/Subtraction.
|
||||
|
||||
;; Integer addition/subtraction instructions.
|
||||
|
||||
(define_expand "adddi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
@ -4967,8 +4976,9 @@
|
||||
"TARGET_ARCH64"
|
||||
"subcc\t%1, %2, %0"
|
||||
[(set_attr "type" "compare")])
|
||||
|
||||
;; Integer Multiply/Divide.
|
||||
|
||||
|
||||
;; Integer multiply/divide instructions.
|
||||
|
||||
;; The 32 bit multiply/divide instructions are deprecated on v9, but at
|
||||
;; least in UltraSPARC I, II and IIi it is a win tick-wise.
|
||||
@ -5632,8 +5642,10 @@
|
||||
"TARGET_SPARCLET"
|
||||
"umacd\t%1, %2, %L0"
|
||||
[(set_attr "type" "imul")])
|
||||
|
||||
;; Boolean instructions
|
||||
|
||||
|
||||
;; Boolean instructions.
|
||||
|
||||
;; We define DImode `and' so with DImode `not' we can get
|
||||
;; DImode `andn'. Other combinations are possible.
|
||||
|
||||
@ -6331,7 +6343,8 @@
|
||||
"TARGET_ARCH64"
|
||||
"orcc\t%1, 0, %0"
|
||||
[(set_attr "type" "compare")])
|
||||
|
||||
|
||||
|
||||
;; Floating point arithmetic instructions.
|
||||
|
||||
(define_expand "addtf3"
|
||||
@ -6691,8 +6704,9 @@
|
||||
"TARGET_FPU"
|
||||
"fsqrts\t%1, %0"
|
||||
[(set_attr "type" "fpsqrts")])
|
||||
|
||||
;;- arithmetic shift instructions
|
||||
|
||||
|
||||
;; Arithmetic shift instructions.
|
||||
|
||||
(define_insn "ashlsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
@ -6990,8 +7004,10 @@
|
||||
return "srlx\t%1, %2, %0";
|
||||
}
|
||||
[(set_attr "type" "shift")])
|
||||
|
||||
;; Unconditional and other jump instructions
|
||||
|
||||
|
||||
;; Unconditional and other jump instructions.
|
||||
|
||||
(define_insn "jump"
|
||||
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
||||
""
|
||||
@ -7034,7 +7050,9 @@
|
||||
"jmp\t%a0%#"
|
||||
[(set_attr "type" "uncond_branch")])
|
||||
|
||||
;;- jump to subroutine
|
||||
|
||||
;; Jump to subroutine instructions.
|
||||
|
||||
(define_expand "call"
|
||||
;; Note that this expression is not used for generating RTL.
|
||||
;; All the RTL is generated explicitly below.
|
||||
@ -7293,7 +7311,8 @@
|
||||
DONE;
|
||||
})
|
||||
|
||||
;;- tail calls
|
||||
;; Tail call instructions.
|
||||
|
||||
(define_expand "sibcall"
|
||||
[(parallel [(call (match_operand 0 "call_operand" "") (const_int 0))
|
||||
(return)])]
|
||||
@ -7341,13 +7360,8 @@
|
||||
"* return output_sibcall(insn, operands[1]);"
|
||||
[(set_attr "type" "sibcall")])
|
||||
|
||||
(define_expand "sibcall_epilogue"
|
||||
[(return)]
|
||||
""
|
||||
{
|
||||
sparc_expand_epilogue ();
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Special instructions.
|
||||
|
||||
(define_expand "prologue"
|
||||
[(const_int 0)]
|
||||
@ -7381,6 +7395,14 @@
|
||||
sparc_expand_epilogue ();
|
||||
})
|
||||
|
||||
(define_expand "sibcall_epilogue"
|
||||
[(return)]
|
||||
""
|
||||
{
|
||||
sparc_expand_epilogue ();
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "return"
|
||||
[(return)]
|
||||
"sparc_can_use_return_insn_p ()"
|
||||
@ -7650,8 +7672,8 @@
|
||||
{ return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
|
||||
[(set_attr "type" "iflush")])
|
||||
|
||||
|
||||
;; find first set.
|
||||
|
||||
;; Find first set instructions.
|
||||
|
||||
;; The scan instruction searches from the most significant bit while ffs
|
||||
;; searches from the least significant bit. The bit index and treatment of
|
||||
@ -7847,6 +7869,9 @@
|
||||
(compare:CCX (match_dup 1) (const_int 0)))])]
|
||||
"")
|
||||
|
||||
|
||||
;; Prefetch instructions.
|
||||
|
||||
;; ??? UltraSPARC-III note: A memory operation loading into the floating point register
|
||||
;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory
|
||||
;; ??? operations. With DFA we might be able to model this, but it requires a lot of
|
||||
@ -7913,7 +7938,10 @@
|
||||
return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
|
||||
}
|
||||
[(set_attr "type" "load")])
|
||||
|
||||
|
||||
|
||||
;; Trap instructions.
|
||||
|
||||
(define_insn "trap"
|
||||
[(trap_if (const_int 1) (const_int 5))]
|
||||
""
|
||||
@ -7949,7 +7977,9 @@
|
||||
"t%C0\t%%xcc, %1"
|
||||
[(set_attr "type" "trap")])
|
||||
|
||||
;; TLS support
|
||||
|
||||
;; TLS support instructions.
|
||||
|
||||
(define_insn "tgd_hi22"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(high:SI (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")]
|
||||
@ -8512,6 +8542,7 @@
|
||||
"stx\t%0, [%1 + %2], %%tldo_add(%3)"
|
||||
[(set_attr "type" "store")])
|
||||
|
||||
|
||||
;; Vector instructions.
|
||||
|
||||
(define_insn "addv2si3"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user