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Libatomic: AArch64: Convert all lse128 assembly to .insn directives
Given the lack of support for the LSE128 instructions in all but the the most up-to-date version of Binutils (2.42), having the build-time test for assembler support for these instructions often leads to the building of Libatomic without support for LSE128-dependent atomic function implementations. This ultimately leads to different people having different versions of Libatomic on their machines, depending on which assembler was available at compilation time. Furthermore, the conditional inclusion of these atomic function implementations predicated on assembler support leads to a series of `#if HAVE_FEAT_LSE128' guards scattered throughout the codebase and the need for a series of aliases when the feature flag evaluates to false. The preprocessor macro guards, together with the conditional aliasing leads to code that is cumbersome to understand and maintain. Both of the issues highlighted above will only get worse with the coming support for LRCPC3 atomics which under the current scheme will also require build-time checks. Consequently, a better option for both consistency across builds and code cleanness is to make recourse to the `.inst' directive. By replacing all novel assembly instructions for their hexadecimal representation within `.inst's, we ensure that the Libatomic code is both considerably cleaner and all machines build the same binary, irrespective of binutils version available at compile time. This patch therefore removes all configure checks for LSE128-support in the assembler and all the guards and aliases that were associated with `HAVE_FEAT_LSE128' libatomic/ChangeLog: * acinclude.m4 (LIBAT_TEST_FEAT_AARCH64_LSE128): Delete. * auto-config.h.in (HAVE_FEAT_LSE128): Likewise * config/linux/aarch64/atomic_16.S: Replace all LSE128 instructions with equivalent `.inst' directives. (HAVE_FEAT_LSE128): Remove all references. * configure: Regenerate. * configure.ac: Remove call to LIBAT_TEST_FEAT_AARCH64_LSE128.
This commit is contained in:
Victor Do Nascimento
parent
cf5f9171ba
commit
f6b9a064a2
@ -83,24 +83,6 @@ AC_DEFUN([LIBAT_TEST_ATOMIC_BUILTIN],[
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])
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])
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dnl
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dnl Test if the host assembler supports armv9.4-a LSE128 isns.
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dnl
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AC_DEFUN([LIBAT_TEST_FEAT_AARCH64_LSE128],[
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AC_CACHE_CHECK([for armv9.4-a LSE128 insn support],
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[libat_cv_have_feat_lse128],[
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AC_LANG_CONFTEST([AC_LANG_PROGRAM([],[asm(".arch armv9-a+lse128")])])
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if AC_TRY_EVAL(ac_compile); then
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eval libat_cv_have_feat_lse128=yes
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else
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eval libat_cv_have_feat_lse128=no
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fi
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rm -f conftest*
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])
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LIBAT_DEFINE_YESNO([HAVE_FEAT_LSE128], [$libat_cv_have_feat_lse128],
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[Have LSE128 support for 16 byte integers.])
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])
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dnl
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dnl Test if we have __atomic_load and __atomic_store for mode $1, size $2
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dnl
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@ -105,9 +105,6 @@
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/* Define to 1 if you have the <dlfcn.h> header file. */
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#undef HAVE_DLFCN_H
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/* Have LSE128 support for 16 byte integers. */
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#undef HAVE_FEAT_LSE128
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/* Define to 1 if you have the <fenv.h> header file. */
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#undef HAVE_FENV_H
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@ -40,18 +40,9 @@
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#include "auto-config.h"
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#if !HAVE_IFUNC
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# undef HAVE_FEAT_LSE128
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# define HAVE_FEAT_LSE128 0
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#endif
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#define HAVE_FEAT_LSE2 HAVE_IFUNC
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#if HAVE_FEAT_LSE128
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.arch armv9-a+lse128
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#else
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.arch armv8-a+lse
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#endif
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#define LSE128(NAME) libat_##NAME##_i1
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#define LSE2(NAME) libat_##NAME##_i2
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@ -226,7 +217,6 @@ ENTRY (exchange_16)
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END (exchange_16)
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#if HAVE_FEAT_LSE128
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ENTRY_FEAT (exchange_16, LSE128)
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mov tmp0, x0
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mov res0, in0
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@ -234,21 +224,23 @@ ENTRY_FEAT (exchange_16, LSE128)
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cbnz w4, 1f
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/* RELAXED. */
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swpp res0, res1, [tmp0]
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/* swpp res0, res1, [tmp0] */
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.inst 0x192180c0
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ret
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1:
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cmp w4, ACQUIRE
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b.hi 2f
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/* ACQUIRE/CONSUME. */
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swppa res0, res1, [tmp0]
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/* swppa res0, res1, [tmp0] */
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.inst 0x19a180c0
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ret
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/* RELEASE/ACQ_REL/SEQ_CST. */
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2: swppal res0, res1, [tmp0]
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2: /* swppal res0, res1, [tmp0] */
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.inst 0x19e180c0
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ret
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END_FEAT (exchange_16, LSE128)
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#endif
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ENTRY (compare_exchange_16)
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@ -446,7 +438,6 @@ ENTRY (fetch_or_16)
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END (fetch_or_16)
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#if HAVE_FEAT_LSE128
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ENTRY_FEAT (fetch_or_16, LSE128)
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mov tmp0, x0
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mov res0, in0
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@ -454,21 +445,23 @@ ENTRY_FEAT (fetch_or_16, LSE128)
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cbnz w4, 1f
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/* RELAXED. */
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ldsetp res0, res1, [tmp0]
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/* ldsetp res0, res1, [tmp0] */
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.inst 0x192130c0
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ret
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1:
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cmp w4, ACQUIRE
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b.hi 2f
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/* ACQUIRE/CONSUME. */
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ldsetpa res0, res1, [tmp0]
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/* ldsetpa res0, res1, [tmp0] */
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.inst 0x19a130c0
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ret
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/* RELEASE/ACQ_REL/SEQ_CST. */
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2: ldsetpal res0, res1, [tmp0]
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2: /* ldsetpal res0, res1, [tmp0] */
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.inst 0x19e130c0
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ret
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END_FEAT (fetch_or_16, LSE128)
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#endif
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ENTRY (or_fetch_16)
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@ -493,14 +486,14 @@ ENTRY (or_fetch_16)
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END (or_fetch_16)
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#if HAVE_FEAT_LSE128
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ENTRY_FEAT (or_fetch_16, LSE128)
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cbnz w4, 1f
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mov tmp0, in0
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mov tmp1, in1
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/* RELAXED. */
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ldsetp in0, in1, [x0]
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/* ldsetp in0, in1, [x0] */
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.inst 0x19233002
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orr res0, in0, tmp0
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orr res1, in1, tmp1
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ret
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@ -509,18 +502,19 @@ ENTRY_FEAT (or_fetch_16, LSE128)
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b.hi 2f
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/* ACQUIRE/CONSUME. */
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ldsetpa in0, in1, [x0]
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/* ldsetpa in0, in1, [x0] */
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.inst 0x19a33002
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orr res0, in0, tmp0
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orr res1, in1, tmp1
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ret
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/* RELEASE/ACQ_REL/SEQ_CST. */
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2: ldsetpal in0, in1, [x0]
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2: /* ldsetpal in0, in1, [x0] */
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.inst 0x19e33002
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orr res0, in0, tmp0
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orr res1, in1, tmp1
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ret
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END_FEAT (or_fetch_16, LSE128)
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#endif
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ENTRY (fetch_and_16)
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@ -545,7 +539,6 @@ ENTRY (fetch_and_16)
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END (fetch_and_16)
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#if HAVE_FEAT_LSE128
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ENTRY_FEAT (fetch_and_16, LSE128)
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mov tmp0, x0
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mvn res0, in0
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@ -553,7 +546,8 @@ ENTRY_FEAT (fetch_and_16, LSE128)
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cbnz w4, 1f
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/* RELAXED. */
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ldclrp res0, res1, [tmp0]
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/* ldclrp res0, res1, [tmp0] */
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.inst 0x192110c0
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ret
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1:
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@ -561,14 +555,15 @@ ENTRY_FEAT (fetch_and_16, LSE128)
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b.hi 2f
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/* ACQUIRE/CONSUME. */
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ldclrpa res0, res1, [tmp0]
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/* ldclrpa res0, res1, [tmp0] */
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.inst 0x19a110c0
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ret
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/* RELEASE/ACQ_REL/SEQ_CST. */
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2: ldclrpal res0, res1, [tmp0]
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2: /* ldclrpal res0, res1, [tmp0] */
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.inst 0x19e110c0
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ret
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END_FEAT (fetch_and_16, LSE128)
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#endif
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ENTRY (and_fetch_16)
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@ -593,14 +588,14 @@ ENTRY (and_fetch_16)
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END (and_fetch_16)
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#if HAVE_FEAT_LSE128
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ENTRY_FEAT (and_fetch_16, LSE128)
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mvn tmp0, in0
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mvn tmp0, in1
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cbnz w4, 1f
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/* RELAXED. */
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ldclrp tmp0, tmp1, [x0]
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/* ldclrp tmp0, tmp1, [x0] */
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.inst 0x19271006
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and res0, tmp0, in0
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and res1, tmp1, in1
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ret
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@ -610,18 +605,19 @@ ENTRY_FEAT (and_fetch_16, LSE128)
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b.hi 2f
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/* ACQUIRE/CONSUME. */
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ldclrpa tmp0, tmp1, [x0]
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/* ldclrpa tmp0, tmp1, [x0] */
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.inst 0x19a71006
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and res0, tmp0, in0
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and res1, tmp1, in1
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ret
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/* RELEASE/ACQ_REL/SEQ_CST. */
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2: ldclrpal tmp0, tmp1, [x5]
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2: /* ldclrpal tmp0, tmp1, [x5] */
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.inst 0x19e710a6
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and res0, tmp0, in0
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and res1, tmp1, in1
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ret
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END_FEAT (and_fetch_16, LSE128)
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#endif
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ENTRY (fetch_xor_16)
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@ -729,16 +725,9 @@ ENTRY (test_and_set_16)
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END (test_and_set_16)
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/* Alias entry points which are the same in LSE2 and LSE128. */
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#if HAVE_IFUNC
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# if !HAVE_FEAT_LSE128
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ALIAS (exchange_16, LSE128, LSE2)
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ALIAS (fetch_or_16, LSE128, LSE2)
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ALIAS (fetch_and_16, LSE128, LSE2)
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ALIAS (or_fetch_16, LSE128, LSE2)
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ALIAS (and_fetch_16, LSE128, LSE2)
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# endif
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/* Alias entry points which are the same in LSE2 and LSE128. */
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ALIAS (load_16, LSE128, LSE2)
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ALIAS (store_16, LSE128, LSE2)
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ALIAS (compare_exchange_16, LSE128, LSE2)
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@ -753,7 +742,6 @@ ALIAS (nand_fetch_16, LSE128, LSE2)
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ALIAS (test_and_set_16, LSE128, LSE2)
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/* Alias entry points which are the same in baseline and LSE2. */
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ALIAS (exchange_16, LSE2, CORE)
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ALIAS (fetch_add_16, LSE2, CORE)
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ALIAS (add_fetch_16, LSE2, CORE)
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43
libatomic/configure
vendored
43
libatomic/configure
vendored
@ -14697,49 +14697,6 @@ _ACEOF
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# Check for target-specific assembly-level support for atomic operations.
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for armv9.4-a LSE128 insn support" >&5
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$as_echo_n "checking for armv9.4-a LSE128 insn support... " >&6; }
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if ${libat_cv_have_feat_lse128+:} false; then :
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$as_echo_n "(cached) " >&6
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else
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cat confdefs.h - <<_ACEOF >conftest.$ac_ext
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/* end confdefs.h. */
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int
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main ()
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{
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asm(".arch armv9-a+lse128")
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;
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return 0;
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}
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_ACEOF
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if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
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(eval $ac_compile) 2>&5
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ac_status=$?
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$as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
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test $ac_status = 0; }; then
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eval libat_cv_have_feat_lse128=yes
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else
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eval libat_cv_have_feat_lse128=no
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fi
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rm -f conftest*
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fi
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libat_cv_have_feat_lse128" >&5
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$as_echo "$libat_cv_have_feat_lse128" >&6; }
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yesno=`echo $libat_cv_have_feat_lse128 | tr 'yesno' '1 0 '`
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cat >>confdefs.h <<_ACEOF
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#define HAVE_FEAT_LSE128 $yesno
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_ACEOF
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5
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$as_echo_n "checking whether byte ordering is bigendian... " >&6; }
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if ${ac_cv_c_bigendian+:} false; then :
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@ -206,9 +206,6 @@ LIBAT_FORALL_MODES([LIBAT_HAVE_ATOMIC_CAS])
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LIBAT_FORALL_MODES([LIBAT_HAVE_ATOMIC_FETCH_ADD])
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LIBAT_FORALL_MODES([LIBAT_HAVE_ATOMIC_FETCH_OP])
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# Check for target-specific assembly-level support for atomic operations.
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LIBAT_TEST_FEAT_AARCH64_LSE128()
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AC_C_BIGENDIAN
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# I don't like the default behaviour of WORDS_BIGENDIAN undefined for LE.
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AH_BOTTOM(
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