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xtensa: use pre- and postincrement FP load/store when available

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Earlier versions of xtensa FPU used to support preincrement FP load and
store instructions (lsiu/ssiu). Recent FPU supports postincrement FP
load and store instructions only (lsip/ssip). Use configuration macro to
decide which version is available.

2014-10-14  Max Filippov  <jcmvbkbc@gmail.com>

gcc/
    * config/xtensa/xtensa.h (TARGET_HARD_FLOAT_POSTINC): new macro.
    * config/xtensa/xtensa.md (*lsiu, *ssiu): add dependency on
    !TARGET_HARD_FLOAT_POSTINC.
    (*lsip, *ssip): new instructions.

From-SVN: r216234
This commit is contained in:
Max Filippov 2014-10-15 04:20:03 +00:00 committed by Max Filippov
parent cf14ea9fe3
commit f211daa3d5
3 changed files with 45 additions and 2 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2014-10-14 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa.h (TARGET_HARD_FLOAT_POSTINC): new macro.
* config/xtensa/xtensa.md (*lsiu, *ssiu): add dependency on
!TARGET_HARD_FLOAT_POSTINC.
(*lsip, *ssip): new instructions.
2014-10-14 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa.md (divsf3, *recipsf2, sqrtsf2, *rsqrtsf2):

4
gcc/config/xtensa/xtensa.h
View File

@ -39,6 +39,9 @@ extern unsigned xtensa_current_frame_size;
#ifndef XCHAL_HAVE_THREADPTR
#define XCHAL_HAVE_THREADPTR 0
#endif
#ifndef XCHAL_HAVE_FP_POSTINC
#define XCHAL_HAVE_FP_POSTINC 0
#endif
#define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
#define TARGET_DENSITY XCHAL_HAVE_DENSITY
#define TARGET_MAC16 XCHAL_HAVE_MAC16
@ -55,6 +58,7 @@ extern unsigned xtensa_current_frame_size;
#define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
#define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
#define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
#define TARGET_HARD_FLOAT_POSTINC XCHAL_HAVE_FP_POSTINC
#define TARGET_ABS XCHAL_HAVE_ABS
#define TARGET_ADDX XCHAL_HAVE_ADDX
#define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC

36
gcc/config/xtensa/xtensa.md
View File

@ -922,7 +922,7 @@
(match_operand:SI 2 "fpmem_offset_operand" "i"))))
(set (match_dup 1)
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT"
"TARGET_HARD_FLOAT && !TARGET_HARD_FLOAT_POSTINC"
{
if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
output_asm_insn ("memw", operands);
@ -938,7 +938,7 @@
(match_operand:SF 2 "register_operand" "f"))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_dup 1)))]
"TARGET_HARD_FLOAT"
"TARGET_HARD_FLOAT && !TARGET_HARD_FLOAT_POSTINC"
{
if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
output_asm_insn ("memw", operands);
@ -948,6 +948,38 @@
(set_attr "mode" "SF")
(set_attr "length" "3")])
(define_insn "*lsip"
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (match_operand:SI 1 "register_operand" "+a")))
(set (match_dup 1)
(plus:SI (match_dup 1)
(match_operand:SI 2 "fpmem_offset_operand" "i")))]
"TARGET_HARD_FLOAT && TARGET_HARD_FLOAT_POSTINC"
{
if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
output_asm_insn ("memw", operands);
return "lsip\t%0, %1, %2";
}
[(set_attr "type" "fload")
(set_attr "mode" "SF")
(set_attr "length" "3")])
(define_insn "*ssip"
[(set (mem:SF (match_operand:SI 0 "register_operand" "+a"))
(match_operand:SF 1 "register_operand" "f"))
(set (match_dup 0)
(plus:SI (match_dup 0)
(match_operand:SI 2 "fpmem_offset_operand" "i")))]
"TARGET_HARD_FLOAT && TARGET_HARD_FLOAT_POSTINC"
{
if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
output_asm_insn ("memw", operands);
return "ssip\t%1, %0, %2";
}
[(set_attr "type" "fstore")
(set_attr "mode" "SF")
(set_attr "length" "3")])
;; 64-bit floating point moves
(define_expand "movdf"