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[PATCH v2] RISC-V: Remove float vector eqne pattern
We can unify eqne and other comparison operations. Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns (*pred_eqne<mode>_scalar_merge_tie_mask): Ditto (*pred_eqne<mode>_scalar): Ditto (*pred_eqne<mode>_scalar_narrow): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test.
This commit is contained in:
demin.han
Jeff Law
parent
e03583e7ee
commit
f0204ae386
@ -1420,12 +1420,8 @@ public:
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switch (e.op_info->op)
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{
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case OP_TYPE_vf: {
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if (CODE == EQ || CODE == NE)
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return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
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e.vector_mode ()));
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else
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return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
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e.vector_mode ()));
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return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
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e.vector_mode ()));
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}
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case OP_TYPE_vv: {
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return e.use_compare_insn (CODE,
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@ -7545,92 +7545,6 @@
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(set_attr "mode" "<MODE>")
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(set_attr "spec_restriction" "none,thv,thv,none,none")])
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(define_expand "@pred_eqne<mode>_scalar"
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[(set (match_operand:<VM> 0 "register_operand")
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(if_then_else:<VM>
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand")
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(match_operand 6 "vector_length_operand")
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(match_operand 7 "const_int_operand")
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(match_operand 8 "const_int_operand")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(match_operator:<VM> 3 "equality_operator"
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[(vec_duplicate:V_VLSF
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(match_operand:<VEL> 5 "register_operand"))
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(match_operand:V_VLSF 4 "register_operand")])
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(match_operand:<VM> 2 "vector_merge_operand")))]
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"TARGET_VECTOR"
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{})
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(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
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[(set (match_operand:<VM> 0 "register_operand" "=vm")
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(if_then_else:<VM>
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(unspec:<VM>
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[(match_operand:<VM> 1 "register_operand" " 0")
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(match_operand 5 "vector_length_operand" " rK")
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(match_operand 6 "const_int_operand" " i")
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(match_operand 7 "const_int_operand" " i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(match_operator:<VM> 2 "equality_operator"
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[(vec_duplicate:V_VLSF
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(match_operand:<VEL> 4 "register_operand" " f"))
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(match_operand:V_VLSF 3 "register_operand" " vr")])
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(match_dup 1)))]
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"TARGET_VECTOR"
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"vmf%B2.vf\t%0,%3,%4,v0.t"
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[(set_attr "type" "vfcmp")
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(set_attr "mode" "<MODE>")
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(set_attr "merge_op_idx" "1")
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(set_attr "vl_op_idx" "5")
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(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
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(set (attr "avl_type_idx") (const_int 7))])
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;; We don't use early-clobber for LMUL <= 1 to get better codegen.
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(define_insn "*pred_eqne<mode>_scalar"
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[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
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(if_then_else:<VM>
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
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(match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(match_operator:<VM> 3 "equality_operator"
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[(vec_duplicate:V_VLSF
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(match_operand:<VEL> 5 "register_operand" " f, f, f, f"))
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(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")])
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(match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
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"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
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"vmf%B3.vf\t%0,%4,%5%p1"
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[(set_attr "type" "vfcmp")
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(set_attr "mode" "<MODE>")
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(set_attr "spec_restriction" "thv,thv,rvv,rvv")])
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;; We use early-clobber for source LMUL > dest LMUL.
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(define_insn "*pred_eqne<mode>_scalar_narrow"
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[(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
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(if_then_else:<VM>
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
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(match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
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(match_operand 7 "const_int_operand" " i, i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(match_operator:<VM> 3 "equality_operator"
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[(vec_duplicate:V_VLSF
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(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
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(match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
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(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
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"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
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"vmf%B3.vf\t%0,%4,%5%p1"
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[(set_attr "type" "vfcmp")
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(set_attr "mode" "<MODE>")
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(set_attr "spec_restriction" "none,thv,thv,none,none")])
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;; -------------------------------------------------------------------------------
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;; ---- Predicated floating-point merge
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;; -------------------------------------------------------------------------------
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@ -0,0 +1,54 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
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#include "riscv_vector.h"
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#define CMP_FLOAT_VF_1(ID, S, OP, IMM) \
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vbool##S##_t test_float_1_##ID##_##S (vfloat##S##m1_t op1, size_t vl) \
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{ \
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return __riscv_vmf##OP##_vf_f##S##m1_b##S (op1, IMM, vl); \
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}
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CMP_FLOAT_VF_1 (0, 32, eq, 0.0)
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CMP_FLOAT_VF_1 (1, 32, eq, 1.0)
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CMP_FLOAT_VF_1 (2, 32, eq, __builtin_nanf ("123"))
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CMP_FLOAT_VF_1 (3, 32, ne, 0.0)
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CMP_FLOAT_VF_1 (4, 32, ne, 1.0)
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CMP_FLOAT_VF_1 (5, 32, ne, __builtin_nanf ("123"))
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CMP_FLOAT_VF_1 (0, 64, eq, 0.0)
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CMP_FLOAT_VF_1 (1, 64, eq, 1.0)
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CMP_FLOAT_VF_1 (2, 64, eq, __builtin_nan ("123"))
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CMP_FLOAT_VF_1 (3, 64, ne, 0.0)
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CMP_FLOAT_VF_1 (4, 64, ne, 1.0)
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CMP_FLOAT_VF_1 (5, 64, ne, __builtin_nan ("123"))
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#define CMP_FLOAT_VF_2(ID, S, OP, IMM) \
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vfloat##S##m1_t test_float_2_##ID##_##S (vfloat##S##m1_t op1, \
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vfloat##S##m1_t op2, size_t vl) \
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{ \
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vfloat##S##m1_t op3 = __riscv_vfmv_s_f_f##S##m1 (IMM, vl); \
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vbool##S##_t mask1 = __riscv_vmf##OP##_vf_f##S##m1_b##S (op1, IMM, vl); \
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vbool##S##_t mask2 = __riscv_vmf##OP##_vv_f##S##m1_b##S (op1, op3, vl); \
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vbool##S##_t mask3 = __riscv_vmor (mask1, mask2, vl); \
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return __riscv_vmerge_vvm_f##S##m1_tu (op1, op1, op2, mask3, vl); \
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}
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CMP_FLOAT_VF_2 (0, 32, eq, 0.0)
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CMP_FLOAT_VF_2 (1, 32, eq, 1.0)
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CMP_FLOAT_VF_2 (2, 32, eq, __builtin_nanf ("123"))
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CMP_FLOAT_VF_2 (3, 32, ne, 0.0)
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CMP_FLOAT_VF_2 (4, 32, ne, 1.0)
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CMP_FLOAT_VF_2 (5, 32, ne, __builtin_nanf ("123"))
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CMP_FLOAT_VF_2 (0, 64, eq, 0.0)
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CMP_FLOAT_VF_2 (1, 64, eq, 1.0)
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CMP_FLOAT_VF_2 (2, 64, eq, __builtin_nan ("123"))
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CMP_FLOAT_VF_2 (3, 64, ne, 0.0)
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CMP_FLOAT_VF_2 (4, 64, ne, 1.0)
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CMP_FLOAT_VF_2 (5, 64, ne, __builtin_nan ("123"))
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/* { dg-final { scan-assembler-times {vmfeq\.vf} 12 } } */
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/* { dg-final { scan-assembler-times {vmfne\.vf} 12 } } */
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/* { dg-final { scan-assembler-times {vmfeq\.vv} 6 } } */
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/* { dg-final { scan-assembler-times {vmfne\.vv} 6 } } */
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