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2014-10-31  Andrew Pinski  <apinski@cavium.com>

	* config/mips/mips-cpus.def (octeon3): New cpu.
	* config/mips/mips.c (mips_rtx_cost_data): Add octeon3.
	(mips_print_operand <case 'T', case 't'>): Fix a bug as the mode
	of the comparison no longer matches mode of the operands.
	(mips_issue_rate): Handle PROCESSOR_OCTEON3.
	* config/mips/mips.h (TARGET_OCTEON):  Add Octeon3.
	(TARGET_OCTEON2): Likewise.
	(TUNE_OCTEON): Add Octeon3.
	* config/mips/mips.md (processor): Add octeon3.
	* config/mips/octeon.md (octeon_fpu): New automaton and cpu_unit.
	(octeon_arith): Add octeon3.
	(octeon_condmove): Remove.
	(octeon_condmove_o1): New reservation.
	(octeon_condmove_o2): New reservation.
	(octeon_condmove_o3_int_on_cc): New reservation.
	(octeon_load_o2): Add octeon3.
	(octeon_cop_o2): Likewise.
	(octeon_store): Likewise.
	(octeon_brj_o2): Likewise.
	(octeon_imul3_o2): Likewise.
	(octeon_imul_o2): Likewise.
	(octeon_mfhilo_o2): Likewise.
	(octeon_imadd_o2): Likewise.
	(octeon_idiv_o2_si): Likewise.
	(octeon_idiv_o2_di): Likewise.
	(octeon_fpu): Add to the automaton.
	(octeon_fpu): New cpu unit.
	(octeon_condmove_o2): Check for non floating point modes.
	(octeon_load_o2): Add prefetchx.
	(octeon_cop_o2): Don't check for octeon3.
	(octeon3_faddsubcvt): New reservation.
	(octeon3_fmul): Likewise.
	(octeon3_fmadd): Likewise.
	(octeon3_div_sf): Likewise.
	(octeon3_div_df): Likewise.
	(octeon3_sqrt_sf): Likewise.
	(octeon3_sqrt_df): Likewise.
	(octeon3_rsqrt_sf): Likewise.
	(octeon3_rsqrt_df): Likewise.
	(octeon3_fabsnegmov): Likewise.
	(octeon_fcond): Likewise.
	(octeon_fcondmov): Likewise.
	(octeon_fpmtc1): Likewise.
	(octeon_fpmfc1): Likewise.
	(octeon_fpload): Likewise.
	(octeon_fpstore): Likewise.
	* config/mips/mips-tables.opt: Regenerate.
	* doc/invoke.texi (-march=@var{arch}): Add octeon3.

2014-10-31  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gcc.target/mips/octeon3-pipe-1.c: New test.

From-SVN: r217028
This commit is contained in:
Naveen H.S 2014-11-03 05:13:43 +00:00
parent 81a55f55da
commit ed60a04bbb
9 changed files with 201 additions and 20 deletions
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51
gcc/ChangeLog
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@ -1,3 +1,54 @@
2014-11-03 Andrew Pinski <apinski@cavium.com>
* config/mips/mips-cpus.def (octeon3): New cpu.
* config/mips/mips.c (mips_rtx_cost_data): Add octeon3.
(mips_print_operand <case 'T', case 't'>): Fix a bug as the mode
of the comparison no longer matches mode of the operands.
(mips_issue_rate): Handle PROCESSOR_OCTEON3.
* config/mips/mips.h (TARGET_OCTEON): Add Octeon3.
(TARGET_OCTEON2): Likewise.
(TUNE_OCTEON): Add Octeon3.
* config/mips/mips.md (processor): Add octeon3.
* config/mips/octeon.md (octeon_fpu): New automaton and cpu_unit.
(octeon_arith): Add octeon3.
(octeon_condmove): Remove.
(octeon_condmove_o1): New reservation.
(octeon_condmove_o2): New reservation.
(octeon_condmove_o3_int_on_cc): New reservation.
(octeon_load_o2): Add octeon3.
(octeon_cop_o2): Likewise.
(octeon_store): Likewise.
(octeon_brj_o2): Likewise.
(octeon_imul3_o2): Likewise.
(octeon_imul_o2): Likewise.
(octeon_mfhilo_o2): Likewise.
(octeon_imadd_o2): Likewise.
(octeon_idiv_o2_si): Likewise.
(octeon_idiv_o2_di): Likewise.
(octeon_fpu): Add to the automaton.
(octeon_fpu): New cpu unit.
(octeon_condmove_o2): Check for non floating point modes.
(octeon_load_o2): Add prefetchx.
(octeon_cop_o2): Don't check for octeon3.
(octeon3_faddsubcvt): New reservation.
(octeon3_fmul): Likewise.
(octeon3_fmadd): Likewise.
(octeon3_div_sf): Likewise.
(octeon3_div_df): Likewise.
(octeon3_sqrt_sf): Likewise.
(octeon3_sqrt_df): Likewise.
(octeon3_rsqrt_sf): Likewise.
(octeon3_rsqrt_df): Likewise.
(octeon3_fabsnegmov): Likewise.
(octeon_fcond): Likewise.
(octeon_fcondmov): Likewise.
(octeon_fpmtc1): Likewise.
(octeon_fpmfc1): Likewise.
(octeon_fpload): Likewise.
(octeon_fpstore): Likewise.
* config/mips/mips-tables.opt: Regenerate.
* doc/invoke.texi (-march=@var{arch}): Add octeon3.
2014-11-03 Zhenqiang Chen <zhenqiang.chen@arm.com>
* ifcvt.c (noce_emit_cmove, noce_get_alt_condition, noce_get_condition):

1
gcc/config/mips/mips-cpus.def
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@ -162,4 +162,5 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY)

5
gcc/config/mips/mips-tables.opt
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@ -667,5 +667,8 @@ EnumValue
Enum(mips_arch_opt_value) String(octeon2) Value(94) Canonical
EnumValue
Enum(mips_arch_opt_value) String(xlp) Value(95) Canonical
Enum(mips_arch_opt_value) String(octeon3) Value(95) Canonical
EnumValue
Enum(mips_arch_opt_value) String(xlp) Value(96) Canonical

15
gcc/config/mips/mips.c
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@ -975,6 +975,20 @@ static const struct mips_rtx_cost_data
COSTS_N_INSNS (35), /* int_div_di */
4, /* branch_cost */
4 /* memory_latency */
},
/* Octeon III */
{
COSTS_N_INSNS (6), /* fp_add */
COSTS_N_INSNS (6), /* fp_mult_sf */
COSTS_N_INSNS (7), /* fp_mult_df */
COSTS_N_INSNS (25), /* fp_div_sf */
COSTS_N_INSNS (48), /* fp_div_df */
COSTS_N_INSNS (6), /* int_mult_si */
COSTS_N_INSNS (6), /* int_mult_di */
COSTS_N_INSNS (18), /* int_div_si */
COSTS_N_INSNS (35), /* int_div_di */
4, /* branch_cost */
4 /* memory_latency */
},
{ /* R3900 */
COSTS_N_INSNS (2), /* fp_add */
@ -13177,6 +13191,7 @@ mips_issue_rate (void)
case PROCESSOR_R9000:
case PROCESSOR_OCTEON:
case PROCESSOR_OCTEON2:
case PROCESSOR_OCTEON3:
return 2;
case PROCESSOR_SB1:

9
gcc/config/mips/mips.h
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@ -230,8 +230,10 @@ struct mips_cpu_info {
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
|| mips_arch == PROCESSOR_OCTEON2)
#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
|| mips_arch == PROCESSOR_OCTEON2 \
|| mips_arch == PROCESSOR_OCTEON3)
#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
|| mips_arch == PROCESSOR_OCTEON3)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
|| mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
@ -261,7 +263,8 @@ struct mips_cpu_info {
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
|| mips_tune == PROCESSOR_OCTEON2)
|| mips_tune == PROCESSOR_OCTEON2 \
|| mips_tune == PROCESSOR_OCTEON3)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)
#define TUNE_P5600 (mips_tune == PROCESSOR_P5600)

1
gcc/config/mips/mips.md
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@ -41,6 +41,7 @@
m4k
octeon
octeon2
octeon3
r3900
r6000
r4000

133
gcc/config/mips/octeon.md
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@ -22,41 +22,55 @@
;; Octeon is a dual-issue processor that can issue all instructions on
;; pipe0 and a subset on pipe1.
(define_automaton "octeon_main, octeon_mult")
(define_automaton "octeon_main, octeon_mult, octeon_fpu")
(define_cpu_unit "octeon_pipe0" "octeon_main")
(define_cpu_unit "octeon_pipe1" "octeon_main")
(define_cpu_unit "octeon_mult" "octeon_mult")
(define_cpu_unit "octeon_fpu" "octeon_fpu")
(define_insn_reservation "octeon_arith" 1
(and (eq_attr "cpu" "octeon,octeon2")
(and (eq_attr "cpu" "octeon,octeon2,octeon3")
(eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
"octeon_pipe0 | octeon_pipe1")
(define_insn_reservation "octeon_condmove" 2
(and (eq_attr "cpu" "octeon,octeon2")
(define_insn_reservation "octeon_condmove_o1" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "condmove"))
"octeon_pipe0 | octeon_pipe1")
(define_insn_reservation "octeon_condmove_o2" 3
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "condmove")
(not (eq_attr "mode" "SF, DF")))
"octeon_pipe0 | octeon_pipe1")
;; movt/movf can only issue in pipe1
(define_insn_reservation "octeon_condmove_o3_int_on_cc" 3
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "condmove")
(not (eq_attr "mode" "SF, DF")))
"octeon_pipe1")
(define_insn_reservation "octeon_load_o1" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "load,prefetch,mtc,mfc"))
"octeon_pipe0")
(define_insn_reservation "octeon_load_o2" 3
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "load,prefetch"))
"octeon_pipe0")
;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency.
;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now.
(define_insn_reservation "octeon_cop_o2" 1
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "mtc,mfc"))
"octeon_pipe1")
(define_insn_reservation "octeon_store" 1
(and (eq_attr "cpu" "octeon,octeon2")
(and (eq_attr "cpu" "octeon,octeon2,octeon3")
(eq_attr "type" "store"))
"octeon_pipe0")
@ -66,7 +80,7 @@
"octeon_pipe0")
(define_insn_reservation "octeon_brj_o2" 2
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "branch,jump,call,trap"))
"octeon_pipe1")
@ -76,7 +90,7 @@
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
(define_insn_reservation "octeon_imul3_o2" 6
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "imul3,pop,clz"))
"octeon_pipe1 + octeon_mult")
@ -86,7 +100,7 @@
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
(define_insn_reservation "octeon_imul_o2" 1
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "imul,mthi,mtlo"))
"octeon_pipe1 + octeon_mult")
@ -96,7 +110,7 @@
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
(define_insn_reservation "octeon_mfhilo_o2" 6
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "mfhi,mflo"))
"octeon_pipe1 + octeon_mult")
@ -106,7 +120,7 @@
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
(define_insn_reservation "octeon_imadd_o2" 1
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "type" "imadd"))
"octeon_pipe1 + octeon_mult")
@ -116,13 +130,13 @@
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
(define_insn_reservation "octeon_idiv_o2_si" 18
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "mode" "SI")
(eq_attr "type" "idiv"))
"octeon_pipe1 + octeon_mult, octeon_mult*17")
(define_insn_reservation "octeon_idiv_o2_di" 35
(and (eq_attr "cpu" "octeon2")
(and (eq_attr "cpu" "octeon2,octeon3")
(eq_attr "mode" "DI")
(eq_attr "type" "idiv"))
"octeon_pipe1 + octeon_mult, octeon_mult*34")
@ -131,6 +145,95 @@
;; patterns.
(define_insn_reservation "octeon_unknown" 1
(and (eq_attr "cpu" "octeon,octeon2")
(and (eq_attr "cpu" "octeon,octeon2,octeon3")
(eq_attr "type" "unknown,multi,atomic,syncloop"))
"octeon_pipe0 + octeon_pipe1")
;; Octeon3 FPU
(define_insn_reservation "octeon3_faddsubcvt" 4
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fadd, fcvt"))
"octeon_pipe1 + octeon_fpu")
(define_insn_reservation "octeon3_fmul" 5
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fmul"))
"octeon_pipe1 + octeon_fpu")
(define_insn_reservation "octeon3_fmadd" 9
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fmadd"))
"octeon_pipe1 + octeon_fpu, octeon_fpu")
(define_insn_reservation "octeon3_div_sf" 12
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fdiv, frdiv")
(eq_attr "mode" "SF"))
"octeon_pipe1 + octeon_fpu, octeon_fpu*8")
(define_insn_reservation "octeon3_div_df" 22
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fdiv, frdiv")
(eq_attr "mode" "SF"))
"octeon_pipe1 + octeon_fpu, octeon_fpu*18")
(define_insn_reservation "octeon3_sqrt_sf" 16
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fsqrt")
(eq_attr "mode" "SF"))
"octeon_pipe1 + octeon_fpu, octeon_fpu*12")
(define_insn_reservation "octeon3_sqrt_df" 30
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fsqrt")
(eq_attr "mode" "DF"))
"octeon_pipe1 + octeon_fpu, octeon_fpu*26")
(define_insn_reservation "octeon3_rsqrt_sf" 27
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "frsqrt")
(eq_attr "mode" "SF"))
"octeon_pipe1 + octeon_fpu, octeon_fpu*23")
(define_insn_reservation "octeon3_rsqrt_df" 51
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "frsqrt")
(eq_attr "mode" "DF"))
"octeon_pipe1 + octeon_fpu, octeon_fpu*47")
(define_insn_reservation "octeon3_fabsnegmov" 2
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fabs, fneg, fmove"))
"octeon_pipe1 + octeon_fpu")
(define_insn_reservation "octeon_fcond" 1
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fcmp"))
"octeon_pipe1 + octeon_fpu")
(define_insn_reservation "octeon_fcondmov" 2
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "condmove")
(eq_attr "mode" "SF,DF"))
"octeon_pipe1 + octeon_fpu")
(define_insn_reservation "octeon_fpmtc1" 2
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "mtc"))
"octeon_pipe1 + octeon_fpu")
(define_insn_reservation "octeon_fpmfc1" 6
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "mtc"))
"octeon_pipe1 + octeon_fpu")
(define_insn_reservation "octeon_fpload" 3
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fpload,fpidxload"))
"octeon_pipe0 + octeon_fpu")
(define_insn_reservation "octeon_fpstore" 3
(and (eq_attr "cpu" "octeon3")
(eq_attr "type" "fpstore,fpidxstore"))
"octeon_pipe0 + octeon_pipe1")

2
gcc/doc/invoke.texi
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@ -17531,7 +17531,7 @@ The processor names are:
@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
@samp{m4k},
@samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec},
@samp{octeon}, @samp{octeon+}, @samp{octeon2},
@samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3},
@samp{orion},
@samp{p5600},
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2014-11-03 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gcc.target/mips/octeon3-pipe-1.c: New test.
2014-11-02 Uros Bizjak <ubizjak@gmail.com>
* g++.dg/cpp0x/gen-attrs-42.C: Add x86_64-*-* target.