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rx.md: Add peepholes and patterns to combine extending loads and simple arithmetic...
* config/rx/rx.md: Add peepholes and patterns to combine extending loads and simple arithmetic instructions. * config/rx/rx.h (ADJUST_INSN_LENGTH): Define. * config/rx/rx-protos.h (rx_adjust_insn_length): Prototype. * config/rx/rx.c (rx_is_legitimate_address): Allow QI and HI modes to use pre-decrement and post-increment addressing. (rx_is_restricted_memory_address): Add range checking of REG+INT addresses. (rx_print_operand): Add support for %Q. Fix handling of %Q. (rx_memory_move_cost): Adjust cost of stores. (rx_adjust_insn_length): New function. From-SVN: r171724
This commit is contained in:
parent
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commit
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@ -1,3 +1,18 @@
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2011-03-30 Nick Clifton <nickc@redhat.com>
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* config/rx/rx.md: Add peepholes and patterns to combine
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extending loads and simple arithmetic instructions.
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* config/rx/rx.h (ADJUST_INSN_LENGTH): Define.
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* config/rx/rx-protos.h (rx_adjust_insn_length): Prototype.
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* config/rx/rx.c (rx_is_legitimate_address): Allow QI and HI
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modes to use pre-decrement and post-increment addressing.
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(rx_is_restricted_memory_address): Add range checking of REG+INT
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addresses.
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(rx_print_operand): Add support for %Q.
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Fix handling of %Q.
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(rx_memory_move_cost): Adjust cost of stores.
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(rx_adjust_insn_length): New function.
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2011-03-30 Jakub Jelinek <jakub@redhat.com>
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2011-03-30 Jakub Jelinek <jakub@redhat.com>
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PR c/48305
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PR c/48305
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@ -31,16 +31,17 @@ extern void rx_expand_prologue (void);
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extern int rx_initial_elimination_offset (int, int);
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extern int rx_initial_elimination_offset (int, int);
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#ifdef RTX_CODE
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#ifdef RTX_CODE
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extern int rx_adjust_insn_length (rtx, int);
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extern void rx_emit_stack_popm (rtx *, bool);
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extern void rx_emit_stack_popm (rtx *, bool);
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extern void rx_emit_stack_pushm (rtx *);
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extern void rx_emit_stack_pushm (rtx *);
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extern void rx_expand_epilogue (bool);
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extern void rx_expand_epilogue (bool);
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extern char * rx_gen_move_template (rtx *, bool);
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extern char * rx_gen_move_template (rtx *, bool);
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extern bool rx_is_legitimate_constant (rtx);
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extern bool rx_is_legitimate_constant (rtx);
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extern bool rx_is_restricted_memory_address (rtx, Mmode);
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extern bool rx_is_restricted_memory_address (rtx, Mmode);
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extern bool rx_match_ccmode (rtx, Mmode);
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extern void rx_notice_update_cc (rtx body, rtx insn);
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extern void rx_notice_update_cc (rtx body, rtx insn);
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extern void rx_split_cbranch (Mmode, Rcode, rtx, rtx, rtx);
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extern void rx_split_cbranch (Mmode, Rcode, rtx, rtx, rtx);
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extern Mmode rx_select_cc_mode (Rcode, rtx, rtx);
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extern Mmode rx_select_cc_mode (Rcode, rtx, rtx);
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extern bool rx_match_ccmode (rtx, Mmode);
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#endif
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#endif
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#endif /* GCC_RX_PROTOS_H */
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#endif /* GCC_RX_PROTOS_H */
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@ -86,7 +86,7 @@ rx_is_legitimate_address (Mmode mode, rtx x, bool strict ATTRIBUTE_UNUSED)
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/* Register Indirect. */
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/* Register Indirect. */
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return true;
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return true;
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if (GET_MODE_SIZE (mode) == 4
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if (GET_MODE_SIZE (mode) <= 4
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&& (GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC))
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&& (GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC))
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/* Pre-decrement Register Indirect or
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/* Pre-decrement Register Indirect or
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Post-increment Register Indirect. */
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Post-increment Register Indirect. */
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@ -126,7 +126,7 @@ rx_is_legitimate_address (Mmode mode, rtx x, bool strict ATTRIBUTE_UNUSED)
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case 1: factor = 1; break;
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case 1: factor = 1; break;
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}
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}
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if (val > (65535 * factor))
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if (val >= (0x10000 * factor))
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return false;
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return false;
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return (val % factor) == 0;
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return (val % factor) == 0;
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}
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}
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@ -167,8 +167,6 @@ rx_is_legitimate_address (Mmode mode, rtx x, bool strict ATTRIBUTE_UNUSED)
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bool
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bool
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rx_is_restricted_memory_address (rtx mem, enum machine_mode mode)
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rx_is_restricted_memory_address (rtx mem, enum machine_mode mode)
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{
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{
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rtx base, index;
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if (! rx_is_legitimate_address
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if (! rx_is_legitimate_address
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(mode, mem, reload_in_progress || reload_completed))
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(mode, mem, reload_in_progress || reload_completed))
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return false;
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return false;
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@ -184,11 +182,18 @@ rx_is_restricted_memory_address (rtx mem, enum machine_mode mode)
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return false;
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return false;
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case PLUS:
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case PLUS:
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{
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rtx base, index;
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/* Only allow REG+INT addressing. */
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/* Only allow REG+INT addressing. */
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base = XEXP (mem, 0);
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base = XEXP (mem, 0);
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index = XEXP (mem, 1);
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index = XEXP (mem, 1);
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return RX_REG_P (base) && CONST_INT_P (index);
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if (! RX_REG_P (base) || ! CONST_INT_P (index))
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return false;
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return IN_RANGE (INTVAL (index), 0, (0x10000 * GET_MODE_SIZE (mode)) - 1);
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}
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case SYMBOL_REF:
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case SYMBOL_REF:
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/* Can happen when small data is being supported.
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/* Can happen when small data is being supported.
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@ -387,11 +392,14 @@ rx_assemble_integer (rtx x, unsigned int size, int is_aligned)
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%L Print low part of a DImode register, integer or address.
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%L Print low part of a DImode register, integer or address.
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%N Print the negation of the immediate value.
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%N Print the negation of the immediate value.
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%Q If the operand is a MEM, then correctly generate
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%Q If the operand is a MEM, then correctly generate
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register indirect or register relative addressing. */
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register indirect or register relative addressing.
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%R Like %Q but for zero-extending loads. */
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static void
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static void
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rx_print_operand (FILE * file, rtx op, int letter)
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rx_print_operand (FILE * file, rtx op, int letter)
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{
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{
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bool unsigned_load = false;
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switch (letter)
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switch (letter)
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{
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{
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case 'A':
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case 'A':
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@ -451,6 +459,7 @@ rx_print_operand (FILE * file, rtx op, int letter)
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else
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else
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{
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{
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unsigned int flags = flags_from_mode (mode);
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unsigned int flags = flags_from_mode (mode);
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switch (code)
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switch (code)
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{
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{
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case LT:
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case LT:
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@ -589,10 +598,15 @@ rx_print_operand (FILE * file, rtx op, int letter)
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rx_print_integer (file, - INTVAL (op));
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rx_print_integer (file, - INTVAL (op));
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break;
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break;
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case 'R':
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gcc_assert (GET_MODE_SIZE (GET_MODE (op)) < 4);
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unsigned_load = true;
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/* Fall through. */
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case 'Q':
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case 'Q':
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if (MEM_P (op))
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if (MEM_P (op))
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{
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{
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HOST_WIDE_INT offset;
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HOST_WIDE_INT offset;
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rtx mem = op;
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op = XEXP (op, 0);
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op = XEXP (op, 0);
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@ -627,22 +641,24 @@ rx_print_operand (FILE * file, rtx op, int letter)
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rx_print_operand (file, op, 0);
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rx_print_operand (file, op, 0);
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fprintf (file, "].");
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fprintf (file, "].");
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switch (GET_MODE_SIZE (GET_MODE (op)))
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switch (GET_MODE_SIZE (GET_MODE (mem)))
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{
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{
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case 1:
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case 1:
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gcc_assert (offset < 65535 * 1);
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gcc_assert (offset <= 65535 * 1);
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fprintf (file, "B");
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fprintf (file, unsigned_load ? "UB" : "B");
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break;
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break;
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case 2:
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case 2:
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gcc_assert (offset % 2 == 0);
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gcc_assert (offset % 2 == 0);
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gcc_assert (offset < 65535 * 2);
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gcc_assert (offset <= 65535 * 2);
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fprintf (file, "W");
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fprintf (file, unsigned_load ? "UW" : "W");
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break;
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break;
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default:
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case 4:
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gcc_assert (offset % 4 == 0);
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gcc_assert (offset % 4 == 0);
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gcc_assert (offset < 65535 * 4);
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gcc_assert (offset <= 65535 * 4);
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fprintf (file, "L");
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fprintf (file, "L");
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break;
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break;
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default:
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gcc_unreachable ();
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}
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}
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break;
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break;
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}
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}
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@ -2449,8 +2465,7 @@ rx_is_legitimate_constant (rtx x)
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default:
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default:
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/* FIXME: Can this ever happen ? */
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/* FIXME: Can this ever happen ? */
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abort ();
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gcc_unreachable ();
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return false;
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}
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}
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break;
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break;
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@ -2593,7 +2608,7 @@ rx_trampoline_init (rtx tramp, tree fndecl, rtx chain)
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static int
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static int
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rx_memory_move_cost (enum machine_mode mode, reg_class_t regclass, bool in)
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rx_memory_move_cost (enum machine_mode mode, reg_class_t regclass, bool in)
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{
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{
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return 2 + memory_move_secondary_cost (mode, regclass, in);
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return (in ? 2 : 0) + memory_move_secondary_cost (mode, regclass, in);
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}
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}
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/* Convert a CC_MODE to the set of flags that it represents. */
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/* Convert a CC_MODE to the set of flags that it represents. */
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@ -2778,6 +2793,113 @@ rx_max_skip_for_label (rtx lab)
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return opsize - 1;
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return opsize - 1;
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return 0;
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return 0;
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}
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}
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/* Compute the real length of the extending load-and-op instructions. */
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int
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rx_adjust_insn_length (rtx insn, int current_length)
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{
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rtx extend, mem, offset;
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bool zero;
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int factor;
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switch (INSN_CODE (insn))
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{
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default:
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return current_length;
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case CODE_FOR_plussi3_zero_extendhi:
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case CODE_FOR_andsi3_zero_extendhi:
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case CODE_FOR_iorsi3_zero_extendhi:
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case CODE_FOR_xorsi3_zero_extendhi:
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case CODE_FOR_divsi3_zero_extendhi:
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case CODE_FOR_udivsi3_zero_extendhi:
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case CODE_FOR_minussi3_zero_extendhi:
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case CODE_FOR_smaxsi3_zero_extendhi:
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case CODE_FOR_sminsi3_zero_extendhi:
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case CODE_FOR_multsi3_zero_extendhi:
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case CODE_FOR_comparesi3_zero_extendqi:
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zero = true;
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factor = 2;
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break;
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case CODE_FOR_plussi3_sign_extendhi:
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case CODE_FOR_andsi3_sign_extendhi:
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case CODE_FOR_iorsi3_sign_extendhi:
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case CODE_FOR_xorsi3_sign_extendhi:
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case CODE_FOR_divsi3_sign_extendhi:
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case CODE_FOR_udivsi3_sign_extendhi:
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case CODE_FOR_minussi3_sign_extendhi:
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case CODE_FOR_smaxsi3_sign_extendhi:
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case CODE_FOR_sminsi3_sign_extendhi:
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case CODE_FOR_multsi3_sign_extendhi:
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case CODE_FOR_comparesi3_zero_extendhi:
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zero = false;
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factor = 2;
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break;
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case CODE_FOR_plussi3_zero_extendqi:
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case CODE_FOR_andsi3_zero_extendqi:
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case CODE_FOR_iorsi3_zero_extendqi:
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case CODE_FOR_xorsi3_zero_extendqi:
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case CODE_FOR_divsi3_zero_extendqi:
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case CODE_FOR_udivsi3_zero_extendqi:
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case CODE_FOR_minussi3_zero_extendqi:
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case CODE_FOR_smaxsi3_zero_extendqi:
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case CODE_FOR_sminsi3_zero_extendqi:
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case CODE_FOR_multsi3_zero_extendqi:
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case CODE_FOR_comparesi3_sign_extendqi:
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zero = true;
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factor = 1;
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break;
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case CODE_FOR_plussi3_sign_extendqi:
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case CODE_FOR_andsi3_sign_extendqi:
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case CODE_FOR_iorsi3_sign_extendqi:
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case CODE_FOR_xorsi3_sign_extendqi:
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case CODE_FOR_divsi3_sign_extendqi:
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case CODE_FOR_udivsi3_sign_extendqi:
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case CODE_FOR_minussi3_sign_extendqi:
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case CODE_FOR_smaxsi3_sign_extendqi:
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case CODE_FOR_sminsi3_sign_extendqi:
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case CODE_FOR_multsi3_sign_extendqi:
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case CODE_FOR_comparesi3_sign_extendhi:
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zero = false;
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factor = 1;
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break;
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}
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/* We are expecting: (SET (REG) (<OP> (REG) (<EXTEND> (MEM)))). */
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extend = single_set (insn);
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gcc_assert (extend != NULL_RTX);
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extend = SET_SRC (extend);
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if (GET_CODE (XEXP (extend, 0)) == ZERO_EXTEND
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|| GET_CODE (XEXP (extend, 0)) == SIGN_EXTEND)
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extend = XEXP (extend, 0);
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else
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extend = XEXP (extend, 1);
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gcc_assert ((zero && (GET_CODE (extend) == ZERO_EXTEND))
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|| (! zero && (GET_CODE (extend) == SIGN_EXTEND)));
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mem = XEXP (extend, 0);
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gcc_checking_assert (MEM_P (mem));
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if (REG_P (XEXP (mem, 0)))
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return (zero && factor == 1) ? 2 : 3;
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/* We are expecting: (MEM (PLUS (REG) (CONST_INT))). */
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gcc_checking_assert (GET_CODE (XEXP (mem, 0)) == PLUS);
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gcc_checking_assert (REG_P (XEXP (XEXP (mem, 0), 0)));
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offset = XEXP (XEXP (mem, 0), 1);
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gcc_checking_assert (GET_CODE (offset) == CONST_INT);
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if (IN_RANGE (INTVAL (offset), 0, 255 * factor))
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return (zero && factor == 1) ? 3 : 4;
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return (zero && factor == 1) ? 4 : 5;
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}
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#undef TARGET_ASM_JUMP_ALIGN_MAX_SKIP
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#undef TARGET_ASM_JUMP_ALIGN_MAX_SKIP
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#define TARGET_ASM_JUMP_ALIGN_MAX_SKIP rx_max_skip_for_label
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#define TARGET_ASM_JUMP_ALIGN_MAX_SKIP rx_max_skip_for_label
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@ -630,3 +630,10 @@ typedef unsigned int CUMULATIVE_ARGS;
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#define REGISTER_MOVE_COST(MODE,FROM,TO) 2
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#define REGISTER_MOVE_COST(MODE,FROM,TO) 2
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#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode(OP, X, Y)
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#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode(OP, X, Y)
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#define ADJUST_INSN_LENGTH(INSN,LENGTH) \
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do \
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{ \
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(LENGTH) = rx_adjust_insn_length ((INSN), (LENGTH)); \
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} \
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while (0)
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@ -1545,6 +1545,139 @@
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(set_attr "length" "3,4,5,6,7,6")]
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(set_attr "length" "3,4,5,6,7,6")]
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)
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)
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;; A set of peepholes to catch extending loads followed by arithmetic operations.
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;; We use iterators where possible to reduce the amount of typing and hence the
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;; possibilities for typos.
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(define_code_iterator extend_types [(zero_extend "") (sign_extend "")])
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(define_code_attr letter [(zero_extend "R") (sign_extend "Q")])
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(define_code_iterator memex_commutative [(plus "") (and "") (ior "") (xor "")])
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(define_code_iterator memex_noncomm [(div "") (udiv "") (minus "")])
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(define_code_iterator memex_nocc [(smax "") (smin "") (mult "")])
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|
|
||||||
|
(define_code_attr op [(plus "add") (and "and") (div "div") (udiv "divu") (smax "max") (smin "min") (mult "mul") (ior "or") (minus "sub") (xor "xor")])
|
||||||
|
|
||||||
|
(define_peephole2
|
||||||
|
[(set (match_operand:SI 0 "register_operand")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
|
||||||
|
(parallel [(set (match_operand:SI 2 "register_operand")
|
||||||
|
(memex_commutative:SI (match_dup 0)
|
||||||
|
(match_dup 2)))
|
||||||
|
(clobber (reg:CC CC_REG))])]
|
||||||
|
"peep2_regno_dead_p (2, REGNO (operands[0]))"
|
||||||
|
[(parallel [(set:SI (match_dup 2)
|
||||||
|
(memex_commutative:SI (match_dup 2)
|
||||||
|
(extend_types:SI (match_dup 1))))
|
||||||
|
(clobber (reg:CC CC_REG))])]
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_peephole2
|
||||||
|
[(set (match_operand:SI 0 "register_operand")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
|
||||||
|
(parallel [(set (match_operand:SI 2 "register_operand")
|
||||||
|
(memex_commutative:SI (match_dup 2)
|
||||||
|
(match_dup 0)))
|
||||||
|
(clobber (reg:CC CC_REG))])]
|
||||||
|
"peep2_regno_dead_p (2, REGNO (operands[0]))"
|
||||||
|
[(parallel [(set:SI (match_dup 2)
|
||||||
|
(memex_commutative:SI (match_dup 2)
|
||||||
|
(extend_types:SI (match_dup 1))))
|
||||||
|
(clobber (reg:CC CC_REG))])]
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_peephole2
|
||||||
|
[(set (match_operand:SI 0 "register_operand")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
|
||||||
|
(parallel [(set (match_operand:SI 2 "register_operand")
|
||||||
|
(memex_noncomm:SI (match_dup 2)
|
||||||
|
(match_dup 0)))
|
||||||
|
(clobber (reg:CC CC_REG))])]
|
||||||
|
"peep2_regno_dead_p (2, REGNO (operands[0]))"
|
||||||
|
[(parallel [(set:SI (match_dup 2)
|
||||||
|
(memex_noncomm:SI (match_dup 2)
|
||||||
|
(extend_types:SI (match_dup 1))))
|
||||||
|
(clobber (reg:CC CC_REG))])]
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_peephole2
|
||||||
|
[(set (match_operand:SI 0 "register_operand")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
|
||||||
|
(set (match_operand:SI 2 "register_operand")
|
||||||
|
(memex_nocc:SI (match_dup 0)
|
||||||
|
(match_dup 2)))]
|
||||||
|
"peep2_regno_dead_p (2, REGNO (operands[0]))"
|
||||||
|
[(set:SI (match_dup 2)
|
||||||
|
(memex_nocc:SI (match_dup 2)
|
||||||
|
(extend_types:SI (match_dup 1))))]
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_peephole2
|
||||||
|
[(set (match_operand:SI 0 "register_operand")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
|
||||||
|
(set (match_operand:SI 2 "register_operand")
|
||||||
|
(memex_nocc:SI (match_dup 2)
|
||||||
|
(match_dup 0)))]
|
||||||
|
"peep2_regno_dead_p (2, REGNO (operands[0]))"
|
||||||
|
[(set:SI (match_dup 2)
|
||||||
|
(memex_nocc:SI (match_dup 2)
|
||||||
|
(extend_types:SI (match_dup 1))))]
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_insn "<memex_commutative:code>si3_<extend_types:code><small_int_modes:mode>"
|
||||||
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(memex_commutative:SI (match_operand:SI 1 "register_operand" "%0")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
|
||||||
|
(clobber (reg:CC CC_REG))]
|
||||||
|
""
|
||||||
|
"<memex_commutative:op>\t%<extend_types:letter>2, %0"
|
||||||
|
[(set_attr "timings" "33")
|
||||||
|
(set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_insn "<memex_noncomm:code>si3_<extend_types:code><small_int_modes:mode>"
|
||||||
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(memex_noncomm:SI (match_operand:SI 1 "register_operand" "0")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
|
||||||
|
(clobber (reg:CC CC_REG))]
|
||||||
|
""
|
||||||
|
"<memex_noncomm:op>\t%<extend_types:letter>2, %0"
|
||||||
|
[(set_attr "timings" "33")
|
||||||
|
(set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_insn "<memex_nocc:code>si3_<extend_types:code><small_int_modes:mode>"
|
||||||
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(memex_nocc:SI (match_operand:SI 1 "register_operand" "%0")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))]
|
||||||
|
""
|
||||||
|
"<memex_nocc:op>\t%<extend_types:letter>2, %0"
|
||||||
|
[(set_attr "timings" "33")
|
||||||
|
(set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_peephole2
|
||||||
|
[(set (match_operand:SI 0 "register_operand")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
|
||||||
|
(set (reg:CC CC_REG)
|
||||||
|
(compare:CC (match_operand:SI 2 "register_operand")
|
||||||
|
(match_dup 0)))]
|
||||||
|
"peep2_regno_dead_p (2, REGNO (operands[0]))"
|
||||||
|
[(set (reg:CC CC_REG)
|
||||||
|
(compare:CC (match_dup 2)
|
||||||
|
(extend_types:SI (match_dup 1))))]
|
||||||
|
)
|
||||||
|
|
||||||
|
(define_insn "comparesi3_<extend_types:code><small_int_modes:mode>"
|
||||||
|
[(set (reg:CC CC_REG)
|
||||||
|
(compare:CC (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand" "Q"))))]
|
||||||
|
""
|
||||||
|
"cmp\t%<extend_types:letter>1, %0"
|
||||||
|
[(set_attr "timings" "33")
|
||||||
|
(set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
|
||||||
|
)
|
||||||
|
|
||||||
;; Floating Point Instructions
|
;; Floating Point Instructions
|
||||||
|
|
||||||
(define_insn "addsf3"
|
(define_insn "addsf3"
|
||||||
@ -1897,14 +2030,6 @@
|
|||||||
rtx addr2 = gen_rtx_REG (SImode, 2);
|
rtx addr2 = gen_rtx_REG (SImode, 2);
|
||||||
rtx len = gen_rtx_REG (SImode, 3);
|
rtx len = gen_rtx_REG (SImode, 3);
|
||||||
|
|
||||||
/* Do not use when the source or destination are volatile - the SMOVF
|
|
||||||
instruction will read and write in word sized blocks, which may be
|
|
||||||
outside of the valid address range. */
|
|
||||||
if (MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
|
|
||||||
FAIL;
|
|
||||||
if (MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))
|
|
||||||
FAIL;
|
|
||||||
|
|
||||||
if (REG_P (operands[0]) && (REGNO (operands[0]) == 2
|
if (REG_P (operands[0]) && (REGNO (operands[0]) == 2
|
||||||
|| REGNO (operands[0]) == 3))
|
|| REGNO (operands[0]) == 3))
|
||||||
FAIL;
|
FAIL;
|
||||||
|
Loading…
Reference in New Issue
Block a user