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i370.c (mvs_add_label): Change spacing for coding conventions.
* i370.c (mvs_add_label): Change spacing for coding conventions.
* i370.h (ASM_OUTPUT_CASE_LABEL): Change to the data CSECT for the
outputing case vectors.
(ASM_OUTPUT_CASE_END): New, put assembler back into code CSECT.
(ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Remove page check,
since vector in in the data CSECT.
(ASM_OUTPUT_REG_POP, ASM_OUTPUT_REG_PUSH): Restore to correct operation. * i370.md (Many patterns): Put the length in the XL directives.
(movdi): Put back STM and MVC in definition.
(floatsidf2): Correct TARGET_ELF_ABI pattern and add back the LE370
pattern using the TCA.
* oe.h (CPP_SPEC): Added to allow trigraphs.
* xm-oe.h (HOST_BITS_PER_LONGLONG): Change to 32. IBM's compiler does
not support the "long long" type.
From-SVN: r33191
This commit is contained in:
Richard Henderson
parent
954869eb3b
commit
e13f6154af
@ -645,7 +645,7 @@ mvs_add_label (id)
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fwd_distance = lp->label_last_ref - lp->label_addr;
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if (mvs_page_code + 2*fwd_distance + mvs_page_lit < 4060) return;
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if (mvs_page_code + 2 * fwd_distance + mvs_page_lit < 4060) return;
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mvs_need_base_reload ++;
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}
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@ -1160,23 +1160,29 @@ enum reg_class
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fprintf (FILE, "%s%d\tEQU\t*\n", PREFIX, NUM); \
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}
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/* Generate case label. */
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/* hack alert -- I don't get it ... what if its a really big case label?
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* wouldn't we have to say label_emitted also ?? */
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/* Generate case label. For HLASM we can change to the data CSECT
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and put the vectors out of the code body. The assembler just
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concatenates CSECTs with the same name. */
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#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \
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fprintf (FILE, "%s%d\tEQU\t*\n", PREFIX, NUM)
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fprintf (FILE, "\tDS\t0F\n"); \
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fprintf (FILE,"\tCSECT\n"); \
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fprintf (FILE, "%s%d\tEQU\t*\n", PREFIX, NUM)
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/* Put the CSECT back to the code body */
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#define ASM_OUTPUT_CASE_END(FILE, NUM, TABLE) \
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assemble_name (FILE, mvs_function_name); \
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fputs ("\tCSECT\n", FILE);
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/* This is how to output an element of a case-vector that is absolute. */
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#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
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mvs_check_page (FILE, 4, 0); \
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fprintf (FILE, "\tDC\tA(L%d)\n", VALUE)
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/* This is how to output an element of a case-vector that is relative. */
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#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
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mvs_check_page (FILE, 4, 0); \
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fprintf (FILE, "\tDC\tA(L%d-L%d)\n", VALUE, REL)
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/* This is how to output an insn to push a register on the stack.
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@ -1188,7 +1194,7 @@ enum reg_class
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#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
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mvs_check_page (FILE, 8, 4); \
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fprintf (FILE, "\tSXXX\t13,=F'4'\n\tST\t%s,%d(13)\n", \
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fprintf (FILE, "\tS\t13,=F'4'\n\tST\t%s,%d(13)\n", \
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reg_names[REGNO], STACK_POINTER_OFFSET)
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/* This is how to output an insn to pop a register from the stack.
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@ -1196,13 +1202,9 @@ enum reg_class
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#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
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mvs_check_page (FILE, 8, 0); \
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fprintf (FILE, "\tL\t%s,%d(13)\n\tLAXXX\t13,4(13)\n", \
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fprintf (FILE, "\tL\t%s,%d(13)\n\tLA\t13,4(13)\n", \
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reg_names[REGNO], STACK_POINTER_OFFSET)
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/* TBD: hack alert XXX these two float point macros print horribly
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incorrect things when run in cross-compiler mode. Thats's because
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in cross-compiler mode, the VALUE is not really a double. See below,
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in the ELF section, for the correct implementation. */
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/* This is how to output an assembler line defining a `double' constant. */
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#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
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fprintf (FILE, "\tDC\tD'%.18G'\n", (VALUE))
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@ -170,7 +170,7 @@
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{
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/* an unsigned compare to zero is always zero/not-zero... */
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mvs_check_page (0, 4, 4);
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return \"N %0,=X'000000FF'\";
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return \"N %0,=XL4'000000FF'\";
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}
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mvs_check_page (0, 4, 0);
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return \"CLI %0,0\";
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@ -189,7 +189,7 @@
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{
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/* an unsigned compare to zero is always zero/not-zero... */
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mvs_check_page (0, 4, 4);
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return \"N %0,=X'000000FF'\";
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return \"N %0,=XL4'000000FF'\";
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}
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mvs_check_page (0, 8, 0);
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return \"SLL %0,24\;SRA %0,24\";
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@ -348,7 +348,7 @@
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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mvs_check_page (0, 4, 1);
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return \"CLM %0,1,=X'%X1'\";
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return \"CLM %0,1,=XL1'%X1'\";
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}
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mvs_check_page (0, 4, 0);
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return \"CLM %0,1,%1\";
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@ -359,7 +359,7 @@
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if (REG_P (operands[1]))
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{
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mvs_check_page (0, 4, 1);
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return \"CLM %1,1,=X'%X0'\";
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return \"CLM %1,1,=XL1'%X0'\";
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}
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mvs_check_page (0, 4, 0);
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return \"CLI %1,%B0\";
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@ -394,7 +394,7 @@
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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mvs_check_page (0, 4, 1);
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return \"CLM %0,1,=X'%X1'\";
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return \"CLM %0,1,=XL1'%X1'\";
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}
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if (!(REG_P (operands[1])))
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{
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@ -648,9 +648,7 @@ check_label_emit ();
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else if (REG_P (operands[1]))
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{
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mvs_check_page (0, 4, 0);
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/* can't use stm otherwise stm r6,r7,0(r10,r13) can happen */
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return \"STM %1,%N1,%0\";
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/* return \"ST %1,%0\;ST %N1,4+%0\"; */
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}
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mvs_check_page (0, 6, 0);
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return \"MVC %O0(8,%R0),%W1\";
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@ -706,17 +704,8 @@ check_label_emit ();
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mvs_check_page (0, 4, 0);
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return \"STD %1,%0\";
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}
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else if (REG_P (operands[1]))
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{
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/* hack alert -- for some reason, %N0 doesn't work
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* when the mem ref is e.g. 168(r13,r1) ...
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* add 4 and pray for the best .. */
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mvs_check_page (0, 8, 0);
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return \"ST %1,%0\;ST %N1,4+%N0\";
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}
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/* this is almost certainly not what is desired, let it break ... */
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mvs_check_page (0, 8, 0);
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return \"xxxST %1,%0\;ST %N1,%N0\";
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mvs_check_page (0, 4, 0);
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return \"STM %1,%N1,%0\";
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}"
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[(set_attr "length" "8")]
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)
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@ -740,16 +729,15 @@ check_label_emit ();
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if (REG_P (operands[0]))
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{
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mvs_check_page (0, 8, 0);
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return \"L %0,%1\;L %N0,4+%N1\";
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return \"LM %0,%N0,%1\";
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}
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else if (REG_P (operands[1]))
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{
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mvs_check_page (0, 8, 0);
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return \"ST %1,%0\;ST %N1,4+%N0\";
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return \"STM %1,%N1,%0\";
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}
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mvs_check_page (0, 6, 0);
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/* should never get here ... */
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return \"xxxxxxMVC %O0(8,%R0),%W1\";
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return \"MVC %O0(8,%R0),%1\";
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}"
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[(set_attr "length" "8")]
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)
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@ -1200,7 +1188,7 @@ check_label_emit ();
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return \"STM %1,%N1,%0\";
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}
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mvs_check_page (0, 6, 0);
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return \"MVC %O0(8,%R0),%W1\";
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return \"MVC %O0(8,%R0),%1\";
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}"
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[(set_attr "length" "12")]
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)
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@ -1715,7 +1703,7 @@ check_label_emit ();
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/* AND only sets zero/not-zero bits not the arithmetic bits ... */
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CC_STATUS_INIT;
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mvs_check_page (0, 4, 4);
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return \"N %1,=X'0000FFFF'\";
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return \"N %1,=XL4'0000FFFF'\";
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}"
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[(set_attr "length" "4")]
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)
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@ -1736,7 +1724,7 @@ check_label_emit ();
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/* AND only sets zero/not-zero bits not the arithmetic bits ... */
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CC_STATUS_INIT;
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mvs_check_page (0, 4, 4);
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return \"N %0,=X'000000FF'\";
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return \"N %0,=XL4'000000FF'\";
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}
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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@ -1766,7 +1754,7 @@ check_label_emit ();
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/* AND only sets zero/not-zero bits not the arithmetic bits ... */
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CC_STATUS_INIT;
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mvs_check_page (0, 4, 4);
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return \"N %0,=X'000000FF'\";
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return \"N %0,=XL4'000000FF'\";
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}
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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@ -1830,6 +1818,8 @@ check_label_emit ();
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;
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; floatsidf2 instruction pattern(s).
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;
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; LE/370 mode uses the float field of the TCA.
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;
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(define_insn "floatsidf2"
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[(set (match_operand:DF 0 "general_operand" "=f")
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@ -1839,10 +1829,15 @@ check_label_emit ();
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{
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check_label_emit ();
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CC_STATUS_INIT;
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#ifdef TARGET_ELF_ABI
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mvs_check_page (0, 22, 12);
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return \"MVC 140(4,13),=XL4'4E000000'\;ST %1,144(,13)\;XI 144(13),128\;LD %0,140(,13)\;SD %0,=XL8'4E00000080000000'\";
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#else
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mvs_check_page (0, 16, 8);
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return \"ST %1,144(,13)\;XI 144(13),128\;LD %0,140(,13)\;SD %0,=XL8'4E00000080000000'\";
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return \"ST %1,508(,12)\;XI 508(12),128\;LD %0,504(,12)\;SD %0,=XL8'4E00000080000000'\";
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#endif
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}"
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[(set_attr "length" "16")]
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[(set_attr "length" "22")]
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)
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;
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@ -2419,7 +2414,7 @@ check_label_emit ();
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/* XXX trouble. Below we generate some rtx's that model what
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* is really supposed to happen with multiply on the 370/390
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* hardware, and that is all well & god. However, during optimization
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* hardware, and that is all well & good. However, during optimization
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* it can happen that the two operands are exchanged (after all,
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* multiplication is commutitive), in which case the doubleword
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* ends up in memory and everything is hosed. The gen_reg_rtx
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@ -3579,7 +3574,7 @@ check_label_emit ();
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return \"X %0,=F'-1'\";
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}
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mvs_check_page (0, 6, 4);
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return \"XC %O0(2,%R0),=X'FFFF'\";
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return \"XC %O0(2,%R0),=XL4'FFFF'\";
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}"
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[(set_attr "length" "6")]
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)
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@ -3867,10 +3862,10 @@ check_label_emit ();
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if (REG_P (operands[2]))
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{
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mvs_check_page (0, 8, 4);
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return \"N %0,=X'0000FFFF'\;SRL %0,0(%2)\";
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return \"N %0,=XL4'0000FFFF'\;SRL %0,0(%2)\";
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}
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mvs_check_page (0, 8, 4);
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return \"N %0,=X'0000FFFF'\;SRL %0,%c2\";
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return \"N %0,=XL4'0000FFFF'\;SRL %0,%c2\";
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}"
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[(set_attr "length" "8")]
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)
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@ -3890,8 +3885,8 @@ check_label_emit ();
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CC_STATUS_INIT; /* AND sets the CC but not how we want it */
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mvs_check_page (0, 8, 4);
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if (REG_P (operands[2]))
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return \"N %0,=X'000000FF'\;SRL %0,0(%2)\";
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return \"N %0,=X'000000FF'\;SRL %0,%c2\";
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return \"N %0,=XL4'000000FF'\;SRL %0,0(%2)\";
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return \"N %0,=XL4'000000FF'\;SRL %0,%c2\";
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}"
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[(set_attr "length" "8")]
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)
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@ -29,6 +29,10 @@ Boston, MA 02111-1307, USA. */
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#define TARGET_EBCDIC 1
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#define TARGET_HLASM 1
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/* Options for the preprocessor for this target machine. */
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#define CPP_SPEC "-trigraphs"
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/* Options for this target machine. */
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#define LIB_SPEC ""
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@ -34,7 +34,7 @@ Boston, MA 02111-1307, USA. */
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#define HOST_BITS_PER_SHORT 16
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#define HOST_BITS_PER_INT 32
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#define HOST_BITS_PER_LONG 32
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#define HOST_BITS_PER_LONGLONG 64
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#define HOST_BITS_PER_LONGLONG 32
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#define HOST_FLOAT_FORMAT IBM_FLOAT_FORMAT
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#define HOST_EBCDIC 1
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