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re PR target/50931 ([avr] Support a 24-bit scalar integer mode)
libgcc/ PR target/50931 * config/avr/t-avr (LIB1ASMSRC): Add _mulpsi3, _mulsqipsi3. * config/avr/lib1funcs.S (__mulpsi3, __mulsqipsi3): New functions. gcc/ PR target/50931 * config/avr/avr.md (mulpsi3): New expander. (*umulqihipsi3, *umulhiqipsi3): New insns. (*mulsqipsi3.libgcc, *mulpsi3.libgcc): New insns. (mulsqipsi3, *mulpsi3): New insn-and-splits. (ashlpsi3): Turn to expander. Move insn code to... (*ashlpsi3): ...this new insn. testsuite/ PR target/50931 * gcc.target/avr/torture/int24-mul.c: New testcase. From-SVN: r182328
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
552d2db565
commit
d7288dfb9f
@ -1,3 +1,13 @@
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2011-12-14 Georg-Johann Lay <avr@gjlay.de>
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PR target/50931
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* config/avr/avr.md (mulpsi3): New expander.
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(*umulqihipsi3, *umulhiqipsi3): New insns.
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(*mulsqipsi3.libgcc, *mulpsi3.libgcc): New insns.
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(mulsqipsi3, *mulpsi3): New insn-and-splits.
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(ashlpsi3): Turn to expander. Move insn code to...
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(*ashlpsi3): ...this new insn.
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2011-12-14 Richard Guenther <rguenther@suse.de>
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* tree-cfg.c (replace_uses_by): Only mark blocks altered
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@ -2113,7 +2113,7 @@
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[(set_attr "type" "xcall")
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(set_attr "cc" "clobber")])
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;; To support widening multiplicatioon with constant we postpone
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;; To support widening multiplication with constant we postpone
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;; expanding to the implicit library call until post combine and
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;; prior to register allocation. Clobber all hard registers that
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;; might be used by the (widening) multiply until it is split and
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@ -2574,6 +2574,132 @@
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[(set_attr "type" "xcall")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; 24-bit multiply
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;; To support widening multiplication with constant we postpone
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;; expanding to the implicit library call until post combine and
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;; prior to register allocation. Clobber all hard registers that
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;; might be used by the (widening) multiply until it is split and
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;; it's final register footprint is worked out.
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(define_expand "mulpsi3"
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[(parallel [(set (match_operand:PSI 0 "register_operand" "")
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(mult:PSI (match_operand:PSI 1 "register_operand" "")
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(match_operand:PSI 2 "nonmemory_operand" "")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))])]
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"AVR_HAVE_MUL"
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{
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if (s8_operand (operands[2], PSImode))
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{
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rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
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emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
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DONE;
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}
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})
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(define_insn "*umulqihipsi3"
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[(set (match_operand:PSI 0 "register_operand" "=&r")
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(mult:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
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(zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
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"AVR_HAVE_MUL"
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"mul %1,%A2
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movw %A0,r0
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mul %1,%B2
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clr %C0
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add %B0,r0
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adc %C0,r1
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clr __zero_reg__"
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[(set_attr "length" "7")
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(set_attr "cc" "clobber")])
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(define_insn "*umulhiqipsi3"
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[(set (match_operand:PSI 0 "register_operand" "=&r")
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(mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
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(zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))]
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"AVR_HAVE_MUL"
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"mul %1,%A2
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movw %A0,r0
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mul %1,%B2
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add %B0,r0
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mov %C0,r1
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clr __zero_reg__
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adc %C0,__zero_reg__"
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[(set_attr "length" "7")
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(set_attr "cc" "clobber")])
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(define_insn_and_split "mulsqipsi3"
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[(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
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(mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" "r"))
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(match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))]
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"AVR_HAVE_MUL && !reload_completed"
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{ gcc_unreachable(); }
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"&& 1"
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[(set (reg:QI 25)
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(match_dup 1))
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(set (reg:PSI 22)
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(match_dup 2))
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(set (reg:PSI 18)
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(mult:PSI (sign_extend:PSI (reg:QI 25))
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(reg:PSI 22)))
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(set (match_dup 0)
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(reg:PSI 18))])
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(define_insn_and_split "*mulpsi3"
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[(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
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(mult:PSI (match_operand:PSI 1 "pseudo_register_operand" "r")
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(match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))]
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"AVR_HAVE_MUL && !reload_completed"
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{ gcc_unreachable(); }
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"&& 1"
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[(set (reg:PSI 18)
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(match_dup 1))
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(set (reg:PSI 22)
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(match_dup 2))
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(parallel [(set (reg:PSI 22)
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(mult:PSI (reg:PSI 22)
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(reg:PSI 18)))
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(clobber (reg:QI 21))
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(clobber (reg:QI 25))
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(clobber (reg:HI 26))])
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(set (match_dup 0)
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(reg:PSI 22))]
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{
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if (s8_operand (operands[2], PSImode))
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{
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rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
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emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
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DONE;
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}
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})
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(define_insn "*mulsqipsi3.libgcc"
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[(set (reg:PSI 18)
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(mult:PSI (sign_extend:PSI (reg:QI 25))
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(reg:PSI 22)))]
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"AVR_HAVE_MUL"
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"%~call __mulsqipsi3"
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[(set_attr "type" "xcall")
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(set_attr "cc" "clobber")])
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(define_insn "*mulpsi3.libgcc"
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[(set (reg:PSI 22)
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(mult:PSI (reg:PSI 22)
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(reg:PSI 18)))
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(clobber (reg:QI 21))
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(clobber (reg:QI 25))
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(clobber (reg:HI 26))]
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"AVR_HAVE_MUL"
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"%~call __mulpsi3"
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[(set_attr "type" "xcall")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; 24-bit signed/unsigned division and modulo.
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;; Notice that the libgcc implementation return the quotient in R22
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@ -3363,7 +3489,34 @@
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(set_attr "adjust_len" "ashlsi")
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(set_attr "cc" "none,set_n,clobber,clobber")])
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(define_insn "ashlpsi3"
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(define_expand "ashlpsi3"
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[(parallel [(set (match_operand:PSI 0 "register_operand" "")
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(ashift:PSI (match_operand:PSI 1 "register_operand" "")
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(match_operand:QI 2 "nonmemory_operand" "")))
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(clobber (scratch:QI))])]
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""
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{
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if (AVR_HAVE_MUL
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&& CONST_INT_P (operands[2]))
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{
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if (IN_RANGE (INTVAL (operands[2]), 3, 6))
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{
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rtx xoffset = force_reg (QImode, gen_int_mode (1 << INTVAL (operands[2]), QImode));
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emit_insn (gen_mulsqipsi3 (operands[0], xoffset, operands[1]));
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DONE;
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}
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else if (optimize_insn_for_speed_p ()
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&& INTVAL (operands[2]) != 16
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&& IN_RANGE (INTVAL (operands[2]), 9, 22))
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{
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rtx xoffset = force_reg (PSImode, gen_int_mode (1 << INTVAL (operands[2]), PSImode));
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emit_insn (gen_mulpsi3 (operands[0], operands[1], xoffset));
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DONE;
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}
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}
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})
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(define_insn "*ashlpsi3"
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[(set (match_operand:PSI 0 "register_operand" "=r,r,r,r")
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(ashift:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0")
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(match_operand:QI 2 "nonmemory_operand" "r,P,O,n")))
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@ -1,3 +1,8 @@
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2011-12-14 Georg-Johann Lay <avr@gjlay.de>
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PR target/50931
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* gcc.target/avr/torture/int24-mul.c: New.
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2011-12-14 Dodji Seketeli <dodji@redhat.com>
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PR c++/51476
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86
gcc/testsuite/gcc.target/avr/torture/int24-mul.c
Normal file
86
gcc/testsuite/gcc.target/avr/torture/int24-mul.c
Normal file
@ -0,0 +1,86 @@
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/* { dg-do run } */
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/* { dg-options "-w" } */
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#include <stdlib.h>
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const __pgm __int24 vals[] =
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{
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0, 1, 2, 3, -1, -2, -3, 0xff, 0x100, 0x101,
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0xffL * 0xff, 0xfffL * 0xfff, 0x101010L, 0xaaaaaaL
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};
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void test_u (void)
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{
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unsigned int i;
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unsigned long la, lb, lc;
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__uint24 a, b, c;
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int S = sizeof (vals) / sizeof (*vals);
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for (i = 0; i < 500; i++)
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{
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if (i < S*S)
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{
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a = vals[i / S];
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b = vals[i % S];
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}
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else
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{
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if (i & 1)
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a += 0x7654321L;
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else
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b += 0x5fe453L;
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}
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c = a * b;
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la = a;
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lb = b;
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lc = 0xffffff & (la * lb);
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if (c != lc)
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abort();
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}
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}
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#define TEST_N_U(A1,A2,B) \
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do { \
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if ((0xffffff & (A1*B)) != A2*B) \
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abort(); \
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} while (0)
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void test_nu (void)
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{
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unsigned long la;
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unsigned int i;
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int S = sizeof (vals) / sizeof (*vals);
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__uint24 a;
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for (i = 0; i < 500; i++)
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{
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a = i < S
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? vals[i % S]
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: a + 0x7654321;
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la = a;
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TEST_N_U (la, a, 2);
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TEST_N_U (la, a, 3);
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TEST_N_U (la, a, 4);
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TEST_N_U (la, a, 5);
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TEST_N_U (la, a, 15);
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TEST_N_U (la, a, 16);
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TEST_N_U (la, a, 128);
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TEST_N_U (la, a, 0x1000);
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}
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}
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int main (void)
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{
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test_u();
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test_nu();
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exit(0);
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return 0;
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}
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@ -1,3 +1,9 @@
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2011-12-14 Georg-Johann Lay <avr@gjlay.de>
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PR target/49313
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* config/avr/t-avr (LIB1ASMSRC): Add _mulpsi3, _mulsqipsi3.
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* config/avr/lib1funcs.S (__mulpsi3, __mulsqipsi3): New functions.
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2011-12-11 Eric Botcazou <ebotcazou@adacore.com>
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* config/sparc/sol2-unwind.h: Use #ifdef directive consistently.
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@ -465,6 +465,153 @@ ENDF __mulsi3
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#endif /* __AVR_HAVE_MUL__ */
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/*******************************************************
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Multiplication 24 x 24
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*******************************************************/
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#if defined (L_mulpsi3)
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;; A[0..2]: In: Multiplicand; Out: Product
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#define A0 22
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#define A1 A0+1
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#define A2 A0+2
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;; B[0..2]: In: Multiplier
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#define B0 18
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#define B1 B0+1
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#define B2 B0+2
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#if defined (__AVR_HAVE_MUL__)
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;; C[0..2]: Expand Result
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#define C0 22
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#define C1 C0+1
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#define C2 C0+2
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;; R24:R22 *= R20:R18
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;; Clobbers: r21, r25, r26, r27, __tmp_reg__
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#define AA0 26
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#define AA2 21
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DEFUN __mulpsi3
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wmov AA0, A0
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mov AA2, A2
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XCALL __umulhisi3
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mul AA2, B0 $ add C2, r0
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mul AA0, B2 $ add C2, r0
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clr __zero_reg__
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ret
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ENDF __mulpsi3
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#undef AA2
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#undef AA0
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#undef C2
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#undef C1
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#undef C0
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#else /* !HAVE_MUL */
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;; C[0..2]: Expand Result
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#define C0 0
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#define C1 C0+1
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#define C2 21
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;; R24:R22 *= R20:R18
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;; Clobbers: __tmp_reg__, R18, R19, R20, R21
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DEFUN __mulpsi3
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;; C[] = 0
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clr __tmp_reg__
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clr C2
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0: ;; Shift N-th Bit of B[] into Carry. N = 24 - Loop
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LSR B2 $ ror B1 $ ror B0
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;; If the N-th Bit of B[] was set...
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brcc 1f
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;; ...then add A[] * 2^N to the Result C[]
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ADD C0,A0 $ adc C1,A1 $ adc C2,A2
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1: ;; Multiply A[] by 2
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LSL A0 $ rol A1 $ rol A2
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;; Loop until B[] is 0
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subi B0,0 $ sbci B1,0 $ sbci B2,0
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brne 0b
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;; Copy C[] to the return Register A[]
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wmov A0, C0
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mov A2, C2
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clr __zero_reg__
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ret
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ENDF __mulpsi3
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#undef C2
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#undef C1
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#undef C0
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#endif /* HAVE_MUL */
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#undef B2
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#undef B1
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#undef B0
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#undef A2
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#undef A1
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#undef A0
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#endif /* L_mulpsi3 */
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#if defined (L_mulsqipsi3) && defined (__AVR_HAVE_MUL__)
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;; A[0..2]: In: Multiplicand
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#define A0 22
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#define A1 A0+1
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#define A2 A0+2
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;; BB: In: Multiplier
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#define BB 25
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;; C[0..2]: Result
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#define C0 18
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#define C1 C0+1
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#define C2 C0+2
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;; C[] = A[] * sign_extend (BB)
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DEFUN __mulsqipsi3
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mul A0, BB
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movw C0, r0
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mul A2, BB
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mov C2, r0
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mul A1, BB
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add C1, r0
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adc C2, r1
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clr __zero_reg__
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sbrs BB, 7
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ret
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;; One-extend BB
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sub C1, A0
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sbc C2, A1
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ret
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ENDF __mulsqipsi3
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#undef C2
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#undef C1
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#undef C0
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#undef BB
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#undef A2
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#undef A1
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#undef A0
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#endif /* L_mulsqipsi3 && HAVE_MUL */
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|
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/*******************************************************
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Multiplication 64 x 64
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*******************************************************/
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@ -1342,7 +1489,7 @@ DEFUN __divdi3_moddi3
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#endif /* SPEED_DIV */
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0: ;; The Prologue
|
||||
;; Save Z = 12 Registers: Y, 17...8
|
||||
;; Save 12 Registers: Y, 17...8
|
||||
;; No Frame needed (X = 0)
|
||||
clr r26
|
||||
clr r27
|
||||
|
||||
@ -2,6 +2,7 @@ LIB1ASMSRC = avr/lib1funcs.S
|
||||
LIB1ASMFUNCS = \
|
||||
_mulqi3 \
|
||||
_mulhi3 \
|
||||
_mulpsi3 _mulsqipsi3 \
|
||||
_mulhisi3 \
|
||||
_umulhisi3 \
|
||||
_usmulhisi3 \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user