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Add AMD znver5 processor enablement with scheduler model
2024-02-14 Jan Hubicka <jh@suse.cz> Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com> gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5. * common/config/i386/i386-common.cc (processor_names): Add znver5. (processor_alias_table): Likewise. * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen family. (processor_subtypes): Add znver5. * config.gcc (x86_64-*-* |...): Likewise. * config/i386/driver-i386.cc (host_detect_local_cpu): Let march=native detect znver5 cpu's. * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5. * config/i386/i386-options.cc (m_ZNVER5): New definition (processor_cost_table): Add znver5. * config/i386/i386.cc (ix86_reassociation_width): Likewise. * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5 (PTA_ZNVER5): New definition. * config/i386/i386.md (define_attr "cpu"): Add znver5. (Scheduling descriptions) Add znver5.md. * config/i386/x86-tune-costs.h (znver5_cost): New definition. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5. (ix86_adjust_cost): Likewise. * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5. (avx512_store_by_pieces): Add m_ZNVER5. * doc/extend.texi: Add znver5. * doc/invoke.texi: Likewise. * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler. gcc/testsuite/ChangeLog: * g++.target/i386/mv29.C: Handle znver5 arch. * gcc.target/i386/funcspec-56.inc:Likewise.
This commit is contained in:
Jan Hubicka
parent
9361f19e08
commit
d0aa0af9a9
@ -310,6 +310,22 @@ get_amd_cpu (struct __processor_model *cpu_model,
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cpu_model->__cpu_subtype = AMDFAM19H_ZNVER3;
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}
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break;
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case 0x1a:
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cpu_model->__cpu_type = AMDFAM1AH;
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if (model <= 0x77)
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{
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cpu = "znver5";
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CHECK___builtin_cpu_is ("znver5");
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cpu_model->__cpu_subtype = AMDFAM1AH_ZNVER5;
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}
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else if (has_cpu_feature (cpu_model, cpu_features2,
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FEATURE_AVX512VP2INTERSECT))
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{
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cpu = "znver5";
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CHECK___builtin_cpu_is ("znver5");
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cpu_model->__cpu_subtype = AMDFAM1AH_ZNVER5;
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}
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break;
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default:
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break;
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}
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@ -2166,7 +2166,8 @@ const char *const processor_names[] =
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"znver1",
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"znver2",
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"znver3",
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"znver4"
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"znver4",
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"znver5"
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};
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/* Guarantee that the array is aligned with enum processor_type. */
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@ -2435,6 +2436,9 @@ const pta processor_alias_table[] =
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{"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
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PTA_ZNVER4,
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M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
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{"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
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PTA_ZNVER5,
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M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
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{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
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@ -63,6 +63,7 @@ enum processor_types
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INTEL_SIERRAFOREST,
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INTEL_GRANDRIDGE,
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INTEL_CLEARWATERFOREST,
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AMDFAM1AH,
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CPU_TYPE_MAX,
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BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
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};
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@ -104,6 +105,7 @@ enum processor_subtypes
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INTEL_COREI7_ARROWLAKE_S,
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INTEL_COREI7_PANTHERLAKE,
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ZHAOXIN_FAM7H_YONGFENG,
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AMDFAM1AH_ZNVER5,
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CPU_SUBTYPE_MAX
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};
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@ -703,9 +703,9 @@ c7 esther"
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# 64-bit x86 processors supported by --with-arch=. Each processor
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# MUST be separated by exactly one space.
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x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
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bdver3 bdver4 znver1 znver2 znver3 znver4 btver1 btver2 k8 k8-sse3 opteron \
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opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \
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slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
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bdver3 bdver4 znver1 znver2 znver3 znver4 znver5 btver1 btver2 k8 k8-sse3 \
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opteron opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 \
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atom slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
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silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
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skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \
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sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
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@ -3759,6 +3759,10 @@ case ${target} in
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arch=znver4
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cpu=znver4
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;;
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znver5-*)
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arch=znver5
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cpu=znver5
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;;
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bdver4-*)
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arch=bdver4
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cpu=bdver4
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@ -3896,6 +3900,10 @@ case ${target} in
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arch=znver4
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cpu=znver4
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;;
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znver5-*)
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arch=znver5
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cpu=znver5
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;;
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bdver4-*)
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arch=bdver4
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cpu=bdver4
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@ -492,6 +492,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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processor = PROCESSOR_GEODE;
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else if (has_feature (FEATURE_MOVBE) && family == 22)
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processor = PROCESSOR_BTVER2;
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else if (has_feature (FEATURE_AVX512VP2INTERSECT))
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processor = PROCESSOR_ZNVER5;
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else if (has_feature (FEATURE_AVX512F))
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processor = PROCESSOR_ZNVER4;
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else if (has_feature (FEATURE_VAES))
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@ -834,6 +836,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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case PROCESSOR_ZNVER4:
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cpu = "znver4";
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break;
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case PROCESSOR_ZNVER5:
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cpu = "znver5";
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break;
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case PROCESSOR_BTVER1:
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cpu = "btver1";
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break;
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@ -136,6 +136,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__znver4");
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def_or_undef (parse_in, "__znver4__");
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break;
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case PROCESSOR_ZNVER5:
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def_or_undef (parse_in, "__znver5");
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def_or_undef (parse_in, "__znver5__");
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break;
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case PROCESSOR_BTVER1:
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def_or_undef (parse_in, "__btver1");
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def_or_undef (parse_in, "__btver1__");
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@ -374,6 +378,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_ZNVER4:
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def_or_undef (parse_in, "__tune_znver4__");
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break;
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case PROCESSOR_ZNVER5:
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def_or_undef (parse_in, "__tune_znver5__");
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break;
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case PROCESSOR_BTVER1:
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def_or_undef (parse_in, "__tune_btver1__");
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break;
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@ -174,11 +174,12 @@ along with GCC; see the file COPYING3. If not see
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#define m_ZNVER2 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER2)
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#define m_ZNVER3 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER3)
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#define m_ZNVER4 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER4)
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#define m_ZNVER5 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER5)
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#define m_BTVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER1)
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#define m_BTVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER2)
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#define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
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#define m_BTVER (m_BTVER1 | m_BTVER2)
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#define m_ZNVER (m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4)
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#define m_ZNVER (m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5)
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#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \
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| m_ZNVER)
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@ -815,7 +816,8 @@ static const struct processor_costs *processor_cost_table[] =
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&znver1_cost,
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&znver2_cost,
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&znver3_cost,
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&znver4_cost
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&znver4_cost,
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&znver5_cost
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};
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/* Guarantee that the array is aligned with enum processor_type. */
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@ -24469,7 +24469,8 @@ ix86_reassociation_width (unsigned int op, machine_mode mode)
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/* Integer vector instructions execute in FP unit
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and can execute 3 additions and one multiplication per cycle. */
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if ((ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2
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|| ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4)
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|| ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4
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|| ix86_tune == PROCESSOR_ZNVER5)
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&& INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
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return 1;
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@ -2320,6 +2320,7 @@ enum processor_type
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PROCESSOR_ZNVER2,
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PROCESSOR_ZNVER3,
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PROCESSOR_ZNVER4,
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PROCESSOR_ZNVER5,
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PROCESSOR_max
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};
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@ -2442,7 +2443,8 @@ constexpr wide_int_bitmask PTA_ZNVER4 = PTA_ZNVER3 | PTA_AVX512F | PTA_AVX512DQ
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| PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL
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| PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI
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| PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ | PTA_EVEX512;
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constexpr wide_int_bitmask PTA_ZNVER5 = PTA_ZNVER4 | PTA_AVXVNNI
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| PTA_MOVDIRI | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_PREFETCHI;
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constexpr wide_int_bitmask PTA_LUJIAZUI = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
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| PTA_SSE3 | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES
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| PTA_PCLMUL | PTA_BMI | PTA_BMI2 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT
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@ -518,7 +518,8 @@
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;; Processor type.
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(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
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atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
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bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4"
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bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
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znver5"
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(const (symbol_ref "ix86_schedule")))
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;; A basic instruction type. Refinements due to arguments to be
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@ -1392,7 +1393,7 @@
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(include "bdver3.md")
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(include "btver2.md")
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(include "znver.md")
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(include "znver4.md")
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(include "zn4zn5.md")
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(include "geode.md")
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(include "atom.md")
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(include "slm.md")
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@ -1986,6 +1986,142 @@ struct processor_costs znver4_cost = {
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2, /* Small unroll factor. */
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};
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/* This table currently replicates znver4_cost table. */
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struct processor_costs znver5_cost = {
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{
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/* Start of register allocator costs. integer->integer move cost is 2. */
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/* reg-reg moves are done by renaming and thus they are even cheaper than
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1 cycle. Because reg-reg move cost is 2 and following tables correspond
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to doubles of latencies, we do not model this correctly. It does not
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seem to make practical difference to bump prices up even more. */
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6, /* cost for loading QImode using
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movzbl. */
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{6, 6, 6}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer
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registers. */
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2, /* cost of reg,reg fld/fst. */
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{14, 14, 17}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode. */
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{12, 12, 16}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode. */
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2, /* cost of moving MMX register. */
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{6, 6}, /* cost of loading MMX registers
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in SImode and DImode. */
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{8, 8}, /* cost of storing MMX registers
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in SImode and DImode. */
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2, 2, 3, /* cost of moving XMM,YMM,ZMM
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register. */
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{6, 6, 10, 10, 12}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit. */
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{8, 8, 8, 12, 12}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit. */
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6, 8, /* SSE->integer and integer->SSE
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moves. */
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8, 8, /* mask->integer and integer->mask moves */
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{6, 6, 6}, /* cost of loading mask register
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in QImode, HImode, SImode. */
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{8, 8, 8}, /* cost if storing mask register
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in QImode, HImode, SImode. */
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2, /* cost of moving mask register. */
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/* End of register allocator costs. */
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},
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COSTS_N_INSNS (1), /* cost of an add instruction. */
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/* TODO: Lea with 3 components has cost 2. */
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COSTS_N_INSNS (1), /* cost of a lea instruction. */
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COSTS_N_INSNS (1), /* variable shift costs. */
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COSTS_N_INSNS (1), /* constant shift costs. */
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{COSTS_N_INSNS (3), /* cost of starting multiply for QI. */
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COSTS_N_INSNS (3), /* HI. */
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COSTS_N_INSNS (3), /* SI. */
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COSTS_N_INSNS (3), /* DI. */
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COSTS_N_INSNS (3)}, /* other. */
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0, /* cost of multiply per each bit
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set. */
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{COSTS_N_INSNS (10), /* cost of a divide/mod for QI. */
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COSTS_N_INSNS (11), /* HI. */
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COSTS_N_INSNS (13), /* SI. */
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COSTS_N_INSNS (16), /* DI. */
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COSTS_N_INSNS (16)}, /* other. */
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COSTS_N_INSNS (1), /* cost of movsx. */
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COSTS_N_INSNS (1), /* cost of movzx. */
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8, /* "large" insn. */
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9, /* MOVE_RATIO. */
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6, /* CLEAR_RATIO */
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{6, 6, 6}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer
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registers. */
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{6, 6, 10, 10, 12}, /* cost of loading SSE registers
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in 32bit, 64bit, 128bit, 256bit and 512bit */
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{8, 8, 8, 12, 12}, /* cost of storing SSE register
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in 32bit, 64bit, 128bit, 256bit and 512bit */
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{6, 6, 6, 6, 6}, /* cost of unaligned loads. */
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{8, 8, 8, 8, 8}, /* cost of unaligned stores. */
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2, 2, 2, /* cost of moving XMM,YMM,ZMM
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register. */
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6, /* cost of moving SSE register to integer. */
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/* VGATHERDPD is 17 uops and throughput is 4, VGATHERDPS is 24 uops,
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throughput 5. Approx 7 uops do not depend on vector size and every load
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is 5 uops. */
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14, 10, /* Gather load static, per_elt. */
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14, 20, /* Gather store static, per_elt. */
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32, /* size of l1 cache. */
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1024, /* size of l2 cache. */
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64, /* size of prefetch block. */
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/* New AMD processors never drop prefetches; if they cannot be performed
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immediately, they are queued. We set number of simultaneous prefetches
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to a large constant to reflect this (it probably is not a good idea not
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to limit number of prefetches at all, as their execution also takes some
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time). */
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100, /* number of parallel prefetches. */
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3, /* Branch cost. */
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COSTS_N_INSNS (7), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (7), /* cost of FMUL instruction. */
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/* Latency of fdiv is 8-15. */
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COSTS_N_INSNS (15), /* cost of FDIV instruction. */
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COSTS_N_INSNS (1), /* cost of FABS instruction. */
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COSTS_N_INSNS (1), /* cost of FCHS instruction. */
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/* Latency of fsqrt is 4-10. */
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COSTS_N_INSNS (25), /* cost of FSQRT instruction. */
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COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
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COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
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COSTS_N_INSNS (3), /* cost of MULSS instruction. */
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COSTS_N_INSNS (3), /* cost of MULSD instruction. */
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COSTS_N_INSNS (4), /* cost of FMA SS instruction. */
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COSTS_N_INSNS (4), /* cost of FMA SD instruction. */
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COSTS_N_INSNS (10), /* cost of DIVSS instruction. */
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/* 9-13. */
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COSTS_N_INSNS (13), /* cost of DIVSD instruction. */
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COSTS_N_INSNS (14), /* cost of SQRTSS instruction. */
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COSTS_N_INSNS (20), /* cost of SQRTSD instruction. */
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/* Zen can execute 4 integer operations per cycle. FP operations
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take 3 cycles and it can execute 2 integer additions and 2
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multiplications thus reassociation may make sense up to with of 6.
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SPEC2k6 bencharks suggests
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that 4 works better than 6 probably due to register pressure.
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Integer vector operations are taken by FP unit and execute 3 vector
|
||||
plus/minus operations per cycle but only one multiply. This is adjusted
|
||||
in ix86_reassociation_width. */
|
||||
4, 4, 3, 6, /* reassoc int, fp, vec_int, vec_fp. */
|
||||
znver2_memcpy,
|
||||
znver2_memset,
|
||||
COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
|
||||
COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
|
||||
"16", /* Loop alignment. */
|
||||
"16", /* Jump alignment. */
|
||||
"0:0:8", /* Label alignment. */
|
||||
"16", /* Func alignment. */
|
||||
4, /* Small unroll limit. */
|
||||
2, /* Small unroll factor. */
|
||||
};
|
||||
|
||||
/* skylake_cost should produce code tuned for Skylake familly of CPUs. */
|
||||
static stringop_algs skylake_memcpy[2] = {
|
||||
{libcall,
|
||||
|
||||
@ -69,6 +69,7 @@ ix86_issue_rate (void)
|
||||
case PROCESSOR_ZNVER2:
|
||||
case PROCESSOR_ZNVER3:
|
||||
case PROCESSOR_ZNVER4:
|
||||
case PROCESSOR_ZNVER5:
|
||||
case PROCESSOR_CORE2:
|
||||
case PROCESSOR_NEHALEM:
|
||||
case PROCESSOR_SANDYBRIDGE:
|
||||
@ -417,6 +418,7 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
|
||||
case PROCESSOR_ZNVER2:
|
||||
case PROCESSOR_ZNVER3:
|
||||
case PROCESSOR_ZNVER4:
|
||||
case PROCESSOR_ZNVER5:
|
||||
/* Stack engine allows to execute push&pop instructions in parall. */
|
||||
if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
|
||||
&& (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
|
||||
|
||||
@ -575,12 +575,12 @@ DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
|
||||
/* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
|
||||
AVX instructions. */
|
||||
DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
|
||||
m_SAPPHIRERAPIDS | m_ZNVER4)
|
||||
m_SAPPHIRERAPIDS | m_ZNVER4 | m_ZNVER5)
|
||||
|
||||
/* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
|
||||
AVX instructions. */
|
||||
DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
|
||||
m_SAPPHIRERAPIDS | m_ZNVER4)
|
||||
m_SAPPHIRERAPIDS | m_ZNVER4 | m_ZNVER5)
|
||||
|
||||
/*****************************************************************************/
|
||||
/*****************************************************************************/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -26194,6 +26194,9 @@ AMD Family 19h Zen version 3.
|
||||
|
||||
@item znver4
|
||||
AMD Family 19h Zen version 4.
|
||||
|
||||
@item znver5
|
||||
AMD Family 1ah Zen version 5.
|
||||
@end table
|
||||
|
||||
Here is an example:
|
||||
|
||||
@ -34487,6 +34487,16 @@ WBNOINVD, PKU, VPCLMULQDQ, VAES, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,
|
||||
AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, AVX512VNNI,
|
||||
AVX512BITALG, AVX512VPOPCNTDQ, GFNI and 64-bit instruction set extensions.)
|
||||
|
||||
@item znver5
|
||||
AMD Family 1ah core based CPUs with x86-64 instruction set support. (This
|
||||
supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,
|
||||
MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
|
||||
SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,
|
||||
WBNOINVD, PKU, VPCLMULQDQ, VAES, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,
|
||||
AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, AVX512VNNI,
|
||||
AVX512BITALG, AVX512VPOPCNTDQ, GFNI, AVXVNNI, MOVDIRI, MOVDIR64B,
|
||||
AVX512VP2INTERSECT, PREFETCHI and 64-bit instruction set extensions.)
|
||||
|
||||
@item btver1
|
||||
CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
|
||||
supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
|
||||
|
||||
@ -53,6 +53,10 @@ int __attribute__ ((target("arch=znver4"))) foo () {
|
||||
return 10;
|
||||
}
|
||||
|
||||
int __attribute__ ((target("arch=znver5"))) foo () {
|
||||
return 11;
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
int val = foo ();
|
||||
@ -77,6 +81,8 @@ int main ()
|
||||
assert (val == 9);
|
||||
else if (__builtin_cpu_is ("znver4"))
|
||||
assert (val == 10);
|
||||
else if (__builtin_cpu_is ("znver5"))
|
||||
assert (val == 11);
|
||||
else
|
||||
assert (val == 0);
|
||||
|
||||
|
||||
@ -224,6 +224,7 @@ extern void test_arch_znver1 (void) __attribute__((__target__("arch=
|
||||
extern void test_arch_znver2 (void) __attribute__((__target__("arch=znver2")));
|
||||
extern void test_arch_znver3 (void) __attribute__((__target__("arch=znver3")));
|
||||
extern void test_arch_znver4 (void) __attribute__((__target__("arch=znver4")));
|
||||
extern void test_arch_znver5 (void) __attribute__((__target__("arch=znver5")));
|
||||
|
||||
extern void test_tune_nocona (void) __attribute__((__target__("tune=nocona")));
|
||||
extern void test_tune_core2 (void) __attribute__((__target__("tune=core2")));
|
||||
@ -249,6 +250,7 @@ extern void test_tune_znver1 (void) __attribute__((__target__("tune=
|
||||
extern void test_tune_znver2 (void) __attribute__((__target__("tune=znver2")));
|
||||
extern void test_tune_znver3 (void) __attribute__((__target__("tune=znver3")));
|
||||
extern void test_tune_znver4 (void) __attribute__((__target__("tune=znver4")));
|
||||
extern void test_tune_znver5 (void) __attribute__((__target__("tune=znver5")));
|
||||
|
||||
extern void test_fpmath_sse (void) __attribute__((__target__("sse2,fpmath=sse")));
|
||||
extern void test_fpmath_387 (void) __attribute__((__target__("sse2,fpmath=387")));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user