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AArch64: fix aarch64_usubw pattern
It looks like during my pre-commit testrun I forgot to apply this patch to the patch stack. It had a typo in the element size. It also looks like since the hi/lo operations take different element counts for the assembler syntax that I can't have a unified pattern. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip, aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): Split into... (aarch64_uaddw<mode>_lo_zip, aarch64_uaddw<mode>_hi_zip, "aarch64_usubw<mode>_lo_zip, "aarch64_usubw<mode>_hi_zip): ... This. * config/aarch64/iterators.md (PERM_EXTEND, perm_index): Remove. (perm_hilo): Remove UNSPEC_ZIP1, UNSPEC_ZIP2. gcc/testsuite/ChangeLog: * gcc.target/aarch64/uxtl-combine-4.c: Fix typo. * gcc.target/aarch64/uxtl-combine-5.c: Likewise. * gcc.target/aarch64/uxtl-combine-6.c: Likewise.
This commit is contained in:
Tamar Christina
parent
8c24011b2b
commit
c2ef470885
@ -4810,7 +4810,7 @@
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[(set_attr "type" "neon_sub_widen")]
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)
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(define_insn "aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip"
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(define_insn "aarch64_usubw<mode>_lo_zip"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(minus:<VWIDE>
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(match_operand:<VWIDE> 1 "register_operand" "w")
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@ -4818,23 +4818,51 @@
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(unspec:<MODE> [
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "aarch64_simd_imm_zero")
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] PERM_EXTEND) 0)))]
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] UNSPEC_ZIP1) 0)))]
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"TARGET_SIMD"
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"usubw<PERM_EXTEND:perm_index>\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
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"usubw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
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[(set_attr "type" "neon_sub_widen")]
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)
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(define_insn "aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip"
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(define_insn "aarch64_uaddw<mode>_lo_zip"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(plus:<VWIDE>
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(subreg:<VWIDE>
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(unspec:<MODE> [
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "aarch64_simd_imm_zero")
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] PERM_EXTEND) 0)
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] UNSPEC_ZIP1) 0)
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(match_operand:<VWIDE> 1 "register_operand" "w")))]
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"TARGET_SIMD"
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"uaddw<PERM_EXTEND:perm_index>\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
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"uaddw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
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[(set_attr "type" "neon_add_widen")]
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)
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(define_insn "aarch64_usubw<mode>_hi_zip"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(minus:<VWIDE>
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(match_operand:<VWIDE> 1 "register_operand" "w")
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(subreg:<VWIDE>
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(unspec:<MODE> [
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "aarch64_simd_imm_zero")
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] UNSPEC_ZIP2) 0)))]
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"TARGET_SIMD"
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"usubw2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
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[(set_attr "type" "neon_sub_widen")]
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)
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(define_insn "aarch64_uaddw<mode>_hi_zip"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(plus:<VWIDE>
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(subreg:<VWIDE>
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(unspec:<MODE> [
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "aarch64_simd_imm_zero")
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] UNSPEC_ZIP2) 0)
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(match_operand:<VWIDE> 1 "register_operand" "w")))]
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"TARGET_SIMD"
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"uaddw2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
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[(set_attr "type" "neon_add_widen")]
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)
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@ -2645,9 +2645,6 @@
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(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
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UNSPEC_UZP1 UNSPEC_UZP2])
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;; Permutes for zero extends
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(define_int_iterator PERM_EXTEND [UNSPEC_ZIP1 UNSPEC_ZIP2])
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(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
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(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
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@ -3470,10 +3467,7 @@
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(UNSPEC_REV16 "16")])
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(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
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(UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")
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(UNSPEC_ZIP2 "hi") (UNSPEC_ZIP1 "lo")])
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(define_int_attr perm_index [(UNSPEC_ZIP2 "2") (UNSPEC_ZIP1 "")])
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(UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
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;; Return true if the associated optab refers to the high-numbered lanes,
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;; false if it refers to the low-numbered lanes. The convention is for
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@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n)
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/* { dg-final { scan-assembler-not {\tzip1\t} } } */
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/* { dg-final { scan-assembler-not {\tzip2\t} } } */
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/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */
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/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */
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/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */
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@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n)
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/* { dg-final { scan-assembler-not {\tzip1\t} } } */
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/* { dg-final { scan-assembler-not {\tzip2\t} } } */
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/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */
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/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */
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/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */
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@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n)
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/* { dg-final { scan-assembler-not {\tzip1\t} } } */
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/* { dg-final { scan-assembler-not {\tzip2\t} } } */
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/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */
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/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */
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/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */
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