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i386: Introduce V2QImode minmax, abs and uavgv2hi3_ceil [PR103861]
Add V2QImode minmax, abs and uavxv2qi3_ceil operations with SSE registers. 2022-01-05 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/103861 * config/i386/mmx.md (VI_16_32): New mode iterator. (VI1_16_32): Ditto. (mmxvecsize): Handle V2QI mode. (<smaxmin:code><mode>3): Rename from <smaxmin:code>v4qi3. Use VI1_16_32 mode iterator. (<umaxmin:code><mode>3): Rename from <umaxmin:code>v4qi3. Use VI1_16_32 mode iterator. (abs<mode>2): Use VI_16_32 mode iterator. (uavgv2qi3_ceil): New insn pattern. gcc/testsuite/ChangeLog: PR target/103861 * gcc.target/i386/pr103861-3.c: New test. * g++.dg/vect/slp-pr98855.cc (dg-final): Check that no vectorization using SLP was performed.
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Uros Bizjak
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c166632bd2
@ -63,6 +63,12 @@
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;; 4-byte integer vector modes
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(define_mode_iterator VI_32 [V4QI V2HI])
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;; 4-byte and 2-byte integer vector modes
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(define_mode_iterator VI_16_32 [V4QI V2QI V2HI])
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;; 4-byte and 2-byte QImode vector modes
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(define_mode_iterator VI1_16_32 [V4QI V2QI])
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;; V2S* modes
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(define_mode_iterator V2FI [V2SF V2SI])
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@ -71,7 +77,8 @@
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;; Mapping from integer vector mode to mnemonic suffix
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(define_mode_attr mmxvecsize
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[(V8QI "b") (V4QI "b") (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")])
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[(V8QI "b") (V4QI "b") (V2QI "b")
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(V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")])
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(define_mode_attr mmxdoublemode
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[(V8QI "V8HI") (V4HI "V4SI")])
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@ -2140,11 +2147,11 @@
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(match_operand:V4HI 2 "register_operand")))]
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"TARGET_MMX_WITH_SSE")
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(define_insn "<code>v4qi3"
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[(set (match_operand:V4QI 0 "register_operand" "=Yr,*x,Yv")
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(smaxmin:V4QI
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(match_operand:V4QI 1 "register_operand" "%0,0,Yv")
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(match_operand:V4QI 2 "register_operand" "Yr,*x,Yv")))]
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(define_insn "<code><mode>3"
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[(set (match_operand:VI1_16_32 0 "register_operand" "=Yr,*x,Yv")
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(smaxmin:VI1_16_32
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(match_operand:VI1_16_32 1 "register_operand" "%0,0,Yv")
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(match_operand:VI1_16_32 2 "register_operand" "Yr,*x,Yv")))]
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"TARGET_SSE4_1"
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"@
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p<maxmin_int>b\t{%2, %0|%0, %2}
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@ -2218,11 +2225,11 @@
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(match_operand:V8QI 2 "register_operand")))]
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"TARGET_MMX_WITH_SSE")
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(define_insn "<code>v4qi3"
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[(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
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(umaxmin:V4QI
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(match_operand:V4QI 1 "register_operand" "%0,Yw")
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(match_operand:V4QI 2 "register_operand" "x,Yw")))]
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(define_insn "<code><mode>3"
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[(set (match_operand:VI1_16_32 0 "register_operand" "=x,Yw")
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(umaxmin:VI1_16_32
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(match_operand:VI1_16_32 1 "register_operand" "%0,Yw")
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(match_operand:VI1_16_32 2 "register_operand" "x,Yw")))]
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"TARGET_SSE2"
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"@
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p<maxmin_int>b\t{%2, %0|%0, %2}
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@ -2269,9 +2276,9 @@
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"TARGET_SSSE3 && TARGET_MMX_WITH_SSE")
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(define_insn "abs<mode>2"
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[(set (match_operand:VI_32 0 "register_operand" "=Yv")
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(abs:VI_32
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(match_operand:VI_32 1 "register_operand" "Yv")))]
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[(set (match_operand:VI_16_32 0 "register_operand" "=Yv")
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(abs:VI_16_32
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(match_operand:VI_16_32 1 "register_operand" "Yv")))]
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"TARGET_SSSE3"
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"%vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
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[(set_attr "type" "sselog1")
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@ -4351,6 +4358,26 @@
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(set_attr "type" "sseiadd")
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(set_attr "mode" "TI")])
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(define_insn "uavgv2qi3_ceil"
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[(set (match_operand:V2QI 0 "register_operand" "=x,Yw")
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(truncate:V2QI
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(lshiftrt:V2HI
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(plus:V2HI
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(plus:V2HI
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(zero_extend:V2HI
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(match_operand:V2QI 1 "register_operand" "%0,Yw"))
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(zero_extend:V2HI
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(match_operand:V2QI 2 "register_operand" "x,Yw")))
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(const_vector:V2HI [(const_int 1) (const_int 1)]))
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(const_int 1))))]
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"TARGET_SSE2"
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"@
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pavgb\t{%2, %0|%0, %2}
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vpavgb\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseiadd")
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(set_attr "mode" "TI")])
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(define_insn "uavgv2hi3_ceil"
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[(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
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(truncate:V2HI
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@ -81,6 +81,5 @@ void encrypt_n(const uint8_t in[], uint8_t out[], size_t blocks, uint32_t *EK)
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}
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}
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// This used to work on { target x86_64-*-* i?86-*-* } but a fix in SLP
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// discovery makes us trip over the threshold again.
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// { dg-final { scan-tree-dump-times "not vectorized: vectorization is not profitable" 2 "slp1" { xfail *-*-* } } }
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// { dg-final { scan-tree-dump "not vectorized: vectorization is not profitable" "slp1" } }
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// { dg-final { scan-tree-dump-not "vectorizing stmts using SLP" "slp1" } }
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66
gcc/testsuite/gcc.target/i386/pr103861-3.c
Normal file
66
gcc/testsuite/gcc.target/i386/pr103861-3.c
Normal file
@ -0,0 +1,66 @@
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/* PR target/103861 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -msse4" } */
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char r[2], a[2], b[2];
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unsigned char ur[2], ua[2], ub[2];
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void maxs (void)
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{
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int i;
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for (i = 0; i < 2; i++)
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r[i] = a[i] > b[i] ? a[i] : b[i];
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}
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/* { dg-final { scan-assembler "pmaxsb" } } */
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void maxu (void)
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{
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int i;
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for (i = 0; i < 2; i++)
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ur[i] = ua[i] > ub[i] ? ua[i] : ub[i];
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}
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/* { dg-final { scan-assembler "pmaxub" } } */
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void mins (void)
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{
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int i;
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for (i = 0; i < 2; i++)
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r[i] = a[i] < b[i] ? a[i] : b[i];
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}
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/* { dg-final { scan-assembler "pminsb" } } */
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void minu (void)
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{
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int i;
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for (i = 0; i < 2; i++)
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ur[i] = ua[i] < ub[i] ? ua[i] : ub[i];
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}
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/* { dg-final { scan-assembler "pminub" } } */
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void _abs (void)
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{
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int i;
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for (i = 0; i < 2; i++)
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r[i] = a[i] < 0 ? -a[i] : a[i];
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}
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/* { dg-final { scan-assembler "pabsb" } } */
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void avgu (void)
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{
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int i;
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for (i = 0; i < 2; i++)
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ur[i] = (ua[i] + ub[i] + 1) >> 1;
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}
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/* { dg-final { scan-assembler "pavgb" { xfail *-*-* } } } */
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