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arc: Update 64bit move split patterns.
ARCv2HS can use a limited number of instructions to implement 64bit moves. The VADD2 is used as a 64bit move, the LDD/STD are 64 bit loads and stores. All those instructions are not baseline, hence we need to provide alternatives when they are not available or cannot be generate due to instruction restriction. This patch is cleaning up those move patterns, and updates splits instruction lengths. gcc/ 2021-06-09 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-protos.h (arc_split_move_p): New prototype. * config/arc/arc.c (arc_split_move_p): New function. (arc_split_move): Clean up. * config/arc/arc.md (movdi_insn): Clean up, use arc_split_move_p. (movdf_insn): Likewise. * config/arc/simdext.md (mov<VWH>_insn): Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
This commit is contained in:
Claudiu Zissulescu
parent
d4d38135b3
commit
c0ba7a8af5
@ -50,6 +50,7 @@ extern void arc_split_ior (rtx *);
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extern bool arc_check_mov_const (HOST_WIDE_INT );
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extern bool arc_split_mov_const (rtx *);
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extern bool arc_can_use_return_insn (void);
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extern bool arc_split_move_p (rtx *);
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#endif /* RTX_CODE */
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extern bool arc_ccfsm_branch_deleted_p (void);
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@ -10108,6 +10108,31 @@ arc_process_double_reg_moves (rtx *operands)
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return true;
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}
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/* Check if we need to split a 64bit move. We do not need to split it if we can
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use vadd2 or ldd/std instructions. */
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bool
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arc_split_move_p (rtx *operands)
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{
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machine_mode mode = GET_MODE (operands[0]);
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if (TARGET_LL64
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&& ((memory_operand (operands[0], mode)
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&& (even_register_operand (operands[1], mode)
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|| satisfies_constraint_Cm3 (operands[1])))
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|| (memory_operand (operands[1], mode)
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&& even_register_operand (operands[0], mode))))
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return false;
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if (TARGET_PLUS_QMACW
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&& even_register_operand (operands[0], mode)
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&& even_register_operand (operands[1], mode))
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return false;
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return true;
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}
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/* operands 0..1 are the operands of a 64 bit move instruction.
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split it into two moves with operands 2/3 and 4/5. */
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@ -10125,25 +10150,6 @@ arc_split_move (rtx *operands)
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return;
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}
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if (TARGET_LL64
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&& ((memory_operand (operands[0], mode)
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&& (even_register_operand (operands[1], mode)
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|| satisfies_constraint_Cm3 (operands[1])))
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|| (memory_operand (operands[1], mode)
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&& even_register_operand (operands[0], mode))))
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{
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emit_move_insn (operands[0], operands[1]);
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return;
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}
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if (TARGET_PLUS_QMACW
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&& even_register_operand (operands[0], mode)
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&& even_register_operand (operands[1], mode))
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{
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emit_move_insn (operands[0], operands[1]);
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return;
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}
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if (TARGET_PLUS_QMACW
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&& GET_CODE (operands[1]) == CONST_VECTOR)
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{
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@ -1330,47 +1330,20 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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"register_operand (operands[0], DImode)
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|| register_operand (operands[1], DImode)
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|| (satisfies_constraint_Cm3 (operands[1])
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&& memory_operand (operands[0], DImode))"
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"*
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{
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switch (which_alternative)
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{
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default:
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return \"#\";
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case 0:
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if (TARGET_PLUS_QMACW
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&& even_register_operand (operands[0], DImode)
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&& even_register_operand (operands[1], DImode))
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return \"vadd2%?\\t%0,%1,0\";
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return \"#\";
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case 2:
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if (TARGET_LL64
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&& memory_operand (operands[1], DImode)
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&& even_register_operand (operands[0], DImode))
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return \"ldd%U1%V1 %0,%1%&\";
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return \"#\";
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case 3:
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if (TARGET_LL64
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&& memory_operand (operands[0], DImode)
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&& (even_register_operand (operands[1], DImode)
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|| satisfies_constraint_Cm3 (operands[1])))
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return \"std%U0%V0 %1,%0\";
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return \"#\";
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}
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}"
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"&& reload_completed"
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&& memory_operand (operands[0], DImode))"
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"@
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vadd2\\t%0,%1,0
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#
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ldd%U1%V1\\t%0,%1
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std%U0%V0\\t%1,%0"
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"&& reload_completed && arc_split_move_p (operands)"
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[(const_int 0)]
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{
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arc_split_move (operands);
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DONE;
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}
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[(set_attr "type" "move,move,load,store")
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;; ??? The ld/st values could be 4 if it's [reg,bignum].
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(set_attr "length" "8,16,*,*")])
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(set_attr "length" "8,16,16,16")])
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;; Floating point move insns.
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@ -1409,50 +1382,22 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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(define_insn_and_split "*movdf_insn"
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[(set (match_operand:DF 0 "move_dest_operand" "=D,r,r,r,r,m")
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(match_operand:DF 1 "move_double_src_operand" "r,D,r,E,m,r"))]
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"register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode)"
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"*
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{
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switch (which_alternative)
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{
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default:
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return \"#\";
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case 2:
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if (TARGET_PLUS_QMACW
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&& even_register_operand (operands[0], DFmode)
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&& even_register_operand (operands[1], DFmode))
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return \"vadd2%?\\t%0,%1,0\";
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return \"#\";
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case 4:
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if (TARGET_LL64
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&& ((even_register_operand (operands[0], DFmode)
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&& memory_operand (operands[1], DFmode))
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|| (memory_operand (operands[0], DFmode)
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&& even_register_operand (operands[1], DFmode))))
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return \"ldd%U1%V1 %0,%1%&\";
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return \"#\";
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case 5:
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if (TARGET_LL64
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&& ((even_register_operand (operands[0], DFmode)
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&& memory_operand (operands[1], DFmode))
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|| (memory_operand (operands[0], DFmode)
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&& even_register_operand (operands[1], DFmode))))
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return \"std%U0%V0 %1,%0\";
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return \"#\";
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}
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}"
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"reload_completed"
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"(register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode))"
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"@
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#
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#
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vadd2\\t%0,%1,0
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#
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ldd%U1%V1\\t%0,%1
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std%U0%V0\\t%1,%0"
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"&& reload_completed && arc_split_move_p (operands)"
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[(const_int 0)]
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{
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arc_split_move (operands);
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DONE;
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}
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[(set_attr "type" "move,move,move,move,load,store")
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(set_attr "predicable" "no,no,no,yes,no,no")
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;; ??? The ld/st values could be 16 if it's [reg,bignum].
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(set_attr "length" "4,16,8,16,16,16")])
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(define_insn_and_split "*movdf_insn_nolrsr"
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@ -1472,41 +1472,19 @@
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(match_operand:VWH 1 "general_operand" "i,r,m,r"))]
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"(register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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"*
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{
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switch (which_alternative)
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{
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default:
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return \"#\";
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case 1:
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if (TARGET_PLUS_QMACW
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&& even_register_operand (operands[0], <MODE>mode)
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&& even_register_operand (operands[1], <MODE>mode))
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return \"vadd2%?\\t%0,%1,0\";
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return \"#\";
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case 2:
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if (TARGET_LL64)
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return \"ldd%U1%V1\\t%0,%1\";
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return \"#\";
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case 3:
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if (TARGET_LL64)
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return \"std%U0%V0\\t%1,%0\";
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return \"#\";
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}
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}"
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"reload_completed"
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"@
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#
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vadd2\\t%0,%1,0
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ldd%U1%V1\\t%0,%1
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std%U0%V0\\t%1,%0"
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"&& reload_completed && arc_split_move_p (operands)"
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[(const_int 0)]
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{
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arc_split_move (operands);
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DONE;
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}
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[(set_attr "type" "move,multi,load,store")
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(set_attr "predicable" "no,no,no,no")
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(set_attr "iscompact" "false,false,false,false")
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])
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[(set_attr "type" "move,move,load,store")
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(set_attr "length" "16,8,16,16")])
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(define_expand "movmisalign<mode>"
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[(set (match_operand:VWH 0 "general_operand" "")
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