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[Patch ARM Refactor Builtins 8/8] Neaten up the ARM Neon builtin infrastructure

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	* config/arm/arm-builtins.c (CONVERT_QUALIFIERS): Delete.
	(COPYSIGNF_QUALIFIERS): Likewise.
	(CREATE_QUALIFIERS): Likewise.
	(DUP_QUALIFIERS): Likewise.
	(FLOAT_WIDEN_QUALIFIERS): Likewise.
	(FLOAT_NARROW_QUALIFIERS): Likewise.
	(REINTERP_QUALIFIERS): Likewise.
	(RINT_QUALIFIERS): Likewise.
	(SPLIT_QUALIFIERS): Likewise.
	(FIXCONV_QUALIFIERS): Likewise.
	(SCALARMUL_QUALIFIERS): Likewise.
	(SCALARMULL_QUALIFIERS): Likewise.
	(SCALARMULH_QUALIFIERS): Likewise.
	(SELECT_QUALIFIERS): Likewise.
	(VTBX_QUALIFIERS): Likewise.
	(SHIFTIMM_QUALIFIERS): Likewise.
	(SCALARMAC_QUALIFIERS): Likewise.
	(LANEMUL_QUALIFIERS): Likewise.
	(LANEMULH_QUALIFIERS): Likewise.
	(LANEMULL_QUALIFIERS): Likewise.
	(SHIFTACC_QUALIFIERS): Likewise.
	(SHIFTINSERT_QUALIFIERS): Likewise.
	(VTBL_QUALIFIERS): Likewise.
	(LOADSTRUCT_QUALIFIERS): Likewise.
	(LOADSTRUCTLANE_QUALIFIERS): Likewise.
	(STORESTRUCT_QUALIFIERS): Likewise.
	(STORESTRUCTLANE_QUALIFIERS): Likewise.
	(neon_builtin_type_mode): Delete.
	(v8qi_UP): Map to V8QImode.
	(v8qi_UP): Map to V8QImode.
	(v4hi_UP): Map to V4HImode.
	(v4hf_UP): Map to V4HFmode.
	(v2si_UP): Map to V2SImode.
	(v2sf_UP): Map to V2SFmode.
	(di_UP): Map to DImode.
	(v16qi_UP): Map to V16QImode.
	(v8hi_UP): Map to V8HImode.
	(v4si_UP): Map to V4SImode.
	(v4sf_UP): Map to V4SFmode.
	(v2di_UP): Map to V2DImode.
	(ti_UP): Map to TImode.
	(ei_UP): Map to EImode.
	(oi_UP): Map to OImode.
	(neon_itype): Delete.
	(neon_builtin_datum): Remove itype, make mode a machine_mode.
	(VAR1): Update accordingly.
	(arm_init_neon_builtins): Use machine_mode directly.
	(neon_dereference_pointer): Likewise.
	(arm_expand_neon_args): Use qualifiers to decide operand types.
	(arm_expand_neon_builtin): Likewise.
	* config/arm/arm_neon_builtins.def: Remap operation type for
	many builtins.

From-SVN: r217700
This commit is contained in:
James Greenhalgh 2014-11-18 10:01:55 +00:00 committed by James Greenhalgh
parent 6276b63014
commit bd79363ce0
3 changed files with 278 additions and 395 deletions
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55
gcc/ChangeLog
View File

@ -1,3 +1,58 @@
2014-11-18 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm-builtins.c (CONVERT_QUALIFIERS): Delete.
(COPYSIGNF_QUALIFIERS): Likewise.
(CREATE_QUALIFIERS): Likewise.
(DUP_QUALIFIERS): Likewise.
(FLOAT_WIDEN_QUALIFIERS): Likewise.
(FLOAT_NARROW_QUALIFIERS): Likewise.
(REINTERP_QUALIFIERS): Likewise.
(RINT_QUALIFIERS): Likewise.
(SPLIT_QUALIFIERS): Likewise.
(FIXCONV_QUALIFIERS): Likewise.
(SCALARMUL_QUALIFIERS): Likewise.
(SCALARMULL_QUALIFIERS): Likewise.
(SCALARMULH_QUALIFIERS): Likewise.
(SELECT_QUALIFIERS): Likewise.
(VTBX_QUALIFIERS): Likewise.
(SHIFTIMM_QUALIFIERS): Likewise.
(SCALARMAC_QUALIFIERS): Likewise.
(LANEMUL_QUALIFIERS): Likewise.
(LANEMULH_QUALIFIERS): Likewise.
(LANEMULL_QUALIFIERS): Likewise.
(SHIFTACC_QUALIFIERS): Likewise.
(SHIFTINSERT_QUALIFIERS): Likewise.
(VTBL_QUALIFIERS): Likewise.
(LOADSTRUCT_QUALIFIERS): Likewise.
(LOADSTRUCTLANE_QUALIFIERS): Likewise.
(STORESTRUCT_QUALIFIERS): Likewise.
(STORESTRUCTLANE_QUALIFIERS): Likewise.
(neon_builtin_type_mode): Delete.
(v8qi_UP): Map to V8QImode.
(v8qi_UP): Map to V8QImode.
(v4hi_UP): Map to V4HImode.
(v4hf_UP): Map to V4HFmode.
(v2si_UP): Map to V2SImode.
(v2sf_UP): Map to V2SFmode.
(di_UP): Map to DImode.
(v16qi_UP): Map to V16QImode.
(v8hi_UP): Map to V8HImode.
(v4si_UP): Map to V4SImode.
(v4sf_UP): Map to V4SFmode.
(v2di_UP): Map to V2DImode.
(ti_UP): Map to TImode.
(ei_UP): Map to EImode.
(oi_UP): Map to OImode.
(neon_itype): Delete.
(neon_builtin_datum): Remove itype, make mode a machine_mode.
(VAR1): Update accordingly.
(arm_init_neon_builtins): Use machine_mode directly.
(neon_dereference_pointer): Likewise.
(arm_expand_neon_args): Use qualifiers to decide operand types.
(arm_expand_neon_builtin): Likewise.
* config/arm/arm_neon_builtins.def: Remap operation type for
many builtins.
2014-11-18 James Greenhalgh <james.greenhalgh@arm.com> 2014-11-18 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm-builtins.c (arm_scalar_builtin_types): New. * config/arm/arm-builtins.c (arm_scalar_builtin_types): New.

400
gcc/config/arm/arm-builtins.c
View File

@ -73,15 +73,6 @@ enum arm_type_qualifiers
static enum arm_type_qualifiers static enum arm_type_qualifiers
arm_unop_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_unop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_internal }; = { qualifier_none, qualifier_none, qualifier_internal };
#define CONVERT_QUALIFIERS (arm_unop_qualifiers)
#define COPYSIGNF_QUALIFIERS (arm_unop_qualifiers)
#define CREATE_QUALIFIERS (arm_unop_qualifiers)
#define DUP_QUALIFIERS (arm_unop_qualifiers)
#define FLOAT_WIDEN_QUALIFIERS (arm_unop_qualifiers)
#define FLOAT_NARROW_QUALIFIERS (arm_unop_qualifiers)
#define REINTERP_QUALIFIERS (arm_unop_qualifiers)
#define RINT_QUALIFIERS (arm_unop_qualifiers)
#define SPLIT_QUALIFIERS (arm_unop_qualifiers)
#define UNOP_QUALIFIERS (arm_unop_qualifiers) #define UNOP_QUALIFIERS (arm_unop_qualifiers)
/* unsigned T (unsigned T). */ /* unsigned T (unsigned T). */
@ -95,25 +86,18 @@ static enum arm_type_qualifiers
arm_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_maybe_immediate }; = { qualifier_none, qualifier_none, qualifier_maybe_immediate };
#define BINOP_QUALIFIERS (arm_binop_qualifiers) #define BINOP_QUALIFIERS (arm_binop_qualifiers)
#define FIXCONV_QUALIFIERS (arm_binop_qualifiers)
#define SCALARMUL_QUALIFIERS (arm_binop_qualifiers)
#define SCALARMULL_QUALIFIERS (arm_binop_qualifiers)
#define SCALARMULH_QUALIFIERS (arm_binop_qualifiers)
/* T (T, T, T). */ /* T (T, T, T). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
arm_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; = { qualifier_none, qualifier_none, qualifier_none, qualifier_none };
#define TERNOP_QUALIFIERS (arm_ternop_qualifiers) #define TERNOP_QUALIFIERS (arm_ternop_qualifiers)
#define SELECT_QUALIFIERS (arm_ternop_qualifiers)
#define VTBX_QUALIFIERS (arm_ternop_qualifiers)
/* T (T, immediate). */ /* T (T, immediate). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
arm_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_immediate }; = { qualifier_none, qualifier_none, qualifier_immediate };
#define GETLANE_QUALIFIERS (arm_getlane_qualifiers) #define GETLANE_QUALIFIERS (arm_getlane_qualifiers)
#define SHIFTIMM_QUALIFIERS (arm_getlane_qualifiers)
/* T (T, T, T, immediate). */ /* T (T, T, T, immediate). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
@ -121,32 +105,24 @@ arm_lanemac_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, = { qualifier_none, qualifier_none, qualifier_none,
qualifier_none, qualifier_immediate }; qualifier_none, qualifier_immediate };
#define LANEMAC_QUALIFIERS (arm_lanemac_qualifiers) #define LANEMAC_QUALIFIERS (arm_lanemac_qualifiers)
#define SCALARMAC_QUALIFIERS (arm_lanemac_qualifiers)
/* T (T, T, immediate). */ /* T (T, T, immediate). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
arm_setlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_setlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate }; = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
#define LANEMUL_QUALIFIERS (arm_setlane_qualifiers)
#define LANEMULH_QUALIFIERS (arm_setlane_qualifiers)
#define LANEMULL_QUALIFIERS (arm_setlane_qualifiers)
#define SETLANE_QUALIFIERS (arm_setlane_qualifiers) #define SETLANE_QUALIFIERS (arm_setlane_qualifiers)
#define SHIFTACC_QUALIFIERS (arm_setlane_qualifiers)
#define SHIFTINSERT_QUALIFIERS (arm_setlane_qualifiers)
/* T (T, T). */ /* T (T, T). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
arm_combine_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_combine_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none }; = { qualifier_none, qualifier_none, qualifier_none };
#define COMBINE_QUALIFIERS (arm_combine_qualifiers) #define COMBINE_QUALIFIERS (arm_combine_qualifiers)
#define VTBL_QUALIFIERS (arm_combine_qualifiers)
/* T ([T element type] *). */ /* T ([T element type] *). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
arm_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_const_pointer_map_mode }; = { qualifier_none, qualifier_const_pointer_map_mode };
#define LOAD1_QUALIFIERS (arm_load1_qualifiers) #define LOAD1_QUALIFIERS (arm_load1_qualifiers)
#define LOADSTRUCT_QUALIFIERS (arm_load1_qualifiers)
/* T ([T element type] *, T, immediate). */ /* T ([T element type] *, T, immediate). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
@ -154,7 +130,6 @@ arm_load1_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_const_pointer_map_mode, = { qualifier_none, qualifier_const_pointer_map_mode,
qualifier_none, qualifier_immediate }; qualifier_none, qualifier_immediate };
#define LOAD1LANE_QUALIFIERS (arm_load1_lane_qualifiers) #define LOAD1LANE_QUALIFIERS (arm_load1_lane_qualifiers)
#define LOADSTRUCTLANE_QUALIFIERS (arm_load1_lane_qualifiers)
/* The first argument (return type) of a store should be void type, /* The first argument (return type) of a store should be void type,
which we represent with qualifier_void. Their first operand will be which we represent with qualifier_void. Their first operand will be
@ -167,7 +142,6 @@ static enum arm_type_qualifiers
arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; = { qualifier_void, qualifier_pointer_map_mode, qualifier_none };
#define STORE1_QUALIFIERS (arm_store1_qualifiers) #define STORE1_QUALIFIERS (arm_store1_qualifiers)
#define STORESTRUCT_QUALIFIERS (arm_store1_qualifiers)
/* void ([T element type] *, T, immediate). */ /* void ([T element type] *, T, immediate). */
static enum arm_type_qualifiers static enum arm_type_qualifiers
@ -175,100 +149,27 @@ arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode, = { qualifier_void, qualifier_pointer_map_mode,
qualifier_none, qualifier_immediate }; qualifier_none, qualifier_immediate };
#define STORE1LANE_QUALIFIERS (arm_storestruct_lane_qualifiers) #define STORE1LANE_QUALIFIERS (arm_storestruct_lane_qualifiers)
#define STORESTRUCTLANE_QUALIFIERS (arm_storestruct_lane_qualifiers)
typedef enum { #define v8qi_UP V8QImode
T_V8QI, #define v4hi_UP V4HImode
T_V4HI, #define v4hf_UP V4HFmode
T_V4HF, #define v2si_UP V2SImode
T_V2SI, #define v2sf_UP V2SFmode
T_V2SF, #define di_UP DImode
T_DI, #define v16qi_UP V16QImode
T_V16QI, #define v8hi_UP V8HImode
T_V8HI, #define v4si_UP V4SImode
T_V4SI, #define v4sf_UP V4SFmode
T_V4SF, #define v2di_UP V2DImode
T_V2DI, #define ti_UP TImode
T_TI, #define ei_UP EImode
T_EI, #define oi_UP OImode
T_OI,
T_MAX /* Size of enum. Keep last. */
} neon_builtin_type_mode;
#define TYPE_MODE_BIT(X) (1 << (X))
#define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \
| TYPE_MODE_BIT (T_V4HF) | TYPE_MODE_BIT (T_V2SI) \
| TYPE_MODE_BIT (T_V2SF) | TYPE_MODE_BIT (T_DI))
#define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \
| TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \
| TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
#define v8qi_UP T_V8QI
#define v4hi_UP T_V4HI
#define v4hf_UP T_V4HF
#define v2si_UP T_V2SI
#define v2sf_UP T_V2SF
#define di_UP T_DI
#define v16qi_UP T_V16QI
#define v8hi_UP T_V8HI
#define v4si_UP T_V4SI
#define v4sf_UP T_V4SF
#define v2di_UP T_V2DI
#define ti_UP T_TI
#define ei_UP T_EI
#define oi_UP T_OI
#define UP(X) X##_UP #define UP(X) X##_UP
typedef enum {
NEON_BINOP,
NEON_TERNOP,
NEON_UNOP,
NEON_BSWAP,
NEON_GETLANE,
NEON_SETLANE,
NEON_CREATE,
NEON_RINT,
NEON_COPYSIGNF,
NEON_DUP,
NEON_DUPLANE,
NEON_COMBINE,
NEON_SPLIT,
NEON_LANEMUL,
NEON_LANEMULL,
NEON_LANEMULH,
NEON_LANEMAC,
NEON_SCALARMUL,
NEON_SCALARMULL,
NEON_SCALARMULH,
NEON_SCALARMAC,
NEON_CONVERT,
NEON_FLOAT_WIDEN,
NEON_FLOAT_NARROW,
NEON_FIXCONV,
NEON_SELECT,
NEON_REINTERP,
NEON_VTBL,
NEON_VTBX,
NEON_LOAD1,
NEON_LOAD1LANE,
NEON_STORE1,
NEON_STORE1LANE,
NEON_LOADSTRUCT,
NEON_LOADSTRUCTLANE,
NEON_STORESTRUCT,
NEON_STORESTRUCTLANE,
NEON_LOGICBINOP,
NEON_SHIFTINSERT,
NEON_SHIFTIMM,
NEON_SHIFTACC
} neon_itype;
typedef struct { typedef struct {
const char *name; const char *name;
const neon_itype itype; machine_mode mode;
const neon_builtin_type_mode mode;
const enum insn_code code; const enum insn_code code;
unsigned int fcode; unsigned int fcode;
enum arm_type_qualifiers *qualifiers; enum arm_type_qualifiers *qualifiers;
@ -277,7 +178,7 @@ typedef struct {
#define CF(N,X) CODE_FOR_neon_##N##X #define CF(N,X) CODE_FOR_neon_##N##X
#define VAR1(T, N, A) \ #define VAR1(T, N, A) \
{#N, NEON_##T, UP (A), CF (N, A), 0, T##_QUALIFIERS}, {#N #A, UP (A), CF (N, A), 0, T##_QUALIFIERS},
#define VAR2(T, N, A, B) \ #define VAR2(T, N, A, B) \
VAR1 (T, N, A) \ VAR1 (T, N, A) \
VAR1 (T, N, B) VAR1 (T, N, B)
@ -310,10 +211,8 @@ typedef struct {
The mode entries in the following table correspond to the "key" type of the The mode entries in the following table correspond to the "key" type of the
instruction variant, i.e. equivalent to that which would be specified after instruction variant, i.e. equivalent to that which would be specified after
the assembler mnemonic, which usually refers to the last vector operand. the assembler mnemonic, which usually refers to the last vector operand.
(Signed/unsigned/polynomial types are not differentiated between though, and The modes listed per instruction should be the same as those defined for
are all mapped onto the same mode for a given element size.) The modes that instruction's pattern in neon.md. */
listed per instruction should be the same as those defined for that
instruction's pattern in neon.md. */
static neon_builtin_datum neon_builtin_data[] = static neon_builtin_datum neon_builtin_data[] =
{ {
@ -980,25 +879,10 @@ arm_init_neon_builtins (void)
bool print_type_signature_p = false; bool print_type_signature_p = false;
char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 }; char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 };
neon_builtin_datum *d = &neon_builtin_data[i]; neon_builtin_datum *d = &neon_builtin_data[i];
const char *const modenames[] =
{
"v8qi", "v4hi", "v4hf", "v2si", "v2sf", "di",
"v16qi", "v8hi", "v4si", "v4sf", "v2di",
"ti", "ei", "oi"
};
const enum machine_mode modes[] =
{
V8QImode, V4HImode, V4HFmode, V2SImode, V2SFmode, DImode,
V16QImode, V8HImode, V4SImode, V4SFmode, V2DImode,
TImode, EImode, OImode
};
char namebuf[60]; char namebuf[60];
tree ftype = NULL; tree ftype = NULL;
tree fndecl = NULL; tree fndecl = NULL;
gcc_assert (ARRAY_SIZE (modenames) == T_MAX);
d->fcode = fcode; d->fcode = fcode;
/* We must track two variables here. op_num is /* We must track two variables here. op_num is
@ -1046,7 +930,7 @@ arm_init_neon_builtins (void)
/* Some builtins have different user-facing types /* Some builtins have different user-facing types
for certain arguments, encoded in d->mode. */ for certain arguments, encoded in d->mode. */
if (qualifiers & qualifier_map_mode) if (qualifiers & qualifier_map_mode)
op_mode = modes[d->mode]; op_mode = d->mode;
/* For pointers, we want a pointer to the basic type /* For pointers, we want a pointer to the basic type
of the vector. */ of the vector. */
@ -1080,11 +964,11 @@ arm_init_neon_builtins (void)
gcc_assert (ftype != NULL); gcc_assert (ftype != NULL);
if (print_type_signature_p) if (print_type_signature_p)
snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s%s_%s", snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s_%s",
d->name, modenames[d->mode], type_signature); d->name, type_signature);
else else
snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s%s", snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s",
d->name, modenames[d->mode]); d->name);
fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD,
NULL, NULL_TREE); NULL, NULL_TREE);
@ -2048,7 +1932,7 @@ typedef enum {
static tree static tree
neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode, neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode,
machine_mode reg_mode, machine_mode reg_mode,
neon_builtin_type_mode type_mode) machine_mode vector_mode)
{ {
HOST_WIDE_INT reg_size, vector_size, nvectors, nelems; HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
tree elem_type, upper_bound, array_type; tree elem_type, upper_bound, array_type;
@ -2057,8 +1941,7 @@ neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode,
reg_size = GET_MODE_SIZE (reg_mode); reg_size = GET_MODE_SIZE (reg_mode);
/* Work out the size of each vector in bytes. */ /* Work out the size of each vector in bytes. */
gcc_assert (TYPE_MODE_BIT (type_mode) & (TB_DREG | TB_QREG)); vector_size = GET_MODE_SIZE (vector_mode);
vector_size = (TYPE_MODE_BIT (type_mode) & TB_QREG ? 16 : 8);
/* Work out how many vectors there are. */ /* Work out how many vectors there are. */
gcc_assert (reg_size % vector_size == 0); gcc_assert (reg_size % vector_size == 0);
@ -2087,21 +1970,17 @@ neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode,
/* Expand a Neon builtin. */ /* Expand a Neon builtin. */
static rtx static rtx
arm_expand_neon_args (rtx target, int icode, int have_retval, arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
neon_builtin_type_mode type_mode, int icode, int have_retval, tree exp, ...)
tree exp, int fcode, ...)
{ {
va_list ap; va_list ap;
rtx pat; rtx pat;
tree arg[NEON_MAX_BUILTIN_ARGS]; tree arg[SIMD_MAX_BUILTIN_ARGS];
rtx op[NEON_MAX_BUILTIN_ARGS]; rtx op[SIMD_MAX_BUILTIN_ARGS];
tree arg_type;
tree formals;
machine_mode tmode = insn_data[icode].operand[0].mode; machine_mode tmode = insn_data[icode].operand[0].mode;
machine_mode mode[NEON_MAX_BUILTIN_ARGS]; machine_mode mode[SIMD_MAX_BUILTIN_ARGS];
machine_mode other_mode; tree formals;
int argc = 0; int argc = 0;
int opno;
if (have_retval if (have_retval
&& (!target && (!target
@ -2109,7 +1988,7 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
|| !(*insn_data[icode].operand[0].predicate) (target, tmode))) || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
target = gen_reg_rtx (tmode); target = gen_reg_rtx (tmode);
va_start (ap, fcode); va_start (ap, exp);
formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode])); formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode]));
@ -2118,19 +1997,20 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
builtin_arg thisarg = (builtin_arg) va_arg (ap, int); builtin_arg thisarg = (builtin_arg) va_arg (ap, int);
if (thisarg == NEON_ARG_STOP) if (thisarg == NEON_ARG_STOP)
break; break;
else else
{ {
opno = argc + have_retval; int opno = argc + have_retval;
mode[argc] = insn_data[icode].operand[opno].mode; arg[argc] = CALL_EXPR_ARG (exp, argc);
arg[argc] = CALL_EXPR_ARG (exp, argc); mode[argc] = insn_data[icode].operand[opno].mode;
arg_type = TREE_VALUE (formals);
if (thisarg == NEON_ARG_MEMORY) if (thisarg == NEON_ARG_MEMORY)
{ {
other_mode = insn_data[icode].operand[1 - opno].mode; machine_mode other_mode
arg[argc] = neon_dereference_pointer (arg[argc], arg_type, = insn_data[icode].operand[1 - opno].mode;
arg[argc] = neon_dereference_pointer (arg[argc],
TREE_VALUE (formals),
mode[argc], other_mode, mode[argc], other_mode,
type_mode); map_mode);
} }
/* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P /* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P
@ -2139,22 +2019,23 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
(thisarg == NEON_ARG_MEMORY (thisarg == NEON_ARG_MEMORY
? EXPAND_MEMORY : EXPAND_NORMAL)); ? EXPAND_MEMORY : EXPAND_NORMAL));
switch (thisarg) switch (thisarg)
{ {
case NEON_ARG_COPY_TO_REG: case NEON_ARG_COPY_TO_REG:
/*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ if (POINTER_TYPE_P (TREE_TYPE (arg[argc])))
if (!(*insn_data[icode].operand[opno].predicate) op[argc] = convert_memory_address (Pmode, op[argc]);
(op[argc], mode[argc])) /*gcc_assert (GET_MODE (op[argc]) == mode[argc]); */
op[argc] = copy_to_mode_reg (mode[argc], op[argc]); if (!(*insn_data[icode].operand[opno].predicate)
break; (op[argc], mode[argc]))
op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
case NEON_ARG_CONSTANT: break;
/* FIXME: This error message is somewhat unhelpful. */
if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc]))
error ("argument must be a constant");
break;
case NEON_ARG_CONSTANT:
if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc]))
error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
"expected %<const int%>", argc + 1);
break;
case NEON_ARG_MEMORY: case NEON_ARG_MEMORY:
/* Check if expand failed. */ /* Check if expand failed. */
if (op[argc] == const0_rtx) if (op[argc] == const0_rtx)
@ -2166,18 +2047,17 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
alias safe. */ alias safe. */
set_mem_alias_set (op[argc], 0); set_mem_alias_set (op[argc], 0);
if (!(*insn_data[icode].operand[opno].predicate) if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc])) (op[argc], mode[argc]))
op[argc] = (replace_equiv_address op[argc] = (replace_equiv_address
(op[argc], force_reg (Pmode, XEXP (op[argc], 0)))); (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
break; break;
case NEON_ARG_STOP: case NEON_ARG_STOP:
gcc_unreachable (); gcc_unreachable ();
} }
argc++; argc++;
formals = TREE_CHAIN (formals); }
}
} }
va_end (ap); va_end (ap);
@ -2229,7 +2109,7 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
case 5: case 5:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
break; break;
default: default:
gcc_unreachable (); gcc_unreachable ();
@ -2249,113 +2129,61 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
static rtx static rtx
arm_expand_neon_builtin (int fcode, tree exp, rtx target) arm_expand_neon_builtin (int fcode, tree exp, rtx target)
{ {
neon_builtin_datum *d = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE]; neon_builtin_datum *d =
neon_itype itype = d->itype; &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE];
enum insn_code icode = d->code; enum insn_code icode = d->code;
neon_builtin_type_mode type_mode = d->mode; builtin_arg args[SIMD_MAX_BUILTIN_ARGS];
int num_args = insn_data[d->code].n_operands;
int is_void = 0;
int k;
switch (itype) is_void = !!(d->qualifiers[0] & qualifier_void);
num_args += is_void;
for (k = 1; k < num_args; k++)
{ {
case NEON_UNOP: /* We have four arrays of data, each indexed in a different fashion.
case NEON_CONVERT: qualifiers - element 0 always describes the function return type.
case NEON_DUPLANE: operands - element 0 is either the operand for return value (if
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, the function has a non-void return type) or the operand for the
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); first argument.
expr_args - element 0 always holds the first argument.
args - element 0 is always used for the return type. */
int qualifiers_k = k;
int operands_k = k - is_void;
int expr_args_k = k - 1;
case NEON_BINOP: if (d->qualifiers[qualifiers_k] & qualifier_immediate)
case NEON_LOGICBINOP: args[k] = NEON_ARG_CONSTANT;
case NEON_SCALARMUL: else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
case NEON_SCALARMULL: {
case NEON_SCALARMULH: rtx arg
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, = expand_normal (CALL_EXPR_ARG (exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); (expr_args_k)));
/* Handle constants only if the predicate allows it. */
case NEON_TERNOP: bool op_const_int_p =
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, (CONST_INT_P (arg)
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, && (*insn_data[icode].operand[operands_k].predicate)
NEON_ARG_STOP); (arg, insn_data[icode].operand[operands_k].mode));
args[k] = op_const_int_p ? NEON_ARG_CONSTANT : NEON_ARG_COPY_TO_REG;
case NEON_GETLANE: }
case NEON_FIXCONV: else if (d->qualifiers[qualifiers_k] & qualifier_pointer)
case NEON_SHIFTIMM: args[k] = NEON_ARG_MEMORY;
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, else
NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, args[k] = NEON_ARG_COPY_TO_REG;
NEON_ARG_STOP);
case NEON_CREATE:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_DUP:
case NEON_RINT:
case NEON_SPLIT:
case NEON_FLOAT_WIDEN:
case NEON_FLOAT_NARROW:
case NEON_BSWAP:
case NEON_REINTERP:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_COPYSIGNF:
case NEON_COMBINE:
case NEON_VTBL:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_LANEMUL:
case NEON_LANEMULL:
case NEON_LANEMULH:
case NEON_SETLANE:
case NEON_SHIFTINSERT:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_STOP);
case NEON_LANEMAC:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_CONSTANT, NEON_ARG_STOP);
case NEON_SHIFTACC:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_STOP);
case NEON_SCALARMAC:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_STOP);
case NEON_SELECT:
case NEON_VTBX:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_STOP);
case NEON_LOAD1:
case NEON_LOADSTRUCT:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_MEMORY, NEON_ARG_STOP);
case NEON_LOAD1LANE:
case NEON_LOADSTRUCTLANE:
return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_STOP);
case NEON_STORE1:
case NEON_STORESTRUCT:
return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_STORE1LANE:
case NEON_STORESTRUCTLANE:
return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_STOP);
} }
args[k] = NEON_ARG_STOP;
gcc_unreachable (); /* The interface to arm_expand_neon_args expects a 0 if
the function is void, and a 1 if it is not. */
return arm_expand_neon_args
(target, d->mode, fcode, icode, !is_void, exp,
args[1],
args[2],
args[3],
args[4],
NEON_ARG_STOP);
} }
/* Expand an expression EXP that calls a built-in function, /* Expand an expression EXP that calls a built-in function,

218
gcc/config/arm/arm_neon_builtins.def
View File

@ -48,16 +48,16 @@ VAR2 (TERNOP, vqdmlsl, v4hi, v2si)
VAR3 (BINOP, vmullp, v8qi, v4hi, v2si) VAR3 (BINOP, vmullp, v8qi, v4hi, v2si)
VAR3 (BINOP, vmulls, v8qi, v4hi, v2si) VAR3 (BINOP, vmulls, v8qi, v4hi, v2si)
VAR3 (BINOP, vmullu, v8qi, v4hi, v2si) VAR3 (BINOP, vmullu, v8qi, v4hi, v2si)
VAR2 (SCALARMULL, vmulls_n, v4hi, v2si) VAR2 (BINOP, vmulls_n, v4hi, v2si)
VAR2 (SCALARMULL, vmullu_n, v4hi, v2si) VAR2 (BINOP, vmullu_n, v4hi, v2si)
VAR2 (LANEMULL, vmulls_lane, v4hi, v2si) VAR2 (SETLANE, vmulls_lane, v4hi, v2si)
VAR2 (LANEMULL, vmullu_lane, v4hi, v2si) VAR2 (SETLANE, vmullu_lane, v4hi, v2si)
VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) VAR2 (BINOP, vqdmull_n, v4hi, v2si)
VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) VAR2 (SETLANE, vqdmull_lane, v4hi, v2si)
VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) VAR4 (BINOP, vqdmulh_n, v4hi, v2si, v8hi, v4si)
VAR4 (SCALARMULH, vqrdmulh_n, v4hi, v2si, v8hi, v4si) VAR4 (BINOP, vqrdmulh_n, v4hi, v2si, v8hi, v4si)
VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) VAR4 (SETLANE, vqdmulh_lane, v4hi, v2si, v8hi, v4si)
VAR4 (LANEMULH, vqrdmulh_lane, v4hi, v2si, v8hi, v4si) VAR4 (SETLANE, vqrdmulh_lane, v4hi, v2si, v8hi, v4si)
VAR2 (BINOP, vqdmull, v4hi, v2si) VAR2 (BINOP, vqdmull, v4hi, v2si)
VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
@ -67,28 +67,28 @@ VAR8 (BINOP, vqshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (BINOP, vqshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (BINOP, vqshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (BINOP, vqrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (BINOP, vqrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (BINOP, vqrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (BINOP, vqrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vrshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vrshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vrshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vrshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) VAR3 (GETLANE, vshrn_n, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vrshrn_n, v8hi, v4si, v2di) VAR3 (GETLANE, vrshrn_n, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vqshrns_n, v8hi, v4si, v2di) VAR3 (GETLANE, vqshrns_n, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vqshrnu_n, v8hi, v4si, v2di) VAR3 (GETLANE, vqshrnu_n, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vqrshrns_n, v8hi, v4si, v2di) VAR3 (GETLANE, vqrshrns_n, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vqrshrnu_n, v8hi, v4si, v2di) VAR3 (GETLANE, vqrshrnu_n, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) VAR3 (GETLANE, vqshrun_n, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vqrshrun_n, v8hi, v4si, v2di) VAR3 (GETLANE, vqrshrun_n, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vqshl_s_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vqshl_s_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vqshl_u_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vqshl_u_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (GETLANE, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR3 (SHIFTIMM, vshlls_n, v8qi, v4hi, v2si) VAR3 (GETLANE, vshlls_n, v8qi, v4hi, v2si)
VAR3 (SHIFTIMM, vshllu_n, v8qi, v4hi, v2si) VAR3 (GETLANE, vshllu_n, v8qi, v4hi, v2si)
VAR8 (SHIFTACC, vsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (SETLANE, vsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTACC, vsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (SETLANE, vsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTACC, vrsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (SETLANE, vrsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTACC, vrsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (SETLANE, vrsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR2 (BINOP, vsub, v2sf, v4sf) VAR2 (BINOP, vsub, v2sf, v4sf)
VAR3 (BINOP, vsubls, v8qi, v4hi, v2si) VAR3 (BINOP, vsubls, v8qi, v4hi, v2si)
VAR3 (BINOP, vsublu, v8qi, v4hi, v2si) VAR3 (BINOP, vsublu, v8qi, v4hi, v2si)
@ -140,8 +140,8 @@ VAR6 (BINOP, vpadals, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
VAR6 (BINOP, vpadalu, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR6 (BINOP, vpadalu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
VAR2 (BINOP, vrecps, v2sf, v4sf) VAR2 (BINOP, vrecps, v2sf, v4sf)
VAR2 (BINOP, vrsqrts, v2sf, v4sf) VAR2 (BINOP, vrsqrts, v2sf, v4sf)
VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (SETLANE, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (SETLANE, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
@ -159,21 +159,21 @@ VAR10 (GETLANE, vget_lane,
VAR6 (GETLANE, vget_laneu, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR6 (GETLANE, vget_laneu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
VAR10 (SETLANE, vset_lane, VAR10 (SETLANE, vset_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) VAR5 (UNOP, vcreate, v8qi, v4hi, v2si, v2sf, di)
VAR10 (DUP, vdup_n, VAR10 (UNOP, vdup_n,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR10 (BINOP, vdup_lane, VAR10 (BINOP, vdup_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di)
VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) VAR5 (UNOP, vget_high, v16qi, v8hi, v4si, v4sf, v2di)
VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) VAR5 (UNOP, vget_low, v16qi, v8hi, v4si, v4sf, v2di)
VAR3 (UNOP, vmovn, v8hi, v4si, v2di) VAR3 (UNOP, vmovn, v8hi, v4si, v2di)
VAR3 (UNOP, vqmovns, v8hi, v4si, v2di) VAR3 (UNOP, vqmovns, v8hi, v4si, v2di)
VAR3 (UNOP, vqmovnu, v8hi, v4si, v2di) VAR3 (UNOP, vqmovnu, v8hi, v4si, v2di)
VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) VAR3 (UNOP, vqmovun, v8hi, v4si, v2di)
VAR3 (UNOP, vmovls, v8qi, v4hi, v2si) VAR3 (UNOP, vmovls, v8qi, v4hi, v2si)
VAR3 (UNOP, vmovlu, v8qi, v4hi, v2si) VAR3 (UNOP, vmovlu, v8qi, v4hi, v2si)
VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) VAR6 (SETLANE, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR2 (LANEMAC, vmlals_lane, v4hi, v2si) VAR2 (LANEMAC, vmlals_lane, v4hi, v2si)
VAR2 (LANEMAC, vmlalu_lane, v4hi, v2si) VAR2 (LANEMAC, vmlalu_lane, v4hi, v2si)
@ -182,66 +182,66 @@ VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR2 (LANEMAC, vmlsls_lane, v4hi, v2si) VAR2 (LANEMAC, vmlsls_lane, v4hi, v2si)
VAR2 (LANEMAC, vmlslu_lane, v4hi, v2si) VAR2 (LANEMAC, vmlslu_lane, v4hi, v2si)
VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si)
VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) VAR6 (BINOP, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) VAR6 (LANEMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR2 (SCALARMAC, vmlals_n, v4hi, v2si) VAR2 (LANEMAC, vmlals_n, v4hi, v2si)
VAR2 (SCALARMAC, vmlalu_n, v4hi, v2si) VAR2 (LANEMAC, vmlalu_n, v4hi, v2si)
VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) VAR2 (LANEMAC, vqdmlal_n, v4hi, v2si)
VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) VAR6 (LANEMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR2 (SCALARMAC, vmlsls_n, v4hi, v2si) VAR2 (LANEMAC, vmlsls_n, v4hi, v2si)
VAR2 (SCALARMAC, vmlslu_n, v4hi, v2si) VAR2 (LANEMAC, vmlslu_n, v4hi, v2si)
VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) VAR2 (LANEMAC, vqdmlsl_n, v4hi, v2si)
VAR10 (SHIFTINSERT, vext, VAR10 (SETLANE, vext,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi)
VAR2 (UNOP, vrev16, v8qi, v16qi) VAR2 (UNOP, vrev16, v8qi, v16qi)
VAR4 (CONVERT, vcvts, v2si, v2sf, v4si, v4sf) VAR4 (UNOP, vcvts, v2si, v2sf, v4si, v4sf)
VAR4 (CONVERT, vcvtu, v2si, v2sf, v4si, v4sf) VAR4 (UNOP, vcvtu, v2si, v2sf, v4si, v4sf)
VAR4 (FIXCONV, vcvts_n, v2si, v2sf, v4si, v4sf) VAR4 (BINOP, vcvts_n, v2si, v2sf, v4si, v4sf)
VAR4 (FIXCONV, vcvtu_n, v2si, v2sf, v4si, v4sf) VAR4 (BINOP, vcvtu_n, v2si, v2sf, v4si, v4sf)
VAR1 (FLOAT_WIDEN, vcvtv4sf, v4hf) VAR1 (UNOP, vcvtv4sf, v4hf)
VAR1 (FLOAT_NARROW, vcvtv4hf, v4sf) VAR1 (UNOP, vcvtv4hf, v4sf)
VAR10 (SELECT, vbsl, VAR10 (TERNOP, vbsl,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR2 (COPYSIGNF, copysignf, v2sf, v4sf) VAR2 (UNOP, copysignf, v2sf, v4sf)
VAR2 (RINT, vrintn, v2sf, v4sf) VAR2 (UNOP, vrintn, v2sf, v4sf)
VAR2 (RINT, vrinta, v2sf, v4sf) VAR2 (UNOP, vrinta, v2sf, v4sf)
VAR2 (RINT, vrintp, v2sf, v4sf) VAR2 (UNOP, vrintp, v2sf, v4sf)
VAR2 (RINT, vrintm, v2sf, v4sf) VAR2 (UNOP, vrintm, v2sf, v4sf)
VAR2 (RINT, vrintz, v2sf, v4sf) VAR2 (UNOP, vrintz, v2sf, v4sf)
VAR2 (RINT, vrintx, v2sf, v4sf) VAR2 (UNOP, vrintx, v2sf, v4sf)
VAR1 (RINT, vcvtav2sf, v2si) VAR1 (UNOP, vcvtav2sf, v2si)
VAR1 (RINT, vcvtav4sf, v4si) VAR1 (UNOP, vcvtav4sf, v4si)
VAR1 (RINT, vcvtauv2sf, v2si) VAR1 (UNOP, vcvtauv2sf, v2si)
VAR1 (RINT, vcvtauv4sf, v4si) VAR1 (UNOP, vcvtauv4sf, v4si)
VAR1 (RINT, vcvtpv2sf, v2si) VAR1 (UNOP, vcvtpv2sf, v2si)
VAR1 (RINT, vcvtpv4sf, v4si) VAR1 (UNOP, vcvtpv4sf, v4si)
VAR1 (RINT, vcvtpuv2sf, v2si) VAR1 (UNOP, vcvtpuv2sf, v2si)
VAR1 (RINT, vcvtpuv4sf, v4si) VAR1 (UNOP, vcvtpuv4sf, v4si)
VAR1 (RINT, vcvtmv2sf, v2si) VAR1 (UNOP, vcvtmv2sf, v2si)
VAR1 (RINT, vcvtmv4sf, v4si) VAR1 (UNOP, vcvtmv4sf, v4si)
VAR1 (RINT, vcvtmuv2sf, v2si) VAR1 (UNOP, vcvtmuv2sf, v2si)
VAR1 (RINT, vcvtmuv4sf, v4si) VAR1 (UNOP, vcvtmuv4sf, v4si)
VAR1 (VTBL, vtbl1, v8qi) VAR1 (COMBINE, vtbl1, v8qi)
VAR1 (VTBL, vtbl2, v8qi) VAR1 (COMBINE, vtbl2, v8qi)
VAR1 (VTBL, vtbl3, v8qi) VAR1 (COMBINE, vtbl3, v8qi)
VAR1 (VTBL, vtbl4, v8qi) VAR1 (COMBINE, vtbl4, v8qi)
VAR1 (VTBX, vtbx1, v8qi) VAR1 (TERNOP, vtbx1, v8qi)
VAR1 (VTBX, vtbx2, v8qi) VAR1 (TERNOP, vtbx2, v8qi)
VAR1 (VTBX, vtbx3, v8qi) VAR1 (TERNOP, vtbx3, v8qi)
VAR1 (VTBX, vtbx4, v8qi) VAR1 (TERNOP, vtbx4, v8qi)
VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) VAR5 (UNOP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di)
VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) VAR5 (UNOP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di)
VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) VAR5 (UNOP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di)
VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) VAR5 (UNOP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di)
VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) VAR5 (UNOP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di)
VAR6 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di, ti) VAR6 (UNOP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di, ti)
VAR6 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di, ti) VAR6 (UNOP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di, ti)
VAR6 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di, ti) VAR6 (UNOP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di, ti)
VAR6 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di, ti) VAR6 (UNOP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di, ti)
VAR6 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di, ti) VAR6 (UNOP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di, ti)
VAR6 (REINTERP, vreinterpretti, v16qi, v8hi, v4si, v4sf, v2di, ti) VAR6 (UNOP, vreinterpretti, v16qi, v8hi, v4si, v4sf, v2di, ti)
VAR10 (LOAD1, vld1, VAR10 (LOAD1, vld1,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR10 (LOAD1LANE, vld1_lane, VAR10 (LOAD1LANE, vld1_lane,
@ -252,30 +252,30 @@ VAR10 (STORE1, vst1,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR10 (STORE1LANE, vst1_lane, VAR10 (STORE1LANE, vst1_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR9 (LOADSTRUCT, vld2, VAR9 (LOAD1, vld2,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
VAR7 (LOADSTRUCTLANE, vld2_lane, VAR7 (LOAD1LANE, vld2_lane,
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) VAR5 (LOAD1, vld2_dup, v8qi, v4hi, v2si, v2sf, di)
VAR9 (STORESTRUCT, vst2, VAR9 (STORE1, vst2,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
VAR7 (STORESTRUCTLANE, vst2_lane, VAR7 (STORE1LANE, vst2_lane,
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR9 (LOADSTRUCT, vld3, VAR9 (LOAD1, vld3,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
VAR7 (LOADSTRUCTLANE, vld3_lane, VAR7 (LOAD1LANE, vld3_lane,
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) VAR5 (LOAD1, vld3_dup, v8qi, v4hi, v2si, v2sf, di)
VAR9 (STORESTRUCT, vst3, VAR9 (STORE1, vst3,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
VAR7 (STORESTRUCTLANE, vst3_lane, VAR7 (STORE1LANE, vst3_lane,
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR9 (LOADSTRUCT, vld4, VAR9 (LOAD1, vld4,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
VAR7 (LOADSTRUCTLANE, vld4_lane, VAR7 (LOAD1LANE, vld4_lane,
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) VAR5 (LOAD1, vld4_dup, v8qi, v4hi, v2si, v2sf, di)
VAR9 (STORESTRUCT, vst4, VAR9 (STORE1, vst4,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf)
VAR7 (STORESTRUCTLANE, vst4_lane, VAR7 (STORE1LANE, vst4_lane,
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)