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mips.h (ISA_HAS_INT_CONDMOVE): Delete.

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* config/mips/mips.h (ISA_HAS_INT_CONDMOVE): Delete.
	* config/mips/mips.c (print_operand): Fold %B/%b handling into %T/%t,
	using the mode of the operand to decide between them.
	* config/mips/mips.md (MOVECC): New mode macro.
	(ccreg): New mode attribute.
	(*mov{si,di,sf,df}_on_{cc,si,di}): Name formerly unnamed patterns.
	Redefine using :GPR and :MOVECC.  Use %T and %t for the condition.
	(mov[sd]icc): Redefine using :GPR.

From-SVN: r86515
This commit is contained in:
Richard Sandiford 2004-08-24 20:43:57 +00:00 committed by Richard Sandiford
parent 0455023232
commit b3c90666df
4 changed files with 57 additions and 192 deletions
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11
gcc/ChangeLog
View File

@ -1,3 +1,14 @@
2004-08-24 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (ISA_HAS_INT_CONDMOVE): Delete.
* config/mips/mips.c (print_operand): Fold %B/%b handling into %T/%t,
using the mode of the operand to decide between them.
* config/mips/mips.md (MOVECC): New mode macro.
(ccreg): New mode attribute.
(*mov{si,di,sf,df}_on_{cc,si,di}): Name formerly unnamed patterns.
Redefine using :GPR and :MOVECC. Use %T and %t for the condition.
(mov[sd]icc): Redefine using :GPR.
2004-08-24 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (mips_emit_prefetch): Delete.

20
gcc/config/mips/mips.c
View File

@ -4480,10 +4480,9 @@ mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
'F' print part of opcode for a floating-point branch condition.
'N' print part of opcode for a branch condition, inverted.
'W' print part of opcode for a floating-point branch condition, inverted.
'B' print 'z' for EQ, 'n' for NE
'b' print 'n' for EQ, 'z' for NE
'T' print 'f' for EQ, 't' for NE
't' print 't' for EQ, 'f' for NE
'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
'z' for (eq:?I ...), 'n' for (ne:?I ...).
't' like 'T', but with the EQ/NE cases reversed
'Z' print register and a comma, but print nothing for $fcc0
'R' print the reloc associated with LO_SUM
@ -4772,14 +4771,11 @@ print_operand (FILE *file, rtx op, int letter)
else if (letter == 'd' || letter == 'x' || letter == 'X')
output_operand_lossage ("invalid use of %%d, %%x, or %%X");
else if (letter == 'B')
fputs (code == EQ ? "z" : "n", file);
else if (letter == 'b')
fputs (code == EQ ? "n" : "z", file);
else if (letter == 'T')
fputs (code == EQ ? "f" : "t", file);
else if (letter == 't')
fputs (code == EQ ? "t" : "f", file);
else if (letter == 'T' || letter == 't')
{
int truth = (code == NE) == (letter == 'T');
fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
}
else if (CONST_GP_P (op))
fputs (reg_names[GLOBAL_POINTER_REGNUM], file);

3
gcc/config/mips/mips.h
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@ -824,9 +824,6 @@ extern const struct mips_cpu_info *mips_tune_info;
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
/* ISA has just the integer condition move instructions (movn,movz) */
#define ISA_HAS_INT_CONDMOVE 0
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (ISA_MIPS4 \

215
gcc/config/mips/mips.md
View File

@ -293,6 +293,10 @@
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
;; This mode macro allows :MOVECC to be used anywhere that a
;; conditional-move-type condition is needed.
(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")])
@ -306,6 +310,10 @@
;; field but the equivalent daddiu has only a 5-bit field.
(define_mode_attr si8_di5 [(SI "8") (DI "5")])
;; In MOVECC templates, this attribute gives the constraint to use
;; for the condition register.
(define_mode_attr ccreg [(SI "d") (DI "d") (CC "z")])
;; This code macro allows all branch instructions to be generated from
;; a single define_expand template.
(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
@ -6019,207 +6027,60 @@ beq\t%2,%.,1b\;\
;; MIPS4 Conditional move instructions.
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
(match_operator:SI 4 "equality_operator"
[(match_operand:SI 1 "register_operand" "d,d")
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(if_then_else:GPR
(match_operator:MOVECC 4 "equality_operator"
[(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
(const_int 0)])
(match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
(match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
mov%T4\t%0,%z2,%1
mov%t4\t%0,%z3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "SI")])
(set_attr "mode" "<GPR:MODE>")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
(match_operator:DI 4 "equality_operator"
[(match_operand:DI 1 "register_operand" "d,d")
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
(match_operator:CC 3 "equality_operator"
[(match_operand:CC 4 "register_operand" "z,z")
(const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3\t%0,%z1,%4
mov%t3\t%0,%z2,%4"
[(set_attr "type" "condmove")
(set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
(match_operator:SI 4 "equality_operator"
[(match_operand:SI 1 "register_operand" "d,d")
(const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
(match_operator:DI 4 "equality_operator"
[(match_operand:DI 1 "register_operand" "d,d")
(const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
(match_operator:CC 3 "equality_operator"
[(match_operand:CC 4 "register_operand" "z,z")
(const_int 0)])
(match_operand:DI 1 "reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
"@
mov%T3\t%0,%z1,%4
mov%t3\t%0,%z2,%4"
[(set_attr "type" "condmove")
(set_attr "mode" "DI")])
(define_insn ""
(define_insn "*movsf_on_<MOVECC:mode>"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
(match_operator:SI 4 "equality_operator"
[(match_operand:SI 1 "register_operand" "d,d")
(const_int 0)])
(match_operator:MOVECC 4 "equality_operator"
[(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\t%0,%2,%1
mov%b4.s\t%0,%3,%1"
mov%T4.s\t%0,%2,%1
mov%t4.s\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
(match_operator:DI 4 "equality_operator"
[(match_operand:DI 1 "register_operand" "d,d")
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\t%0,%2,%1
mov%b4.s\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
(match_operator:CC 3 "equality_operator"
[(match_operand:CC 4 "register_operand" "z,z")
(const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3.s\t%0,%1,%4
mov%t3.s\t%0,%2,%4"
[(set_attr "type" "condmove")
(set_attr "mode" "SF")])
(define_insn ""
(define_insn "*movdf_on_<MOVECC:mode>"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
(match_operator:SI 4 "equality_operator"
[(match_operand:SI 1 "register_operand" "d,d")
(const_int 0)])
(match_operator:MOVECC 4 "equality_operator"
[(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\t%0,%2,%1
mov%b4.d\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
(match_operator:DI 4 "equality_operator"
[(match_operand:DI 1 "register_operand" "d,d")
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\t%0,%2,%1
mov%b4.d\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
(match_operator:CC 3 "equality_operator"
[(match_operand:CC 4 "register_operand" "z,z")
(const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%T3.d\t%0,%1,%4
mov%t3.d\t%0,%2,%4"
mov%T4.d\t%0,%2,%1
mov%t4.d\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "DF")])
;; These are the main define_expand's used to make conditional moves.
(define_expand "movsicc"
(define_expand "mov<mode>cc"
[(set (match_dup 4) (match_operand 1 "comparison_operator"))
(set (match_operand:SI 0 "register_operand")
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand")
(match_operand:SI 3 "reg_or_0_operand")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
{
gen_conditional_move (operands);
DONE;
})
(define_expand "movdicc"
[(set (match_dup 4) (match_operand 1 "comparison_operator"))
(set (match_operand:DI 0 "register_operand")
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "reg_or_0_operand")
(match_operand:DI 3 "reg_or_0_operand")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
(set (match_operand:GPR 0 "register_operand")
(if_then_else:GPR (match_dup 5)
(match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "reg_or_0_operand")))]
"ISA_HAS_CONDMOVE"
{
gen_conditional_move (operands);
DONE;