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Add new nds32 port, including machine description, libgcc, and documentation.

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[gcc/ChangeLog]
	* config.gcc (nds32*-*-*): Add nds32 target.
	* config/nds32/nds32.c: New file.
	* config/nds32/nds32.h: New file.
	* config/nds32/nds32.md: New file.
	* config/nds32/constants.md: New file.
	* config/nds32/constraints.md: New file.
	* config/nds32/iterators.md: New file.
	* config/nds32/nds32-doubleword.md: New file.
	* config/nds32/nds32-intrinsic.md: New file.
	* config/nds32/nds32_intrinsic.h: New file.
	* config/nds32/nds32-modes.def: New file.
	* config/nds32/nds32-multiple.md: New file.
	* config/nds32/nds32.opt: New file.
	* config/nds32/nds32-opts.h: New file.
	* config/nds32/nds32-protos.h: New file.
	* config/nds32/nds32-peephole2.md: New file.
	* config/nds32/pipelines.md: New file.
	* config/nds32/predicates.md: New file.
	* config/nds32/t-mlibs: New file.
	* common/config/nds32: New directory and files.

	* doc/invoke.texi (NDS32 options): Document nds32 specific options.
	* doc/md.texi (NDS32 family): Document nds32 specific constraints.
	* doc/install.texi (Cross-Compiler-Specific Options): Document
	--with-nds32-lib for nds32 target.
	* doc/extend.texi (Function Attributes, Target Builtins): Document
	nds32 specific attributes.
	
[libgcc/ChangeLog]
	* config.host (nds32*-elf*): Add nds32 target.
	* config/nds32 : New directory and files.
	
[contrib/ChangeLog]
	* config-list.mk (nds32le-elf, nds32be-elf): Add nds32 target.

Co-Authored-By: Shiva Chen <shiva0217@gmail.com>

From-SVN: r204269
This commit is contained in:
Chung-Ju Wu 2013-10-31 17:08:16 +00:00 committed by Chung-Ju Wu
parent 7214306b3e
commit 9304f87611
284 changed files with 26215 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
contrib/ChangeLog
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@ -1,3 +1,7 @@
2013-10-31 Chung-Ju Wu <jasonwucj@gmail.com>
* config-list.mk (nds32le-elf, nds32be-elf): Add nds32 target.
2013-10-29 Tobias Burnus <burnus@net-b.de>
* gcc_update (files_and_dependencies): Add rules for

1
contrib/config-list.mk
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@ -47,6 +47,7 @@ LIST = aarch64-elf aarch64-linux-gnu \
mips-wrs-vxworks mipstx39-elf mmix-knuth-mmixware mn10300-elf moxie-elf \
moxie-uclinux moxie-rtems pdp11-aout picochip-elfOPT-enable-obsolete \
msp430-elf \
nds32le-elf nds32be-elf \
powerpc-darwin8 \
powerpc-darwin7 powerpc64-darwin powerpc-freebsd6 powerpc-netbsd \
powerpc-eabispe powerpc-eabisimaltivec powerpc-eabisim ppc-elf \

31
gcc/ChangeLog
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@ -1,3 +1,34 @@
2013-10-31 Chung-Ju Wu <jasonwucj@gmail.com>
Shiva Chen <shiva0217@gmail.com>
* config.gcc (nds32*-*-*): Add nds32 target.
* config/nds32/nds32.c: New file.
* config/nds32/nds32.h: New file.
* config/nds32/nds32.md: New file.
* config/nds32/constants.md: New file.
* config/nds32/constraints.md: New file.
* config/nds32/iterators.md: New file.
* config/nds32/nds32-doubleword.md: New file.
* config/nds32/nds32-intrinsic.md: New file.
* config/nds32/nds32_intrinsic.h: New file.
* config/nds32/nds32-modes.def: New file.
* config/nds32/nds32-multiple.md: New file.
* config/nds32/nds32.opt: New file.
* config/nds32/nds32-opts.h: New file.
* config/nds32/nds32-protos.h: New file.
* config/nds32/nds32-peephole2.md: New file.
* config/nds32/pipelines.md: New file.
* config/nds32/predicates.md: New file.
* config/nds32/t-mlibs: New file.
* common/config/nds32: New directory and files.
* doc/invoke.texi (NDS32 options): Document nds32 specific options.
* doc/md.texi (NDS32 family): Document nds32 specific constraints.
* doc/install.texi (Cross-Compiler-Specific Options): Document
--with-nds32-lib for nds32 target.
* doc/extend.texi (Function Attributes, Target Builtins): Document
nds32 specific attributes.
2013-10-31 Vladimir Makarov <vmakarov@redhat.com>
* lra-constraints (process_alt_operands): Use the result

117
gcc/common/config/nds32/nds32-common.c Normal file
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@ -0,0 +1,117 @@
/* Common hooks of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "diagnostic-core.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
/* ------------------------------------------------------------------------ */
/* Implement TARGET_HANDLE_OPTION. */
static bool
nds32_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
const struct cl_decoded_option *decoded,
location_t loc)
{
size_t code = decoded->opt_index;
int value = decoded->value;
switch (code)
{
case OPT_misr_vector_size_:
/* Check the valid vector size: 4 or 16. */
if (value != 4 && value != 16)
{
error_at (loc, "for the option -misr-vector-size=X, the valid X "
"must be: 4 or 16");
return false;
}
return true;
case OPT_mcache_block_size_:
/* Check valid value: 4 8 16 32 64 128 256 512. */
if (exact_log2 (value) < 2 || exact_log2 (value) > 9)
{
error_at (loc, "for the option -mcache-block-size=X, the valid X "
"must be: 4, 8, 16, 32, 64, 128, 256, or 512");
return false;
}
return true;
default:
return true;
}
}
/* ------------------------------------------------------------------------ */
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
static const struct default_options nds32_option_optimization_table[] =
{
/* Enable -fomit-frame-pointer by default at -O1 or higher. */
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
/* Enable -mv3push by default at -Os, but it is useless under V2 ISA. */
{ OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
/* ------------------------------------------------------------------------ */
/* Run-time Target Specification. */
/* Default enable
TARGET_GP_DIRECT: Generate gp-imply instruction.
TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
TARGET_PERF_EXT : Generate performance extention instrcution.
TARGET_CMOV : Generate conditional move instruction. */
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS \
(MASK_GP_DIRECT \
| MASK_16_BIT \
| MASK_PERF_EXT \
| MASK_CMOV)
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION nds32_handle_option
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE nds32_option_optimization_table
/* Defining the Output Assembler Language. */
#undef TARGET_EXCEPT_UNWIND_INFO
#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
/* ------------------------------------------------------------------------ */
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
/* ------------------------------------------------------------------------ */

49
gcc/config.gcc
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@ -421,6 +421,10 @@ mips*-*-*)
extra_headers="loongson.h"
extra_options="${extra_options} g.opt mips/mips-tables.opt"
;;
nds32*)
cpu_type=nds32
extra_headers="nds32_intrinsic.h"
;;
picochip-*-*)
cpu_type=picochip
;;
@ -2091,6 +2095,18 @@ msp430*-*-*)
target_has_targetm_common=no
tmake_file="${tmake_file} msp430/t-msp430"
;;
nds32le-*-*)
target_cpu_default="0"
tm_defines="${tm_defines}"
tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
tmake_file="nds32/t-mlibs"
;;
nds32be-*-*)
target_cpu_default="0|MASK_BIG_ENDIAN"
tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
tmake_file="nds32/t-mlibs"
;;
pdp11-*-*)
tm_file="${tm_file} newlib-stdint.h"
use_gcc_stdint=wrap
@ -3754,6 +3770,39 @@ case "${target}" in
esac
;;
nds32*-*-*)
supported_defaults="arch nds32_lib"
# process --with-arch
case "${with_arch}" in
"" | v2 | v3 | v3m)
# OK
;;
*)
echo "Cannot accept --with-arch=$with_arch, available values are: v2 v3 v3m" 1>&2
exit 1
;;
esac
# process --with-nds32-lib
case "${with_nds32_lib}" in
"")
# the default library is newlib
with_nds32_lib=newlib
;;
newlib)
# OK
;;
mculib)
# OK
;;
*)
echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2
exit 1
;;
esac
;;
powerpc*-*-* | rs6000-*-*)
supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64"

46
gcc/config/nds32/constants.md Normal file
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@ -0,0 +1,46 @@
;; Constant defintions of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Register numbers.
(define_constants
[(R8_REGNUM 8)
(TA_REGNUM 15)
(FP_REGNUM 28)
(GP_REGNUM 29)
(LP_REGNUM 30)
(SP_REGNUM 31)
])
;; The unspec_volatile operation index.
(define_c_enum "unspec_volatile_element" [
UNSPEC_VOLATILE_FUNC_RETURN
UNSPEC_VOLATILE_ISYNC
UNSPEC_VOLATILE_ISB
UNSPEC_VOLATILE_MFSR
UNSPEC_VOLATILE_MFUSR
UNSPEC_VOLATILE_MTSR
UNSPEC_VOLATILE_MTUSR
UNSPEC_VOLATILE_SETGIE_EN
UNSPEC_VOLATILE_SETGIE_DIS
])
;; ------------------------------------------------------------------------

254
gcc/config/nds32/constraints.md Normal file
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@ -0,0 +1,254 @@
;; Constraint definitions of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Check 16.8.7 Defining Machine-Specific Constraints for detail.
;; NO contrains can be prefixed with: E F V X g i m n o p r s
;; Machine-dependent integer: I J K L M N O P
;; Machine-dependent floating: G H
(define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
"LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")
(define_register_constraint "l" "LOW_REGS"
"LOW register class $r0 ~ $r7")
(define_register_constraint "d" "MIDDLE_REGS"
"MIDDLE register class $r0 ~ $r11, $r16 ~ $r19")
(define_register_constraint "h" "HIGH_REGS"
"HIGH register class $r12 ~ $r14, $r20 ~ $r31")
(define_register_constraint "t" "R15_TA_REG"
"Temporary Assist register $ta (i.e. $r15)")
(define_register_constraint "k" "STACK_REG"
"Stack register $sp")
(define_constraint "Iu03"
"Unsigned immediate 3-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 3) && ival >= 0")))
(define_constraint "In03"
"Negative immediate 3-bit value in the range of -7 to 0"
(and (match_code "const_int")
(match_test "IN_RANGE (ival, -7, 0)")))
(define_constraint "Iu04"
"Unsigned immediate 4-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 4) && ival >= 0")))
(define_constraint "Is05"
"Signed immediate 5-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
(define_constraint "Iu05"
"Unsigned immediate 5-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 5) && ival >= 0")))
(define_constraint "In05"
"Negative immediate 5-bit value in the range of -31 to 0"
(and (match_code "const_int")
(match_test "IN_RANGE (ival, -31, 0)")))
;; Ip05 is special and dedicated for v3 movpi45 instruction.
;; movpi45 has imm5u field but the range is 16 ~ 47.
(define_constraint "Ip05"
"Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
(and (match_code "const_int")
(match_test "ival < ((1 << 5) + 16)
&& ival >= (0 + 16)
&& (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
(define_constraint "Iu06"
"Unsigned immediate 6-bit value constraint for addri36.sp instruction"
(and (match_code "const_int")
(match_test "ival < (1 << 6)
&& ival >= 0
&& (ival % 4 == 0)
&& (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
(define_constraint "Iu08"
"Unsigned immediate 8-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 8) && ival >= 0")))
(define_constraint "Iu09"
"Unsigned immediate 9-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 9) && ival >= 0")))
(define_constraint "Is10"
"Signed immediate 10-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 9) && ival >= -(1 << 9)")))
(define_constraint "Is11"
"Signed immediate 11-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
(define_constraint "Is15"
"Signed immediate 15-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 14) && ival >= -(1 << 14)")))
(define_constraint "Iu15"
"Unsigned immediate 15-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 15) && ival >= 0")))
;; Ic15 is special and dedicated for performance extension
;; 'bclr' (single-bit-clear) instruction.
;; It is used in andsi3 pattern and recognized for the immediate
;; which is NOT in the range of imm15u but OK for 'bclr' instruction.
;; (If the immediate value IS in the range of imm15u,
;; we can directly use 'andi' instruction.)
(define_constraint "Ic15"
"A constant which is not in the range of imm15u but ok for bclr instruction"
(and (match_code "const_int")
(match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)")))
;; Ie15 is special and dedicated for performance extension
;; 'bset' (single-bit-set) instruction.
;; It is used in iorsi3 pattern and recognized for the immediate
;; which is NOT in the range of imm15u but OK for 'bset' instruction.
;; (If the immediate value IS in the range of imm15u,
;; we can directly use 'ori' instruction.)
(define_constraint "Ie15"
"A constant which is not in the range of imm15u but ok for bset instruction"
(and (match_code "const_int")
(match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)")))
;; It15 is special and dedicated for performance extension
;; 'btgl' (single-bit-toggle) instruction.
;; It is used in xorsi3 pattern and recognized for the immediate
;; which is NOT in the range of imm15u but OK for 'btgl' instruction.
;; (If the immediate value IS in the range of imm15u,
;; we can directly use 'xori' instruction.)
(define_constraint "It15"
"A constant which is not in the range of imm15u but ok for btgl instruction"
(and (match_code "const_int")
(match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)")))
;; Ii15 is special and dedicated for v3 isa
;; 'bitci' (bit-clear-immediate) instruction.
;; It is used in andsi3 pattern and recognized for the immediate whose
;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction.
;; For example, 'andi $r0,$r0,0xfffffffc' can be presented
; with 'bitci $r0,$r0,3'.
(define_constraint "Ii15"
"A constant whose compliment value is in the range of imm15u
and ok for bitci instruction"
(and (match_code "const_int")
(match_test "nds32_can_use_bitci_p (ival)")))
(define_constraint "Is16"
"Signed immediate 16-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 15) && ival >= -(1 << 15)")))
(define_constraint "Is17"
"Signed immediate 17-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 16) && ival >= -(1 << 16)")))
(define_constraint "Is19"
"Signed immediate 19-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 18) && ival >= -(1 << 18)")))
(define_constraint "Is20"
"Signed immediate 20-bit value"
(and (match_code "const_int")
(match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
(define_constraint "Ihig"
"The immediate value that can be simply set high 20-bit"
(and (match_code "const_int")
(match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
(define_constraint "Izeb"
"The immediate value 0xff"
(and (match_code "const_int")
(match_test "(ival == 0xff)")))
(define_constraint "Izeh"
"The immediate value 0xffff"
(and (match_code "const_int")
(match_test "(ival == 0xffff)")))
(define_constraint "Ixls"
"The immediate value 0x01"
(and (match_code "const_int")
(match_test "TARGET_PERF_EXT && (ival == 0x1)")))
(define_constraint "Ix11"
"The immediate value 0x7ff"
(and (match_code "const_int")
(match_test "TARGET_PERF_EXT && (ival == 0x7ff)")))
(define_constraint "Ibms"
"The immediate value with power of 2"
(and (match_code "const_int")
(match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
&& (IN_RANGE (exact_log2 (ival), 0, 7))")))
(define_constraint "Ifex"
"The immediate value with power of 2 minus 1"
(and (match_code "const_int")
(match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
&& (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
(define_memory_constraint "U33"
"Memory constraint for 333 format"
(and (match_code "mem")
(match_test "nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
(define_memory_constraint "U45"
"Memory constraint for 45 format"
(and (match_code "mem")
(match_test "(nds32_mem_format (op) == ADDRESS_REG)
&& (GET_MODE (op) == SImode)")))
(define_memory_constraint "U37"
"Memory constraint for 37 format"
(and (match_code "mem")
(match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
|| nds32_mem_format (op) == ADDRESS_FP_IMM7U)
&& (GET_MODE (op) == SImode)")))
;; ------------------------------------------------------------------------

55
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@ -0,0 +1,55 @@
;; Code and mode itertator and attribute definitions
;; of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;----------------------------------------------------------------------------
;; Mode iterators.
;;----------------------------------------------------------------------------
;; A list of integer modes that are up to one word long.
(define_mode_iterator QIHISI [QI HI SI])
;; A list of integer modes that are up to one half-word long.
(define_mode_iterator QIHI [QI HI])
;; A list of the modes that are up to double-word long.
(define_mode_iterator DIDF [DI DF])
;;----------------------------------------------------------------------------
;; Mode attributes.
;;----------------------------------------------------------------------------
(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
(define_mode_attr byte [(QI "1") (HI "2") (SI "4")])
;;----------------------------------------------------------------------------
;; Code iterators.
;;----------------------------------------------------------------------------
;;----------------------------------------------------------------------------
;; Code attributes.
;;----------------------------------------------------------------------------
;;----------------------------------------------------------------------------

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@ -0,0 +1,251 @@
;; DImode/DFmode patterns description of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; -------------------------------------------------------------
;; Move DImode/DFmode instructions.
;; -------------------------------------------------------------
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
{
/* Need to force register if mem <- !reg. */
if (MEM_P (operands[0]) && !REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
})
(define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" ""))]
""
{
/* Need to force register if mem <- !reg. */
if (MEM_P (operands[0]) && !REG_P (operands[1]))
operands[1] = force_reg (DFmode, operands[1]);
})
(define_insn "move_<mode>"
[(set (match_operand:DIDF 0 "nonimmediate_operand" "=r, r, r, m")
(match_operand:DIDF 1 "general_operand" " r, i, m, r"))]
""
{
rtx addr;
rtx otherops[5];
switch (which_alternative)
{
case 0:
return "movd44\t%0, %1";
case 1:
/* reg <- const_int, we ask gcc to split instruction. */
return "#";
case 2:
/* Refer to nds32_legitimate_address_p() in nds32.c,
we only allow "reg", "symbol_ref", "const", and "reg + const_int"
as address rtx for DImode/DFmode memory access. */
addr = XEXP (operands[1], 0);
otherops[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
otherops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
otherops[2] = addr;
if (REG_P (addr))
{
/* (reg) <- (mem (reg)) */
output_asm_insn ("lmw.bi\t%0, [%2], %1, 0", otherops);
}
else if (GET_CODE (addr) == PLUS)
{
/* (reg) <- (mem (plus (reg) (const_int))) */
rtx op0 = XEXP (addr, 0);
rtx op1 = XEXP (addr, 1);
if (REG_P (op0))
{
otherops[2] = op0;
otherops[3] = op1;
otherops[4] = gen_int_mode (INTVAL (op1) + 4, SImode);
}
else
{
otherops[2] = op1;
otherops[3] = op0;
otherops[4] = gen_int_mode (INTVAL (op0) + 4, SImode);
}
/* To avoid base overwrite when REGNO(%0) == REGNO(%2). */
if (REGNO (otherops[0]) != REGNO (otherops[2]))
{
output_asm_insn ("lwi\t%0, [%2 + (%3)]", otherops);
output_asm_insn ("lwi\t%1, [%2 + (%4)]", otherops);
}
else
{
output_asm_insn ("lwi\t%1, [%2 + (%4)]", otherops);
output_asm_insn ("lwi\t%0,[ %2 + (%3)]", otherops);
}
}
else
{
/* (reg) <- (mem (symbol_ref ...))
(reg) <- (mem (const ...)) */
output_asm_insn ("lwi.gp\t%0, [ + %2]", otherops);
output_asm_insn ("lwi.gp\t%1, [ + %2 + 4]", otherops);
}
/* We have already used output_asm_insn() by ourself,
so return an empty string. */
return "";
case 3:
/* Refer to nds32_legitimate_address_p() in nds32.c,
we only allow "reg", "symbol_ref", "const", and "reg + const_int"
as address rtx for DImode/DFmode memory access. */
addr = XEXP (operands[0], 0);
otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1]));
otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
otherops[2] = addr;
if (REG_P (addr))
{
/* (mem (reg)) <- (reg) */
output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops);
}
else if (GET_CODE (addr) == PLUS)
{
/* (mem (plus (reg) (const_int))) <- (reg) */
rtx op0 = XEXP (addr, 0);
rtx op1 = XEXP (addr, 1);
if (REG_P (op0))
{
otherops[2] = op0;
otherops[3] = op1;
otherops[4] = gen_int_mode (INTVAL (op1) + 4, SImode);
}
else
{
otherops[2] = op1;
otherops[3] = op0;
otherops[4] = gen_int_mode (INTVAL (op0) + 4, SImode);
}
/* To avoid base overwrite when REGNO(%0) == REGNO(%2). */
if (REGNO (otherops[0]) != REGNO (otherops[2]))
{
output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
}
else
{
output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
}
}
else
{
/* (mem (symbol_ref ...)) <- (reg)
(mem (const ...)) <- (reg) */
output_asm_insn ("swi.gp\t%0, [ + %2]", otherops);
output_asm_insn ("swi.gp\t%1, [ + %2 + 4]", otherops);
}
/* We have already used output_asm_insn() by ourself,
so return an empty string. */
return "";
default:
gcc_unreachable ();
}
}
[(set_attr "type" "move,move,move,move")
(set_attr "length" " 4, 16, 8, 8")])
(define_split
[(set (match_operand:DIDF 0 "register_operand" "")
(match_operand:DIDF 1 "const_double_operand" ""))]
"reload_completed"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))]
{
/* Construct lowpart rtx. */
operands[2] = gen_lowpart (SImode, operands[0]);
operands[3] = gen_lowpart (SImode, operands[1]);
/* Construct highpart rtx. */
/* Note that operands[1] can be VOIDmode constant,
so we need to use gen_highpart_mode().
Refer to gcc/emit-rtl.c for more information. */
operands[4] = gen_highpart (SImode, operands[0]);
operands[5] = gen_highpart_mode (SImode,
GET_MODE (operands[0]), operands[1]);
/* Actually we would like to create move behavior by ourself.
So that movsi expander could have chance to split large constant. */
emit_move_insn (operands[2], operands[3]);
emit_move_insn (operands[4], operands[5]);
DONE;
})
;; There is 'movd44' instruction for DImode/DFmode movement under V3/V3M ISA.
;; We only need to split it under V2 ISA or none-16-bit code generation.
(define_split
[(set (match_operand:DIDF 0 "register_operand" "")
(match_operand:DIDF 1 "register_operand" ""))]
"reload_completed
&& (TARGET_ISA_V2 || !TARGET_16_BIT)"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))]
{
operands[2] = gen_highpart (SImode, operands[0]);
operands[3] = gen_highpart (SImode, operands[1]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
/* Handle a partial overlap. */
if (rtx_equal_p (operands[0], operands[3]))
{
rtx tmp0 = operands[0];
rtx tmp1 = operands[1];
operands[0] = operands[2];
operands[1] = operands[3];
operands[2] = tmp0;
operands[3] = tmp1;
}
})
;; -------------------------------------------------------------
;; Boolean DImode instructions.
;; -------------------------------------------------------------
;; Nowadays, the generic code is supposed to split the DImode
;; boolean operations and have good code generation.
;; Unless we find out some bad cases, there is no need to
;; define DImode boolean operations by ourself.
;; -------------------------------------------------------------

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;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; ------------------------------------------------------------------------
;; Register Transfer.
(define_insn "unspec_volatile_mfsr"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFSR))]
""
"mfsr\t%0, %V1"
[(set_attr "type" "misc")
(set_attr "length" "4")]
)
(define_insn "unspec_volatile_mfusr"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFUSR))]
""
"mfusr\t%0, %V1"
[(set_attr "type" "misc")
(set_attr "length" "4")]
)
(define_insn "unspec_volatile_mtsr"
[(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTSR)]
""
"mtsr\t%0, %V1"
[(set_attr "type" "misc")
(set_attr "length" "4")]
)
(define_insn "unspec_volatile_mtusr"
[(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTUSR)]
""
"mtusr\t%0, %V1"
[(set_attr "type" "misc")
(set_attr "length" "4")]
)
;; ------------------------------------------------------------------------
;; Interrupt Instructions.
(define_insn "unspec_volatile_setgie_en"
[(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_EN)]
""
"setgie.e"
[(set_attr "type" "misc")]
)
(define_insn "unspec_volatile_setgie_dis"
[(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_DIS)]
""
"setgie.d"
[(set_attr "type" "misc")]
)
;; ------------------------------------------------------------------------
;; Cache Synchronization Instructions
(define_insn "unspec_volatile_isync"
[(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_ISYNC)]
""
"isync\t%0"
[(set_attr "type" "misc")]
)
(define_insn "unspec_volatile_isb"
[(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_ISB)]
""
"isb"
[(set_attr "type" "misc")]
)
;; ------------------------------------------------------------------------

21
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/* Extra machine modes of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* So far, there is no need to define any modes for nds32 target. */

410
gcc/config/nds32/nds32-multiple.md Normal file
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;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.for NDS32.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Load Multiple Insns.
;;
;; operands[0] is the first of the consecutive registers.
;; operands[1] is the first memory location.
;; operands[2] is the number of consecutive registers.
(define_expand "load_multiple"
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))])]
""
{
int maximum;
/* Because reduced-set regsiters has few registers
(r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
be used for register allocation),
using 8 registers for load_multiple may easily consume all of them.
It makes register allocation/spilling hard to work.
So we only allow maximum=4 registers for load_multiple
under reduced-set registers. */
if (TARGET_REDUCED_REGS)
maximum = 4;
else
maximum = 8;
/* Here are the conditions that must be all passed,
otherwise we have to FAIL this rtx generation:
1. The number of consecutive registers must be integer.
2. Maximum 4 or 8 registers for lmw.bi instruction
(based on this nds32-multiple.md design).
3. Minimum 2 registers for lmw.bi instruction
(based on this nds32-multiple.md design).
4. operands[0] must be register for sure.
5. operands[1] must be memory for sure.
6. Do not cross $r15 register because it is not allocatable. */
if (GET_CODE (operands[2]) != CONST_INT
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != REG
|| GET_CODE (operands[1]) != MEM
|| REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
FAIL;
/* For (mem addr), we force_reg on addr here,
so that nds32_expand_load_multiple can easily use it. */
operands[3] = nds32_expand_load_multiple (REGNO (operands[0]),
INTVAL (operands[2]),
force_reg (SImode,
XEXP (operands[1], 0)),
operands[1]);
})
;; Ordinary Load Multiple.
(define_insn "*lmwsi8"
[(match_parallel 0 "nds32_load_multiple_operation"
[(set (match_operand:SI 2 "register_operand" "")
(mem:SI (match_operand:SI 1 "register_operand" "r")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))
(set (match_operand:SI 5 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 12))))
(set (match_operand:SI 6 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 16))))
(set (match_operand:SI 7 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 20))))
(set (match_operand:SI 8 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 24))))
(set (match_operand:SI 9 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
"(XVECLEN (operands[0], 0) == 8)"
"lmw.bi\t%2, [%1], %9, 0x0"
[(set_attr "type" "load")
(set_attr "length" "4")]
)
(define_insn "*lmwsi7"
[(match_parallel 0 "nds32_load_multiple_operation"
[(set (match_operand:SI 2 "register_operand" "")
(mem:SI (match_operand:SI 1 "register_operand" "r")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))
(set (match_operand:SI 5 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 12))))
(set (match_operand:SI 6 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 16))))
(set (match_operand:SI 7 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 20))))
(set (match_operand:SI 8 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
"(XVECLEN (operands[0], 0) == 7)"
"lmw.bi\t%2, [%1], %8, 0x0"
[(set_attr "type" "load")
(set_attr "length" "4")]
)
(define_insn "*lmwsi6"
[(match_parallel 0 "nds32_load_multiple_operation"
[(set (match_operand:SI 2 "register_operand" "")
(mem:SI (match_operand:SI 1 "register_operand" "r")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))
(set (match_operand:SI 5 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 12))))
(set (match_operand:SI 6 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 16))))
(set (match_operand:SI 7 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
"(XVECLEN (operands[0], 0) == 6)"
"lmw.bi\t%2, [%1], %7, 0x0"
[(set_attr "type" "load")
(set_attr "length" "4")]
)
(define_insn "*lmwsi5"
[(match_parallel 0 "nds32_load_multiple_operation"
[(set (match_operand:SI 2 "register_operand" "")
(mem:SI (match_operand:SI 1 "register_operand" "r")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))
(set (match_operand:SI 5 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 12))))
(set (match_operand:SI 6 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
"(XVECLEN (operands[0], 0) == 5)"
"lmw.bi\t%2, [%1], %6, 0x0"
[(set_attr "type" "load")
(set_attr "length" "4")]
)
(define_insn "*lmwsi4"
[(match_parallel 0 "nds32_load_multiple_operation"
[(set (match_operand:SI 2 "register_operand" "")
(mem:SI (match_operand:SI 1 "register_operand" "r")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))
(set (match_operand:SI 5 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
"(XVECLEN (operands[0], 0) == 4)"
"lmw.bi\t%2, [%1], %5, 0x0"
[(set_attr "type" "load")
(set_attr "length" "4")]
)
(define_insn "*lmwsi3"
[(match_parallel 0 "nds32_load_multiple_operation"
[(set (match_operand:SI 2 "register_operand" "")
(mem:SI (match_operand:SI 1 "register_operand" "r")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
"(XVECLEN (operands[0], 0) == 3)"
"lmw.bi\t%2, [%1], %4, 0x0"
[(set_attr "type" "load")
(set_attr "length" "4")]
)
(define_insn "*lmwsi2"
[(match_parallel 0 "nds32_load_multiple_operation"
[(set (match_operand:SI 2 "register_operand" "")
(mem:SI (match_operand:SI 1 "register_operand" "r")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
"(XVECLEN (operands[0], 0) == 2)"
"lmw.bi\t%2, [%1], %3, 0x0"
[(set_attr "type" "load")
(set_attr "length" "4")]
)
;; Store Multiple Insns.
;;
;; operands[0] is the first memory location.
;; opernads[1] is the first of the consecutive registers.
;; operands[2] is the number of consecutive registers.
(define_expand "store_multiple"
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))])]
""
{
int maximum;
/* Because reduced-set regsiters has few registers
(r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
be used for register allocation),
using 8 registers for store_multiple may easily consume all of them.
It makes register allocation/spilling hard to work.
So we only allow maximum=4 registers for store_multiple
under reduced-set registers. */
if (TARGET_REDUCED_REGS)
maximum = 4;
else
maximum = 8;
/* Here are the conditions that must be all passed,
otherwise we have to FAIL this rtx generation:
1. The number of consecutive registers must be integer.
2. Maximum 4 or 8 registers for smw.bi instruction
(based on this nds32-multiple.md design).
3. Minimum 2 registers for smw.bi instruction
(based on this nds32-multiple.md design).
4. operands[0] must be memory for sure.
5. operands[1] must be register for sure.
6. Do not cross $r15 register because it is not allocatable. */
if (GET_CODE (operands[2]) != CONST_INT
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != MEM
|| GET_CODE (operands[1]) != REG
|| REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
FAIL;
/* For (mem addr), we force_reg on addr here,
so that nds32_expand_store_multiple can easily use it. */
operands[3] = nds32_expand_store_multiple (REGNO (operands[1]),
INTVAL (operands[2]),
force_reg (SImode,
XEXP (operands[0], 0)),
operands[0]);
})
;; Ordinary Store Multiple.
(define_insn "*stmsi8"
[(match_parallel 0 "nds32_store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 3 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 4 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
(match_operand:SI 5 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
(match_operand:SI 6 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
(match_operand:SI 7 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
(match_operand:SI 8 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
(match_operand:SI 9 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 8)"
"smw.bi\t%2, [%1], %9, 0x0"
[(set_attr "type" "store")
(set_attr "length" "4")]
)
(define_insn "*stmsi7"
[(match_parallel 0 "nds32_store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 3 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 4 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
(match_operand:SI 5 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
(match_operand:SI 6 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
(match_operand:SI 7 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
(match_operand:SI 8 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 7)"
"smw.bi\t%2, [%1], %8, 0x0"
[(set_attr "type" "store")
(set_attr "length" "4")]
)
(define_insn "*stmsi6"
[(match_parallel 0 "nds32_store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 3 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 4 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
(match_operand:SI 5 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
(match_operand:SI 6 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
(match_operand:SI 7 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 6)"
"smw.bi\t%2, [%1], %7, 0x0"
[(set_attr "type" "store")
(set_attr "length" "4")]
)
(define_insn "*stmsi5"
[(match_parallel 0 "nds32_store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 3 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 4 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
(match_operand:SI 5 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
(match_operand:SI 6 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 5)"
"smw.bi\t%2, [%1], %6, 0x0"
[(set_attr "type" "store")
(set_attr "length" "4")]
)
(define_insn "*stmsi4"
[(match_parallel 0 "nds32_store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 3 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 4 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
(match_operand:SI 5 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 4)"
"smw.bi\t%2, [%1], %5, 0x0"
[(set_attr "type" "store")
(set_attr "length" "4")]
)
(define_insn "*stmsi3"
[(match_parallel 0 "nds32_store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 3 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 4 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 3)"
"smw.bi\t%2, [%1], %4, 0x0"
[(set_attr "type" "store")
(set_attr "length" "4")]
)
(define_insn "*stmsi2"
[(match_parallel 0 "nds32_store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 3 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 2)"
"smw.bi\t%2, [%1], %3, 0x0"
[(set_attr "type" "store")
(set_attr "length" "4")]
)
;; Move a block of memory if it is word aligned and MORE than 2 words long.
;; We could let this apply for blocks of less than this, but it clobbers so
;; many registers that there is then probably a better way.
;;
;; operands[0] is the destination block of memory.
;; operands[1] is the source block of memory.
;; operands[2] is the number of bytes to move.
;; operands[3] is the known shared alignment.
(define_expand "movmemqi"
[(match_operand:BLK 0 "general_operand" "")
(match_operand:BLK 1 "general_operand" "")
(match_operand:SI 2 "const_int_operand" "")
(match_operand:SI 3 "const_int_operand" "")]
""
{
if (nds32_expand_movmemqi (operands[0],
operands[1],
operands[2],
operands[3]))
DONE;
FAIL;
})
;; ------------------------------------------------------------------------

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/* Definitions for option handling of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef NDS32_OPTS_H
#define NDS32_OPTS_H
#define NDS32_DEFAULT_CACHE_BLOCK_SIZE 16
#define NDS32_DEFAULT_ISR_VECTOR_SIZE (TARGET_ISA_V3 ? 4 : 16)
/* The various ANDES ISA. */
enum nds32_arch_type
{
ARCH_V2,
ARCH_V3,
ARCH_V3M
};
#endif

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;; define_peephole2 optimization patterns of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Use define_peephole and define_peephole2 to handle possible
;; target-specific optimization in this file.
;; ------------------------------------------------------------------------

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/* Prototypes for exported functions of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* ------------------------------------------------------------------------ */
/* Defining Data Structures for Per-function Information. */
extern void nds32_init_expanders (void);
/* Register Usage. */
/* -- How Values Fit in Registers. */
extern int nds32_hard_regno_nregs (int, enum machine_mode);
extern int nds32_hard_regno_mode_ok (int, enum machine_mode);
/* Register Classes. */
extern enum reg_class nds32_regno_reg_class (int);
/* Stack Layout and Calling Conventions. */
/* -- Basic Stack Layout. */
extern rtx nds32_return_addr_rtx (int, rtx);
/* -- Eliminating Frame Pointer and Arg Pointer. */
extern HOST_WIDE_INT nds32_initial_elimination_offset (unsigned int,
unsigned int);
/* -- Passing Arguments in Registers. */
extern void nds32_init_cumulative_args (CUMULATIVE_ARGS *,
tree, rtx, tree, int);
/* -- Function Entry and Exit. */
extern void nds32_expand_prologue (void);
extern void nds32_expand_epilogue (void);
extern void nds32_expand_prologue_v3push (void);
extern void nds32_expand_epilogue_v3pop (void);
/* ------------------------------------------------------------------------ */
/* Auxiliary functions for auxiliary macros in nds32.h. */
extern bool nds32_ls_333_p (rtx, rtx, rtx, enum machine_mode);
/* Auxiliary functions for expanding rtl used in nds32-multiple.md. */
extern rtx nds32_expand_load_multiple (int, int, rtx, rtx);
extern rtx nds32_expand_store_multiple (int, int, rtx, rtx);
extern int nds32_expand_movmemqi (rtx, rtx, rtx, rtx);
/* Auxiliary functions for multiple load/store predicate checking. */
extern bool nds32_valid_multiple_load_store (rtx, bool);
/* Auxiliary functions for stack operation predicate checking. */
extern bool nds32_valid_stack_push_pop (rtx, bool);
/* Auxiliary functions for bit operation detection. */
extern int nds32_can_use_bclr_p (int);
extern int nds32_can_use_bset_p (int);
extern int nds32_can_use_btgl_p (int);
extern int nds32_can_use_bitci_p (int);
/* Auxiliary function for 'Computing the Length of an Insn'. */
extern int nds32_adjust_insn_length (rtx, int);
/* Auxiliary functions for FP_AS_GP detection. */
extern bool nds32_symbol_load_store_p (rtx);
extern int nds32_fp_as_gp_check_available (void);
/* Auxiliary functions for jump table generation. */
extern const char *nds32_output_casesi_pc_relative (rtx *);
extern const char *nds32_output_casesi (rtx *);
/* Auxiliary functions to identify 16 bit addresing mode. */
extern enum nds32_16bit_address_type nds32_mem_format (rtx);
/* Auxiliary functions to output assembly code. */
extern const char *nds32_output_16bit_store (rtx *, int);
extern const char *nds32_output_16bit_load (rtx *, int);
extern const char *nds32_output_32bit_store (rtx *, int);
extern const char *nds32_output_32bit_load (rtx *, int);
extern const char *nds32_output_32bit_load_s (rtx *, int);
/* Auxiliary functions to output stack push/pop instruction. */
extern const char *nds32_output_stack_push (void);
extern const char *nds32_output_stack_pop (void);
/* Auxiliary functions to decide output alignment or not. */
extern int nds32_target_alignment (rtx);
/* ------------------------------------------------------------------------ */

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/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* ------------------------------------------------------------------------ */
/* The following are auxiliary macros or structure declarations
that are used all over the nds32.c and nds32.h. */
/* Computing the Length of an Insn. */
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
(LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
/* Check instruction LS-37-FP-implied form.
Note: actually its immediate range is imm9u
since it is used for lwi37/swi37 instructions. */
#define NDS32_LS_37_FP_P(rt, ra, imm) \
(REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
&& REGNO (ra) == FP_REGNUM \
&& satisfies_constraint_Iu09 (imm))
/* Check instruction LS-37-SP-implied form.
Note: actually its immediate range is imm9u
since it is used for lwi37/swi37 instructions. */
#define NDS32_LS_37_SP_P(rt, ra, imm) \
(REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
&& REGNO (ra) == SP_REGNUM \
&& satisfies_constraint_Iu09 (imm))
/* Check load/store instruction form : Rt3, Ra3, imm3u. */
#define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
/* Check load/store instruction form : Rt4, Ra5, const_int_0.
Note: no need to check ra because Ra5 means it covers all registers. */
#define NDS32_LS_450_P(rt, ra, imm) \
((imm == const0_rtx) \
&& (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
|| REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
/* Check instruction RRI-333-form. */
#define NDS32_RRI_333_P(rt, ra, imm) \
(REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
&& REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
&& satisfies_constraint_Iu03 (imm))
/* Check instruction RI-45-form. */
#define NDS32_RI_45_P(rt, ra, imm) \
(REGNO (rt) == REGNO (ra) \
&& (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
|| REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
&& satisfies_constraint_Iu05 (imm))
/* Check instruction RR-33-form. */
#define NDS32_RR_33_P(rt, ra) \
(REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
&& REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
/* Check instruction RRR-333-form. */
#define NDS32_RRR_333_P(rt, ra, rb) \
(REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
&& REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
&& REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
/* Check instruction RR-45-form.
Note: no need to check rb because Rb5 means it covers all registers. */
#define NDS32_RR_45_P(rt, ra, rb) \
(REGNO (rt) == REGNO (ra) \
&& (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
|| REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
/* Classifies address type to distinguish 16-bit/32-bit format. */
enum nds32_16bit_address_type
{
/* [reg]: 45 format address. */
ADDRESS_REG,
/* [lo_reg + imm3u]: 333 format address. */
ADDRESS_LO_REG_IMM3U,
/* post_inc [lo_reg + imm3u]: 333 format address. */
ADDRESS_POST_INC_LO_REG_IMM3U,
/* [$fp + imm7u]: fp imply address. */
ADDRESS_FP_IMM7U,
/* [$sp + imm7u]: sp imply address. */
ADDRESS_SP_IMM7U,
/* Other address format. */
ADDRESS_NOT_16BIT_FORMAT
};
/* ------------------------------------------------------------------------ */
/* Define maximum numbers of registers for passing arguments. */
#define NDS32_MAX_REGS_FOR_ARGS 6
/* Define the register number for first argument. */
#define NDS32_GPR_ARG_FIRST_REGNUM 0
/* Define the register number for return value. */
#define NDS32_GPR_RET_FIRST_REGNUM 0
/* Define double word alignment bits. */
#define NDS32_DOUBLE_WORD_ALIGNMENT 64
/* Define alignment checking macros for convenience. */
#define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
#define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
#define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
/* Round X up to the nearest double word. */
#define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
/* This macro is used to calculate the numbers of registers for
containing 'size' bytes of the argument.
The size of a register is a word in nds32 target.
So we use UNITS_PER_WORD to do the calculation. */
#define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
((mode == BLKmode) \
? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
: ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* This macro is used to return the register number for passing argument.
We need to obey the following rules:
1. If it is required MORE THAN one register,
make sure the register number is a even value.
2. If it is required ONLY one register,
the register number can be odd or even value. */
#define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \
((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
: ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
/* This macro is to check if there are still available registers
for passing argument. */
#define NDS32_ARG_PASS_IN_REG_P(reg_offset, mode, type) \
(((reg_offset) < NDS32_MAX_REGS_FOR_ARGS) \
&& ((reg_offset) + NDS32_NEED_N_REGS_FOR_ARG (mode, type) \
<= NDS32_MAX_REGS_FOR_ARGS))
/* This macro is to check if the register is required to be saved on stack.
If call_used_regs[regno] == 0, regno is the callee-saved register.
If df_regs_ever_live_p(regno) == true, it is used in the current function.
As long as the register satisfies both criteria above,
it is required to be saved. */
#define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
/* ------------------------------------------------------------------------ */
/* A C structure for machine-specific, per-function data.
This is added to the cfun structure. */
struct GTY(()) machine_function
{
/* Number of bytes allocated on the stack for variadic args
if we want to push them into stack as pretend arguments by ourself. */
int va_args_size;
/* Number of bytes reserved on the stack for
local and temporary variables. */
int local_size;
/* Number of bytes allocated on the stack for outgoing arguments. */
int out_args_size;
/* Number of bytes on the stack for saving $fp. */
int fp_size;
/* Number of bytes on the stack for saving $gp. */
int gp_size;
/* Number of bytes on the stack for saving $lp. */
int lp_size;
/* Number of bytes on the stack for saving callee-saved registers. */
int callee_saved_regs_size;
/* The padding bytes in callee-saved area may be required. */
int callee_saved_area_padding_bytes;
/* The first required register that should be saved on stack
for va_args (one named argument + nameless arguments). */
int va_args_first_regno;
/* The last required register that should be saved on stack
for va_args (one named argument + nameless arguments). */
int va_args_last_regno;
/* The first required callee-saved register. */
int callee_saved_regs_first_regno;
/* The last required callee-saved register. */
int callee_saved_regs_last_regno;
/* Indicate that whether this function needs
prologue/epilogue code generation. */
int naked_p;
/* Indicate that whether this function
uses fp_as_gp optimization. */
int fp_as_gp_p;
};
/* A C structure that contains the arguments information. */
typedef struct
{
unsigned int reg_offset;
} nds32_cumulative_args;
/* ------------------------------------------------------------------------ */
/* The following we define C-ISR related stuff.
In nds32 architecture, we have 73 vectors for interrupt/exception.
For each vector (except for vector 0, which is used for reset behavior),
we allow users to set its register saving scheme and interrupt level. */
/* There are 73 vectors in nds32 architecture.
0 for reset handler,
1-8 for exception handler,
and 9-72 for interrupt handler.
We use an array, which is defined in nds32.c, to record
essential information for each vector. */
#define NDS32_N_ISR_VECTORS 73
/* Define possible isr category. */
enum nds32_isr_category
{
NDS32_ISR_NONE,
NDS32_ISR_INTERRUPT,
NDS32_ISR_EXCEPTION,
NDS32_ISR_RESET
};
/* Define isr register saving scheme. */
enum nds32_isr_save_reg
{
NDS32_SAVE_ALL,
NDS32_PARTIAL_SAVE
};
/* Define isr nested type. */
enum nds32_isr_nested_type
{
NDS32_NESTED,
NDS32_NOT_NESTED,
NDS32_NESTED_READY
};
/* Define structure to record isr information.
The isr vector array 'isr_vectors[]' with this structure
is defined in nds32.c. */
struct nds32_isr_info
{
/* The field to identify isr category.
It should be set to NDS32_ISR_NONE by default.
If user specifies a function as isr by using attribute,
this field will be set accordingly. */
enum nds32_isr_category category;
/* A string for the applied function name.
It should be set to empty string by default. */
char func_name[100];
/* The register saving scheme.
It should be set to NDS32_PARTIAL_SAVE by default
unless user specifies attribute to change it. */
enum nds32_isr_save_reg save_reg;
/* The nested type.
It should be set to NDS32_NOT_NESTED by default
unless user specifies attribute to change it. */
enum nds32_isr_nested_type nested_type;
/* Total vectors.
The total vectors = interrupt + exception numbers + reset.
It should be set to 0 by default.
This field is ONLY used in NDS32_ISR_RESET category. */
unsigned int total_n_vectors;
/* A string for nmi handler name.
It should be set to empty string by default.
This field is ONLY used in NDS32_ISR_RESET category. */
char nmi_name[100];
/* A string for warm handler name.
It should be set to empty string by default.
This field is ONLY used in NDS32_ISR_RESET category. */
char warm_name[100];
};
/* ------------------------------------------------------------------------ */
/* Define code for all nds32 builtins. */
enum nds32_builtins
{
NDS32_BUILTIN_ISYNC,
NDS32_BUILTIN_ISB,
NDS32_BUILTIN_MFSR,
NDS32_BUILTIN_MFUSR,
NDS32_BUILTIN_MTSR,
NDS32_BUILTIN_MTUSR,
NDS32_BUILTIN_SETGIE_EN,
NDS32_BUILTIN_SETGIE_DIS
};
/* ------------------------------------------------------------------------ */
#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
#define TARGET_ISA_V3 (nds32_arch_option == ARCH_V3)
#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
/* ------------------------------------------------------------------------ */
/* Controlling the Compilation Driver. */
#define OPTION_DEFAULT_SPECS \
{"arch", "%{!march=*:-march=%(VALUE)}" }
#define CC1_SPEC \
""
#define ASM_SPEC \
" %{mbig-endian:-EB} %{mlittle-endian:-EL}"
/* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
we need to pass '--relax' to linker.
Besides, for -mex9, we need to further pass '--mex9'. */
#define LINK_SPEC \
" %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
" %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
" %{mex9:--mex9}"
#define LIB_SPEC \
" -lc -lgloss"
/* The option -mno-ctor-dtor can disable constructor/destructor feature
by applying different crt stuff. In the convention, crt0.o is the
startup file without constructor/destructor;
crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
startup files with constructor/destructor.
Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
currently provided by GCC for nds32 target.
For nds32 target so far:
If -mno-ctor-dtor, we are going to link
"crt0.o [user objects]".
If general cases, we are going to link
"crt1.o crtbegin1.o [user objects] crtend1.o". */
#define STARTFILE_SPEC \
" %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
" %{!mno-ctor-dtor:crtbegin1.o%s}"
#define ENDFILE_SPEC \
" %{!mno-ctor-dtor:crtend1.o%s}"
/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we configure gcc
with --target=nds32be-* setting.
Check gcc/config.gcc for more information.
In addition, currently we only have elf toolchain,
where mgp-direct is always the default. */
#ifdef TARGET_BIG_ENDIAN_DEFAULT
#define MULTILIB_DEFAULTS { "mbig-endian", "mgp-direct" }
#else
#define MULTILIB_DEFAULTS { "mlittle-endian", "mgp-direct" }
#endif
/* Run-time Target Specification. */
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_define ("__nds32__"); \
\
if (TARGET_ISA_V2) \
builtin_define ("__NDS32_ISA_V2__"); \
if (TARGET_ISA_V3) \
builtin_define ("__NDS32_ISA_V3__"); \
if (TARGET_ISA_V3M) \
builtin_define ("__NDS32_ISA_V3M__"); \
\
if (TARGET_BIG_ENDIAN) \
builtin_define ("__big_endian__"); \
if (TARGET_REDUCED_REGS) \
builtin_define ("__NDS32_REDUCED_REGS__"); \
if (TARGET_CMOV) \
builtin_define ("__NDS32_CMOV__"); \
if (TARGET_PERF_EXT) \
builtin_define ("__NDS32_PERF_EXT__"); \
if (TARGET_16_BIT) \
builtin_define ("__NDS32_16_BIT__"); \
if (TARGET_GP_DIRECT) \
builtin_define ("__NDS32_GP_DIRECT__"); \
\
builtin_assert ("cpu=nds32"); \
builtin_assert ("machine=nds32"); \
} while (0)
/* Defining Data Structures for Per-function Information. */
/* This macro is called once per function,
before generation of any RTL has begun. */
#define INIT_EXPANDERS nds32_init_expanders ()
/* Storage Layout. */
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
#define UNITS_PER_WORD 4
#define PROMOTE_MODE(m, unsignedp, type) \
if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
{ \
(m) = SImode; \
}
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 64
#define FUNCTION_BOUNDARY 32
#define BIGGEST_ALIGNMENT 64
#define EMPTY_FIELD_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 8
#define STRICT_ALIGNMENT 1
#define PCC_BITFIELD_TYPE_MATTERS 1
/* Layout of Source Language Data Types. */
#define INT_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
#define DEFAULT_SIGNED_CHAR 1
#define SIZE_TYPE "long unsigned int"
#define PTRDIFF_TYPE "long int"
#define WCHAR_TYPE "short unsigned int"
#define WCHAR_TYPE_SIZE 16
/* Register Usage. */
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers. */
#define FIRST_PSEUDO_REGISTER 34
/* An initializer that says which registers are used for fixed
purposes all throughout the compiled code and are therefore
not available for general allocation.
$r28 : $fp
$r29 : $gp
$r30 : $lp
$r31 : $sp
caller-save registers: $r0 ~ $r5, $r16 ~ $r23
callee-save registers: $r6 ~ $r10, $r11 ~ $r14
reserved for assembler : $r15
reserved for other use : $r24, $r25, $r26, $r27 */
#define FIXED_REGISTERS \
{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* r8 r9 r10 r11 r12 r13 r14 r15 */ \
0, 0, 0, 0, 0, 0, 0, 1, \
/* r16 r17 r18 r19 r20 r21 r22 r23 */ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1, 1, 1, 1, 0, 1, 0, 1, \
/* ARG_POINTER:32 */ \
1, \
/* FRAME_POINTER:33 */ \
1 \
}
/* Identifies the registers that are not available for
general allocation of values that must live across
function calls -- so they are caller-save registers.
0 : callee-save registers
1 : caller-save registers */
#define CALL_USED_REGISTERS \
{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
1, 1, 1, 1, 1, 1, 0, 0, \
/* r8 r9 r10 r11 r12 r13 r14 r15 */ \
0, 0, 0, 0, 0, 0, 0, 1, \
/* r16 r17 r18 r19 r20 r21 r22 r23 */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1, 1, 1, 1, 0, 1, 0, 1, \
/* ARG_POINTER:32 */ \
1, \
/* FRAME_POINTER:33 */ \
1 \
}
/* In nds32 target, we have three levels of registers:
LOW_COST_REGS : $r0 ~ $r7
MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
#define REG_ALLOC_ORDER \
{ \
0, 1, 2, 3, 4, 5, 6, 7, \
8, 9, 10, 11, 16, 17, 18, 19, \
12, 13, 14, 15, 20, 21, 22, 23, \
24, 25, 26, 27, 28, 29, 30, 31, \
32, \
33 \
}
/* Tell IRA to use the order we define rather than messing it up with its
own cost calculations. */
#define HONOR_REG_ALLOC_ORDER
/* The number of consecutive hard regs needed starting at
reg "regno" for holding a value of mode "mode". */
#define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
/* Value is 1 if hard register "regno" can hold a value
of machine-mode "mode". */
#define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
/* A C expression that is nonzero if a value of mode1
is accessible in mode2 without copying.
Define this macro to return nonzero in as many cases as possible
since doing so will allow GCC to perform better register allocation.
We can use general registers to tie QI/HI/SI modes together. */
#define MODES_TIEABLE_P(mode1, mode2) \
(GET_MODE_CLASS (mode1) == MODE_INT \
&& GET_MODE_CLASS (mode2) == MODE_INT \
&& GET_MODE_SIZE (mode1) <= UNITS_PER_WORD \
&& GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
/* Register Classes. */
/* In nds32 target, we have three levels of registers:
Low cost regsiters : $r0 ~ $r7
Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
High cost registers : $r12 ~ $r14, $r20 ~ $r31
In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
so that it provides more chance to use low cost registers. */
enum reg_class
{
NO_REGS,
R15_TA_REG,
STACK_REG,
LOW_REGS,
MIDDLE_REGS,
HIGH_REGS,
GENERAL_REGS,
FRAME_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"R15_TA_REG", \
"STACK_REG", \
"LOW_REGS", \
"MIDDLE_REGS", \
"HIGH_REGS", \
"GENERAL_REGS", \
"FRAME_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{0x00000000, 0x00000000}, /* NO_REGS : */ \
{0x00008000, 0x00000000}, /* R15_TA_REG : 15 */ \
{0x80000000, 0x00000000}, /* STACK_REG : 31 */ \
{0x000000ff, 0x00000000}, /* LOW_REGS : 0-7 */ \
{0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19 */ \
{0xfff07000, 0x00000000}, /* HIGH_REGS : 12-14, 20-31 */ \
{0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31 */ \
{0x00000000, 0x00000003}, /* FRAME_REGS : 32, 33 */ \
{0xffffffff, 0x00000003} /* ALL_REGS : 0-31, 32, 33 */ \
}
#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
#define BASE_REG_CLASS GENERAL_REGS
#define INDEX_REG_CLASS GENERAL_REGS
/* Return nonzero if it is suitable for use as a
base register in operand addresses.
So far, we return nonzero only if "num" is a hard reg
of the suitable class or a pseudo register which is
allocated to a suitable hard reg. */
#define REGNO_OK_FOR_BASE_P(num) \
((num) < 32 || (unsigned) reg_renumber[num] < 32)
/* Return nonzero if it is suitable for use as a
index register in operand addresses.
So far, we return nonzero only if "num" is a hard reg
of the suitable class or a pseudo register which is
allocated to a suitable hard reg.
The difference between an index register and a base register is that
the index register may be scaled. */
#define REGNO_OK_FOR_INDEX_P(num) \
((num) < 32 || (unsigned) reg_renumber[num] < 32)
/* Obsolete Macros for Defining Constraints. */
/* Stack Layout and Calling Conventions. */
#define STACK_GROWS_DOWNWARD
#define FRAME_GROWS_DOWNWARD 1
#define STARTING_FRAME_OFFSET 0
#define STACK_POINTER_OFFSET 0
#define FIRST_PARM_OFFSET(fundecl) 0
#define RETURN_ADDR_RTX(count, frameaddr) \
nds32_return_addr_rtx (count, frameaddr)
/* A C expression whose value is RTL representing the location
of the incoming return address at the beginning of any function
before the prologue.
If this RTL is REG, you should also define
DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
#define STACK_POINTER_REGNUM SP_REGNUM
#define FRAME_POINTER_REGNUM 33
#define HARD_FRAME_POINTER_REGNUM FP_REGNUM
#define ARG_POINTER_REGNUM 32
#define STATIC_CHAIN_REGNUM 16
#define ELIMINABLE_REGS \
{ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
#define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
(offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
#define ACCUMULATE_OUTGOING_ARGS 1
#define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
#define CUMULATIVE_ARGS nds32_cumulative_args
#define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
/* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
We better cast REGNO into signed integer so that we can avoid
'comparison of unsigned expression >= 0 is always true' warning. */
#define FUNCTION_ARG_REGNO_P(regno) \
(((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0) \
&& ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_REGS_FOR_ARGS))
#define DEFAULT_PCC_STRUCT_RETURN 0
/* EXIT_IGNORE_STACK should be nonzero if, when returning
from a function, the stack pointer does not matter.
The value is tested only in functions that have frame pointers.
In nds32 target, the function epilogue recovers the
stack pointer from the frame. */
#define EXIT_IGNORE_STACK 1
#define FUNCTION_PROFILER(file, labelno) \
fprintf (file, "/* profiler %d */", (labelno))
/* Implementing the Varargs Macros. */
/* Trampolines for Nested Functions. */
/* Giving A-function and B-function,
if B-function wants to call A-function's nested function,
we need to fill trampoline code into A-function's stack
so that B-function can execute the code in stack to indirectly
jump to (like 'trampoline' action) desired nested function.
The trampoline code for nds32 target must contains following parts:
1. instructions (4 * 4 = 16 bytes):
get $pc first
load chain_value to static chain register via $pc
load nested function address to $r15 via $pc
jump to desired nested function via $r15
2. data (4 * 2 = 8 bytes):
chain_value
nested function address
Please check nds32.c implementation for more information. */
#define TRAMPOLINE_SIZE 24
/* Because all instructions/data in trampoline template are 4-byte size,
we set trampoline alignment 8*4=32 bits. */
#define TRAMPOLINE_ALIGNMENT 32
/* Implicit Calls to Library Routines. */
/* Addressing Modes. */
/* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
#define HAVE_POST_INCREMENT 1
/* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
#define HAVE_POST_DECREMENT 1
/* We have "LWI.bi Rt, [Ra], imm" instruction form. */
#define HAVE_POST_MODIFY_DISP 1
/* We have "LW.bi Rt, [Ra], Rb" instruction form. */
#define HAVE_POST_MODIFY_REG 1
#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
#define MAX_REGS_PER_ADDRESS 2
/* Anchored Addresses. */
/* Condition Code Status. */
/* Describing Relative Costs of Operations. */
/* A C expression for the cost of a branch instruction.
A value of 1 is the default;
other values are interpreted relative to that. */
#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
#define SLOW_BYTE_ACCESS 1
#define NO_FUNCTION_CSE
/* Adjusting the Instruction Scheduler. */
/* Dividing the Output into Sections (Texts, Data, . . . ). */
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
/* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
So we use '.section .bss' alternatively. */
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
/* Define this macro to be an expression with a nonzero value if jump tables
(for tablejump insns) should be output in the text section,
along with the assembler instructions.
Otherwise, the readonly data section is used. */
#define JUMP_TABLES_IN_TEXT_SECTION 1
/* Position Independent Code. */
/* Defining the Output Assembler Language. */
#define ASM_COMMENT_START "!"
#define ASM_APP_ON "! #APP"
#define ASM_APP_OFF "! #NO_APP\n"
#define ASM_OUTPUT_LABELREF(stream, name) \
asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
#define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
assemble_name (stream, XSTR (sym, 0))
#define ASM_OUTPUT_LABEL_REF(stream, buf) \
assemble_name (stream, buf)
#define LOCAL_LABEL_PREFIX "."
#define REGISTER_NAMES \
{ \
"$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
"$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
"$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
"$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
"$AP", \
"$SFP" \
}
/* Output normal jump table entry. */
#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
asm_fprintf (stream, "\t.word\t%LL%d\n", value)
/* Output pc relative jump table entry. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
do \
{ \
switch (GET_MODE (body)) \
{ \
case QImode: \
asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
break; \
case HImode: \
asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
break; \
case SImode: \
asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
break; \
default: \
gcc_unreachable(); \
} \
} while (0)
/* We have to undef it first because elfos.h formerly define it
check gcc/config.gcc and gcc/config/elfos.h for more information. */
#undef ASM_OUTPUT_CASE_LABEL
#define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
do \
{ \
asm_fprintf (stream, "\t! Jump Table Begin\n"); \
(*targetm.asm_out.internal_label) (stream, prefix, num); \
} while (0)
#define ASM_OUTPUT_CASE_END(stream, num, table) \
do \
{ \
/* Because our jump table is in text section, \
we need to make sure 2-byte alignment after \
the jump table for instructions fetch. */ \
if (GET_MODE (PATTERN (table)) == QImode) \
ASM_OUTPUT_ALIGN (stream, 1); \
asm_fprintf (stream, "\t! Jump Table End\n"); \
} while (0)
/* This macro is not documented yet.
But we do need it to make jump table vector aligned. */
#define ADDR_VEC_ALIGN(JUMPTABLE) 2
#define DWARF2_UNWIND_INFO 1
#define JUMP_ALIGN(x) \
(align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
#define LOOP_ALIGN(x) \
(align_loops_log ? align_loops_log : nds32_target_alignment (x))
#define LABEL_ALIGN(x) \
(align_labels_log ? align_labels_log : nds32_target_alignment (x))
#define ASM_OUTPUT_ALIGN(stream, power) \
fprintf (stream, "\t.align\t%d\n", power)
/* Controlling Debugging Information Format. */
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_ASM_LINE_DEBUG_INFO 1
/* Cross Compilation and Floating Point. */
/* Mode Switching Instructions. */
/* Defining target-specific uses of __attribute__. */
/* Emulating TLS. */
/* Defining coprocessor specifics for MIPS targets. */
/* Parameters for Precompiled Header Validity Checking. */
/* C++ ABI parameters. */
/* Adding support for named address spaces. */
/* Miscellaneous Parameters. */
/* This is the machine mode that elements of a jump-table should have. */
#define CASE_VECTOR_MODE Pmode
/* Return the preferred mode for and addr_diff_vec when the mininum
and maximum offset are known. */
#define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
: (max_offset >= 100) ? HImode \
: QImode)
/* Generate pc relative jump table when -fpic or -Os. */
#define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
/* Define this macro if operations between registers with integral mode
smaller than a word are always performed on the entire register. */
#define WORD_REGISTER_OPERATIONS
/* A C expression indicating when insns that read memory in mem_mode,
an integral mode narrower than a word, set the bits outside of mem_mode
to be either the sign-extension or the zero-extension of the data read. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* The maximum number of bytes that a single instruction can move quickly
between memory and registers or between two memory locations. */
#define MOVE_MAX 4
/* A C expression that is nonzero if on this machine the number of bits
actually used for the count of a shift operation is equal to the number
of bits needed to represent the size of the object being shifted. */
#define SHIFT_COUNT_TRUNCATED 1
/* A C expression which is nonzero if on this machine it is safe to "convert"
an integer of 'inprec' bits to one of 'outprec' bits by merely operating
on it as if it had only 'outprec' bits. */
#define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
/* A C expression describing the value returned by a comparison operator with
an integral mode and stored by a store-flag instruction ('cstoremode4')
when the condition is true. */
#define STORE_FLAG_VALUE 1
/* An alias for the machine mode for pointers. */
#define Pmode SImode
/* An alias for the machine mode used for memory references to functions
being called, in call RTL expressions. */
#define FUNCTION_MODE SImode
/* ------------------------------------------------------------------------ */

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; Options of Andes NDS32 cpu for GNU compiler
; Copyright (C) 2012-2013 Free Software Foundation, Inc.
; Contributed by Andes Technology Corporation.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published
; by the Free Software Foundation; either version 3, or (at your
; option) any later version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
HeaderInclude
config/nds32/nds32-opts.h
mbig-endian
Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
Generate code in big-endian mode.
mlittle-endian
Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
Generate code in little-endian mode.
mreduced-regs
Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
Use reduced-set registers for register allocation.
mfull-regs
Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
Use full-set registers for register allocation.
mcmov
Target Report Mask(CMOV)
Generate conditional move instructions.
mperf-ext
Target Report Mask(PERF_EXT)
Generate performance extension instructions.
mv3push
Target Report Mask(V3PUSH)
Generate v3 push25/pop25 instructions.
m16-bit
Target Report Mask(16_BIT)
Generate 16-bit instructions.
mgp-direct
Target Report Mask(GP_DIRECT)
Generate GP base instructions directly.
misr-vector-size=
Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
Specify the size of each interrupt vector, which must be 4 or 16.
mcache-block-size=
Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
Specify the size of each cache block, which must be a power of 2 between 4 and 512.
march=
Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
Specify the name of the target architecture.
Enum
Name(nds32_arch_type) Type(enum nds32_arch_type)
EnumValue
Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
EnumValue
Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
EnumValue
Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
mforce-fp-as-gp
Target Report Mask(FORCE_FP_AS_GP)
Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization.
mforbid-fp-as-gp
Target Report Mask(FORBID_FP_AS_GP)
Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'.
mex9
Target Report Mask(EX9)
Use special directives to guide linker doing ex9 optimization.
mctor-dtor
Target Report
Enable constructor/destructor feature.
mrelax
Target Report
Guide linker to relax instructions.

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/* Intrinsic definitions of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _NDS32_INTRINSIC_H
#define _NDS32_INTRINSIC_H
enum nds32_intrinsic_registers
{
__NDS32_REG_PSW__ = 1024,
__NDS32_REG_IPSW__,
__NDS32_REG_ITYPE__,
__NDS32_REG_IPC__
};
#endif /* nds32_intrinsic.h */

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;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "nds32_machine")
(define_cpu_unit "general_unit" "nds32_machine")
(define_insn_reservation "simple_insn" 1
(eq_attr "type" "unknown,load,store,move,alu,compare,branch,call,misc")
"general_unit")
;; ------------------------------------------------------------------------

92
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@ -0,0 +1,92 @@
;; Predicate definitions of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_predicate "nds32_equality_comparison_operator"
(match_code "eq,ne"))
(define_predicate "nds32_greater_less_comparison_operator"
(match_code "gt,ge,lt,le"))
(define_special_predicate "nds32_logical_binary_operator"
(match_code "and,ior,xor"))
(define_predicate "nds32_symbolic_operand"
(match_code "const,symbol_ref,label_ref"))
(define_predicate "nds32_reg_constant_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "const_int_operand")))
(define_predicate "nds32_rimm15s_operand"
(ior (match_operand 0 "register_operand")
(and (match_operand 0 "const_int_operand")
(match_test "satisfies_constraint_Is15 (op)"))))
(define_predicate "nds32_imm5u_operand"
(and (match_operand 0 "const_int_operand")
(match_test "satisfies_constraint_Iu05 (op)")))
(define_predicate "nds32_move_operand"
(and (match_operand 0 "general_operand")
(not (match_code "high,const,symbol_ref,label_ref")))
{
/* If the constant op does NOT satisfy Is20 nor Ihig,
we can not perform move behavior by a single instruction. */
if (CONST_INT_P (op)
&& !satisfies_constraint_Is20 (op)
&& !satisfies_constraint_Ihig (op))
return false;
return true;
})
(define_special_predicate "nds32_load_multiple_operation"
(match_code "parallel")
{
/* To verify 'load' operation, pass 'true' for the second argument.
See the implementation in nds32.c for details. */
return nds32_valid_multiple_load_store (op, true);
})
(define_special_predicate "nds32_store_multiple_operation"
(match_code "parallel")
{
/* To verify 'store' operation, pass 'false' for the second argument.
See the implementation in nds32.c for details. */
return nds32_valid_multiple_load_store (op, false);
})
(define_special_predicate "nds32_stack_push_operation"
(match_code "parallel")
{
/* To verify 'push' operation, pass 'true' for the second argument.
See the implementation in nds32.c for details. */
return nds32_valid_stack_push_pop (op, true);
})
(define_special_predicate "nds32_stack_pop_operation"
(match_code "parallel")
{
/* To verify 'pop' operation, pass 'false' for the second argument.
See the implementation in nds32.c for details. */
return nds32_valid_stack_push_pop (op, false);
})
;; ------------------------------------------------------------------------

38
gcc/config/nds32/t-mlibs Normal file
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@ -0,0 +1,38 @@
# The multilib settings of Andes NDS32 cpu for GNU compiler
# Copyright (C) 2012-2013 Free Software Foundation, Inc.
# Contributed by Andes Technology Corporation.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published
# by the Free Software Foundation; either version 3, or (at your
# option) any later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# We need to build following multilibs combinations:
#
# 1. <None multilibs>
# 2. -mlittle-endian
# 3. -mbig-endian
# 4. -mgp-direct
# 5. -mno-gp-direct
# 6. -mlittle-endian -mgp-direct
# 7. -mlittle-endian -mno-gp-direct
# 8. -mbig-endian -mgp-direct
# 9. -mlittle-endian -mno-gp-direct
#
# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the
# driver program which options are defaults for this target and thus
# do not need to be handled specially.
MULTILIB_OPTIONS = mlittle-endian/mbig-endian mgp-direct/mno-gp-direct
# ------------------------------------------------------------------------

93
gcc/doc/extend.texi
View File

@ -2505,6 +2505,12 @@ on data in the eight-bit data area. Note the eight-bit data area is limited to
You must use GAS and GLD from GNU binutils version 2.7 or later for
this attribute to work correctly.
@item exception
@cindex exception handler functions
Use this attribute on the NDS32 target to indicate that the specified function
is an exception handler. The compiler will generate corresponding sections
for use in an exception handler.
@item exception_handler
@cindex exception handler functions on the Blackfin processor
Use this attribute on the Blackfin to indicate that the specified function
@ -2965,6 +2971,32 @@ void __attribute__ ((interrupt, use_shadow_register_set,
use_debug_exception_return)) v7 ();
@end smallexample
On NDS32 target, this attribute is to indicate that the specified function
is an interrupt handler. The compiler will generate corresponding sections
for use in an interrupt handler. You can use the following attributes
to modify the behavior:
@table @code
@item nested
@cindex @code{nested} attribute
This interrupt service routine is interruptible.
@item not_nested
@cindex @code{not_nested} attribute
This interrupt service routine is not interruptible.
@item nested_ready
@cindex @code{nested_ready} attribute
This interrupt service routine is interruptible after @code{PSW.GIE}
(global interrupt enable) is set. This allows interrupt service routine to
finish some short critical code before enabling interrupts.
@item save_all
@cindex @code{save_all} attribute
The system will help save all registers into stack before entering
interrupt handler.
@item partial_save
@cindex @code{partial_save} attribute
The system will help save caller registers into stack before entering
interrupt handler.
@end table
On RL78, use @code{brk_interrupt} instead of @code{interrupt} for
handlers intended to be used with the @code{BRK} opcode (i.e.@: those
that must end with @code{RETB} instead of @code{RETI}).
@ -3201,9 +3233,10 @@ and newer.
@item naked
@cindex function without a prologue/epilogue code
Use this attribute on the ARM, AVR, MCORE, MSP430, RL78, RX and SPU ports to indicate that
the specified function does not need prologue/epilogue sequences generated by
the compiler. It is up to the programmer to provide these sequences. The
Use this attribute on the ARM, AVR, MCORE, MSP430, NDS32, RL78, RX and SPU
ports to indicate that the specified function does not need prologue/epilogue
sequences generated by the compiler.
It is up to the programmer to provide these sequences. The
only statements that can be safely included in naked functions are
@code{asm} statements that do not have operands. All other statements,
including declarations of local variables, @code{if} statements, and so
@ -3575,6 +3608,21 @@ safe since the loaders there save EAX, EDX and ECX. (Lazy binding can be
disabled with the linker or the loader if desired, to avoid the
problem.)
@item reset
@cindex reset handler functions
Use this attribute on the NDS32 target to indicate that the specified function
is a reset handler. The compiler will generate corresponding sections
for use in a reset handler. You can use the following attributes
to provide extra exception handling:
@table @code
@item nmi
@cindex @code{nmi} attribute
Provide a user-defined function to handle NMI exception.
@item warm
@cindex @code{warm} attribute
Provide a user-defined function to handle warm reset exception.
@end table
@item sseregparm
@cindex @code{sseregparm} attribute
On the Intel 386 with SSE support, the @code{sseregparm} attribute
@ -9131,6 +9179,7 @@ instructions, but allow the compiler to schedule those calls.
* MIPS Loongson Built-in Functions::
* Other MIPS Built-in Functions::
* MSP430 Built-in Functions::
* NDS32 Built-in Functions::
* picoChip Built-in Functions::
* PowerPC Built-in Functions::
* PowerPC AltiVec/VSX Built-in Functions::
@ -12584,6 +12633,44 @@ handlers and the changes to the status register will only take affect
once the handler returns.
@end table
@node NDS32 Built-in Functions
@subsection NDS32 Built-in Functions
These built-in functions are available for the NDS32 target:
@deftypefn {Built-in Function} void __builtin_nds32_isync (int *@var{addr})
Insert an ISYNC instruction into the instruction stream where
@var{addr} is an instruction address for serialization.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_nds32_isb (void)
Insert an ISB instruction into the instruction stream.
@end deftypefn
@deftypefn {Built-in Function} int __builtin_nds32_mfsr (int @var{sr})
Return the content of a system register which is mapped by @var{sr}.
@end deftypefn
@deftypefn {Built-in Function} int __builtin_nds32_mfusr (int @var{usr})
Return the content of a user space register which is mapped by @var{usr}.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_nds32_mtsr (int @var{value}, int @var{sr})
Move the @var{value} to a system register which is mapped by @var{sr}.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_nds32_mtusr (int @var{value}, int @var{usr})
Move the @var{value} to a user space register which is mapped by @var{usr}.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_nds32_setgie_en (void)
Enable global interrupt.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_nds32_setgie_dis (void)
Disable global interrupt.
@end deftypefn
@node picoChip Built-in Functions
@subsection picoChip Built-in Functions

5
gcc/doc/install.texi
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@ -1862,6 +1862,11 @@ This option is only supported for the AVR target. It is not supported for
RTEMS configurations, which currently use newlib. The option is
supported since version 4.7.2 and is the default in 4.8.0 and newer.
@item --with-nds32-lib=@var{library}
Specifies that @var{library} setting is used for building @file{libgcc.a}.
Currently, the valid @var{library} is @samp{newlib} or @samp{mculib}.
This option is only supported for the NDS32 target.
@item --with-build-time-tools=@var{dir}
Specifies where to find the set of target tools (assembler, linker, etc.)
that will be used while building GCC itself. This option can be useful

117
gcc/doc/invoke.texi
View File

@ -822,6 +822,20 @@ Objective-C and Objective-C++ Dialects}.
@emph{MSP430 Options}
@gccoptlist{-msim -masm-hex -mmcu= -mlarge -msmall -mrelax}
@emph{NDS32 Options}
@gccoptlist{-mbig-endian -mlittle-endian @gol
-mreduced-regs -mfull-regs @gol
-mcmov -mno-cmov @gol
-mperf-ext -mno-perf-ext @gol
-mv3push -mno-v3push @gol
-m16bit -mno-16bit @gol
-mgp-direct -mno-gp-direct @gol
-misr-vector-size=@var{num} @gol
-mcache-block-size=@var{num} @gol
-march=@var{arch} @gol
-mforce-fp-as-gp -mforbid-fp-as-gp @gol
-mex9 -mctor-dtor -mrelax}
@emph{PDP-11 Options}
@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
-mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol
@ -10991,6 +11005,7 @@ platform.
* MN10300 Options::
* Moxie Options::
* MSP430 Options::
* NDS32 Options::
* PDP-11 Options::
* picoChip Options::
* PowerPC Options::
@ -17792,6 +17807,108 @@ the final link.
@end table
@node NDS32 Options
@subsection NDS32 Options
@cindex NDS32 Options
These options are defined for NDS32 implementations:
@table @gcctabopt
@item -mbig-endian
@opindex mbig-endian
Generate code in big-endian mode.
@item -mlittle-endian
@opindex mlittle-endian
Generate code in little-endian mode.
@item -mreduced-regs
@opindex mreduced-regs
Use reduced-set registers for register allocation.
@item -mfull-regs
@opindex mfull-regs
Use full-set registers for register allocation.
@item -mcmov
@opindex mcmov
Generate conditional move instructions.
@item -mno-cmov
@opindex mno-cmov
Do not generate conditional move instructions.
@item -mperf-ext
@opindex mperf-ext
Generate performance extension instructions.
@item -mno-perf-ext
@opindex mno-perf-ext
Do not generate performance extension instructions.
@item -mv3push
@opindex mv3push
Generate v3 push25/pop25 instructions.
@item -mno-v3push
@opindex mno-v3push
Do not generate v3 push25/pop25 instructions.
@item -m16-bit
@opindex m16-bit
Generate 16-bit instructions.
@item -mno-16-bit
@opindex mno-16-bit
Do not generate 16-bit instructions.
@item -mgp-direct
@opindex mgp-direct
Generate GP base instructions directly.
@item -mno-gp-direct
@opindex mno-gp-direct
Do no generate GP base instructions directly.
@item -misr-vector-size=@var{num}
@opindex misr-vector-size
Specify the size of each interrupt vector, which must be 4 or 16.
@item -mcache-block-size=@var{num}
@opindex mcache-block-size
Specify the size of each cache block,
which must be a power of 2 between 4 and 512.
@item -march=@var{arch}
@opindex march
Specify the name of the target architecture.
@item -mforce-fp-as-gp
@opindex mforce-fp-as-gp
Prevent $fp being allocated during register allocation so that compiler
is able to force performing fp-as-gp optimization.
@item -mforbid-fp-as-gp
@opindex mforbid-fp-as-gp
Forbid using $fp to access static and global variables.
This option strictly forbids fp-as-gp optimization
regardless of @option{-mforce-fp-as-gp}.
@item -mex9
@opindex mex9
Use special directives to guide linker doing ex9 optimization.
@item -mctor-dtor
@opindex mctor-dtor
Enable constructor/destructor feature.
@item -mrelax
@opindex mrelax
Guide linker to relax instructions.
@end table
@node PDP-11 Options
@subsection PDP-11 Options
@cindex PDP-11 Options

81
gcc/doc/md.texi
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@ -3152,6 +3152,87 @@ Memory reference, stack only.
@end table
@item NDS32---@file{config/nds32/constraints.md}
@table @code
@item w
LOW register class $r0 to $r7 constraint for V3/V3M ISA.
@item l
LOW register class $r0 to $r7.
@item d
MIDDLE register class $r0 to $r11, $r16 to $r19.
@item h
HIGH register class $r12 to $r14, $r20 to $r31.
@item t
Temporary assist register $ta (i.e.@: $r15).
@item k
Stack register $sp.
@item Iu03
Unsigned immediate 3-bit value.
@item In03
Negative immediate 3-bit value in the range of @minus{}7--0.
@item Iu04
Unsigned immediate 4-bit value.
@item Is05
Signed immediate 5-bit value.
@item Iu05
Unsigned immediate 5-bit value.
@item In05
Negative immediate 5-bit value in the range of @minus{}31--0.
@item Ip05
Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
@item Iu06
Unsigned immediate 6-bit value constraint for addri36.sp instruction.
@item Iu08
Unsigned immediate 8-bit value.
@item Iu09
Unsigned immediate 9-bit value.
@item Is10
Signed immediate 10-bit value.
@item Is11
Signed immediate 11-bit value.
@item Is15
Signed immediate 15-bit value.
@item Iu15
Unsigned immediate 15-bit value.
@item Ic15
A constant which is not in the range of imm15u but ok for bclr instruction.
@item Ie15
A constant which is not in the range of imm15u but ok for bset instruction.
@item It15
A constant which is not in the range of imm15u but ok for btgl instruction.
@item Ii15
A constant whose compliment value is in the range of imm15u
and ok for bitci instruction.
@item Is16
Signed immediate 16-bit value.
@item Is17
Signed immediate 17-bit value.
@item Is19
Signed immediate 19-bit value.
@item Is20
Signed immediate 20-bit value.
@item Ihig
The immediate value that can be simply set high 20-bit.
@item Izeb
The immediate value 0xff.
@item Izeh
The immediate value 0xffff.
@item Ixls
The immediate value 0x01.
@item Ix11
The immediate value 0x7ff.
@item Ibms
The immediate value with power of 2.
@item Ifex
The immediate value with power of 2 minus 1.
@item U33
Memory constraint for 333 format.
@item U45
Memory constraint for 45 format.
@item U37
Memory constraint for 37 format.
@end table
@item PDP-11---@file{config/pdp11/constraints.md}
@table @code
@item a

6
libgcc/ChangeLog
View File

@ -1,3 +1,9 @@
2013-10-31 Chung-Ju Wu <jasonwucj@gmail.com>
Shiva Chen <shiva0217@gmail.com>
* config.host (nds32*-elf*): Add nds32 target.
* config/nds32 : New directory and files.
2013-10-16 Hans-Peter Nilsson <hp@axis.com>
For CRIS ports, switch to soft-fp. Improve arit.c and longlong.h.

26
libgcc/config.host
View File

@ -143,6 +143,9 @@ mips*-*-*)
cpu_type=mips
tmake_file=mips/t-mips
;;
nds32*-*)
cpu_type=nds32
;;
powerpc*-*-*)
cpu_type=rs6000
;;
@ -850,6 +853,29 @@ moxie-*-rtems*)
msp430*-*-elf)
tmake_file="$tm_file t-crtstuff t-fdpbit msp430/t-msp430"
;;
nds32*-elf*)
# Basic makefile fragment and extra_parts for crt stuff.
# We also append c-isr library implementation.
tmake_file="${tmake_file} nds32/t-nds32 nds32/t-nds32-isr"
extra_parts="crtbegin1.o crtend1.o libnds32_isr.a"
# Append library definition makefile fragment according to --with-nds32-lib=X setting.
case "${with_nds32_lib}" in
"" | newlib)
# Append library definition makefile fragment t-nds32-newlib.
# Append 'soft-fp' software floating point make rule fragment provided by gcc.
tmake_file="${tmake_file} nds32/t-nds32-newlib t-softfp-sfdf t-softfp"
;;
mculib)
# Append library definition makefile fragment t-nds32-mculib.
# The software floating point library is included in mculib.
tmake_file="${tmake_file} nds32/t-nds32-mculib"
;;
*)
echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2
exit 1
;;
esac
;;
pdp11-*-*)
tmake_file="pdp11/t-pdp11 t-fdpbit"
;;

103
libgcc/config/nds32/crtzero.S Normal file
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@ -0,0 +1,103 @@
/* The startup code sample of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
!!==============================================================================
!!
!! crtzero.S
!!
!! This is JUST A SAMPLE of nds32 startup code !!
!! You can refer this content and implement
!! the actual one in newlib/mculib.
!!
!!==============================================================================
!!------------------------------------------------------------------------------
!! Jump to start up code
!!------------------------------------------------------------------------------
.section .nds32_init, "ax"
j _start
!!------------------------------------------------------------------------------
!! Startup code implementation
!!------------------------------------------------------------------------------
.section .text
.global _start
.weak _SDA_BASE_
.weak _FP_BASE_
.align 2
.func _start
.type _start, @function
_start:
.L_fp_gp_lp_init:
la $fp, _FP_BASE_ ! init $fp
la $gp, _SDA_BASE_ ! init $gp for small data access
movi $lp, 0 ! init $lp
.L_stack_init:
la $sp, _stack ! init $sp
movi $r0, -8 ! align $sp to 8-byte (use 0xfffffff8)
and $sp, $sp, $r0 ! align $sp to 8-byte (filter out lower 3-bit)
.L_bss_init:
! clear BSS, this process can be 4 time faster if data is 4 byte aligned
! if so, use swi.p instead of sbi.p
! the related stuff are defined in linker script
la $r0, _edata ! get the starting addr of bss
la $r2, _end ! get ending addr of bss
beq $r0, $r2, .L_call_main ! if no bss just do nothing
movi $r1, 0 ! should be cleared to 0
.L_clear_bss:
sbi.p $r1, [$r0], 1 ! Set 0 to bss
bne $r0, $r2, .L_clear_bss ! Still bytes left to set
!.L_stack_heap_check:
! la $r0, _end ! init heap_end
! s.w $r0, heap_end ! save it
!.L_init_argc_argv:
! ! argc/argv initialization if necessary; default implementation is in crt1.o
! la $r9, _arg_init ! load address of _arg_init?
! beqz $r9, .L4 ! has _arg_init? no, go check main()
! addi $sp, $sp, -512 ! allocate space for command line + arguments
! move $r6, $sp ! r6 = buffer addr of cmd line
! move $r0, $r6 ! r0 = buffer addr of cmd line
! syscall 6002 ! get cmd line
! move $r0, $r6 ! r0 = buffer addr of cmd line
! addi $r1, $r6, 256 ! r1 = argv
! jral $r9 ! init argc/argv
! addi $r1, $r6, 256 ! r1 = argv
.L_call_main:
! call main() if main() is provided
la $r15, main ! load address of main
jral $r15 ! call main
.L_terminate_program:
syscall 0x1 ! use syscall 0x1 to terminate program
.size _start, .-_start
.end
!! ------------------------------------------------------------------------

159
libgcc/config/nds32/initfini.c Normal file
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@ -0,0 +1,159 @@
/* .init/.fini section handling + C++ global constructor/destructor
handling of Andes NDS32 cpu for GNU compiler.
This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm.
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Declare a pointer to void function type. */
typedef void (*func_ptr) (void);
#ifdef CRT_BEGIN
/* NOTE: In order to be able to support SVR4 shared libraries, we arrange
to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__,
__DTOR_END__ } per root executable and also one set of these symbols
per shared library. So in any given whole process image, we may have
multiple definitions of each of these symbols. In order to prevent
these definitions from conflicting with one another, and in order to
ensure that the proper lists are used for the initialization/finalization
of each individual shared library (respectively), we give these symbols
only internal (i.e. `static') linkage, and we also make it a point to
refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
symbol in crtinit.o, where they are defined. */
static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors")))
= { (func_ptr) (-1) };
static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
= { (func_ptr) (-1) };
/* Run all the global destructors on exit from the program. */
/* Some systems place the number of pointers in the first word of the
table. On SVR4 however, that word is -1. In all cases, the table is
null-terminated. On SVR4, we start from the beginning of the list and
invoke each per-compilation-unit destructor routine in order
until we find that null.
Note that this function MUST be static. There will be one of these
functions in each root executable and one in each shared library, but
although they all have the same code, each one is unique in that it
refers to one particular associated `__DTOR_LIST__' which belongs to the
same particular root executable or shared library file. */
static void __do_global_dtors (void)
asm ("__do_global_dtors") __attribute__ ((section (".text")));
static void
__do_global_dtors (void)
{
func_ptr *p;
for (p = __DTOR_LIST__ + 1; *p; p++)
(*p) ();
}
/* .init section start.
This must appear at the start of the .init section. */
asm ("\n\
.section .init\n\
.global _init\n\
.type _init, @function\n\
_init:\n\
! 1. store $fp\n\
! 2. adjust $fp by $sp\n\
! 3. adjust $sp\n\
");
/* .fini section start.
This must appear at the start of the .fini section. */
asm ("\n\
.section .fini\n\
.global _fini\n\
.type _fini, @function\n\
_fini:\n\
! 1. store $fp\n\
! 2. adjust $fp by $sp\n\
! 3. adjust $sp\n\
! 4. call __do_global_dtors\n\
j __do_global_dtors\n\
");
#endif /* CRT_BEGIN */
#ifdef CRT_END
/* Define __dso_handle which would be needed for C++ library.
Since our elf-toolchain only builds programs with static link,
we can directly define 'void *__dso_handle = 0'. */
void *__dso_handle = 0;
/* Put a word containing zero at the end of each of our two lists of function
addresses. Note that the words defined here go into the .ctors and .dtors
sections of the crtend.o file, and since that file is always linked in
last, these words naturally end up at the very ends of the two lists
contained in these two sections. */
static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors")))
= { (func_ptr) 0 };
static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors")))
= { (func_ptr) 0 };
/* Run all global constructors for the program.
Note that they are run in reverse order. */
static void __do_global_ctors (void)
asm ("__do_global_ctors") __attribute__ ((section (".text")));
static void
__do_global_ctors (void)
{
func_ptr *p;
for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
(*p) ();
}
/* .init section end.
This must live at the end of the .init section. */
asm ("\n\
.section .init\n\
! 1. call __do_global_ctors\n\
! 2. adjust back $sp\n\
! 3. restore $fp\n\
j __do_global_ctors\n\
");
/* .fini section end.
This must live at the end of the .fini section. */
asm ("\n\
.section .fini\n\
! 1. adjust back $sp\n\
! 2. restore $fp\n\
");
#endif /* CRT_END */

38
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/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.macro ADJ_INTR_LVL
#if defined(NDS32_NESTED) /* Nested handler. */
mfsr $r3, $PSW
addi $r3, $r3, #-0x1
mtsr $r3, $PSW
#elif defined(NDS32_NESTED_READY) /* Nested ready handler. */
/* Save ipc and ipsw and lower INT level. */
mfsr $r3, $PSW
addi $r3, $r3, #-0x2
mtsr $r3, $PSW
#else /* Not nested handler. */
#endif
.endm

132
libgcc/config/nds32/isr-library/excp_isr.S Normal file
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/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is original 16-byte vector size version.
*/
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_e_sa_ns
.type _nds32_e_sa_ns, @function
_nds32_e_sa_ns:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_sa_nr
.type _nds32_e_sa_nr, @function
_nds32_e_sa_nr:
#else /* Not nested handler. */
.globl _nds32_e_sa_nn
.type _nds32_e_sa_nn, @function
_nds32_e_sa_nn:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.globl _nds32_e_ps_ns
.type _nds32_e_ps_ns, @function
_nds32_e_ps_ns:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_ps_nr
.type _nds32_e_ps_nr, @function
_nds32_e_ps_nr:
#else /* Not nested handler. */
.globl _nds32_e_ps_nn
.type _nds32_e_ps_nn, @function
_nds32_e_ps_nn:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 16-byte vector size version.
The vector id was restored into $r0 in vector by compiler.
*/
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL
#else
SAVE_PARTIAL
#endif
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
RESTORE_PARTIAL
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_e_sa_ns, .-_nds32_e_sa_ns
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_sa_nr, .-_nds32_e_sa_nr
#else /* Not nested handler. */
.size _nds32_e_sa_nn, .-_nds32_e_sa_nn
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.size _nds32_e_ps_ns, .-_nds32_e_ps_ns
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_ps_nr, .-_nds32_e_ps_nr
#else /* Not nested handler. */
.size _nds32_e_ps_nn, .-_nds32_e_ps_nn
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */

133
libgcc/config/nds32/isr-library/excp_isr_4b.S Normal file
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/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is 4-byte vector size version.
The "_4b" postfix was added for 4-byte version symbol.
*/
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_e_sa_ns_4b
.type _nds32_e_sa_ns_4b, @function
_nds32_e_sa_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_sa_nr_4b
.type _nds32_e_sa_nr_4b, @function
_nds32_e_sa_nr_4b:
#else /* Not nested handler. */
.globl _nds32_e_sa_nn_4b
.type _nds32_e_sa_nn_4b, @function
_nds32_e_sa_nn_4b:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.globl _nds32_e_ps_ns_4b
.type _nds32_e_ps_ns_4b, @function
_nds32_e_ps_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_ps_nr_4b
.type _nds32_e_ps_nr_4b, @function
_nds32_e_ps_nr_4b:
#else /* Not nested handler. */
.globl _nds32_e_ps_nn_4b
.type _nds32_e_ps_nn_4b, @function
_nds32_e_ps_nn_4b:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 4-byte vector size version.
The vector id was restored into $lp in vector by compiler.
*/
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL_4B
#else
SAVE_PARTIAL_4B
#endif
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
RESTORE_PARTIAL
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_e_sa_ns_4b, .-_nds32_e_sa_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_sa_nr_4b, .-_nds32_e_sa_nr_4b
#else /* Not nested handler. */
.size _nds32_e_sa_nn_4b, .-_nds32_e_sa_nn_4b
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.size _nds32_e_ps_ns_4b, .-_nds32_e_ps_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_ps_nr_4b, .-_nds32_e_ps_nr_4b
#else /* Not nested handler. */
.size _nds32_e_ps_nn_4b, .-_nds32_e_ps_nn_4b
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */

132
libgcc/config/nds32/isr-library/intr_isr.S Normal file
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/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is original 16-byte vector size version.
*/
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_i_sa_ns
.type _nds32_i_sa_ns, @function
_nds32_i_sa_ns:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_i_sa_nr
.type _nds32_i_sa_nr, @function
_nds32_i_sa_nr:
#else /* Not nested handler. */
.globl _nds32_i_sa_nn
.type _nds32_i_sa_nn, @function
_nds32_i_sa_nn:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.globl _nds32_i_ps_ns
.type _nds32_i_ps_ns, @function
_nds32_i_ps_ns:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_i_ps_nr
.type _nds32_i_ps_nr, @function
_nds32_i_ps_nr:
#else /* Not nested handler. */
.globl _nds32_i_ps_nn
.type _nds32_i_ps_nn, @function
_nds32_i_ps_nn:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 16-byte vector size version.
The vector id was restored into $r0 in vector by compiler.
*/
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL
#else
SAVE_PARTIAL
#endif
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
RESTORE_PARTIAL
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_i_sa_ns, .-_nds32_i_sa_ns
#elif defined(NDS32_NESTED_READY)
.size _nds32_i_sa_nr, .-_nds32_i_sa_nr
#else /* Not nested handler. */
.size _nds32_i_sa_nn, .-_nds32_i_sa_nn
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.size _nds32_i_ps_ns, .-_nds32_i_ps_ns
#elif defined(NDS32_NESTED_READY)
.size _nds32_i_ps_nr, .-_nds32_i_ps_nr
#else /* Not nested handler. */
.size _nds32_i_ps_nn, .-_nds32_i_ps_nn
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */

134
libgcc/config/nds32/isr-library/intr_isr_4b.S Normal file
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/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is 4-byte vector size version.
The "_4b" postfix was added for 4-byte version symbol.
*/
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_i_sa_ns_4b
.type _nds32_i_sa_ns_4b, @function
_nds32_i_sa_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_i_sa_nr_4b
.type _nds32_i_sa_nr_4b, @function
_nds32_i_sa_nr_4b:
#else /* Not nested handler. */
.globl _nds32_i_sa_nn_4b
.type _nds32_i_sa_nn_4b, @function
_nds32_i_sa_nn_4b:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.globl _nds32_i_ps_ns_4b
.type _nds32_i_ps_ns_4b, @function
_nds32_i_ps_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_i_ps_nr_4b
.type _nds32_i_ps_nr_4b, @function
_nds32_i_ps_nr_4b:
#else /* Not nested handler. */
.globl _nds32_i_ps_nn_4b
.type _nds32_i_ps_nn_4b, @function
_nds32_i_ps_nn_4b:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 4-byte vector size version.
The vector id was restored into $lp in vector by compiler.
*/
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL_4B
#else
SAVE_PARTIAL_4B
#endif
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
RESTORE_PARTIAL
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_i_sa_ns_4b, .-_nds32_i_sa_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_i_sa_nr_4b, .-_nds32_i_sa_nr_4b
#else /* Not nested handler. */
.size _nds32_i_sa_nn_4b, .-_nds32_i_sa_nn_4b
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.size _nds32_i_ps_ns_4b, .-_nds32_i_ps_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_i_ps_nr_4b, .-_nds32_i_ps_nr_4b
#else /* Not nested handler. */
.size _nds32_i_ps_nn_4b, .-_nds32_i_ps_nn_4b
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */

32
libgcc/config/nds32/isr-library/jmptbl_vid00.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.00, "a"
.align 2
.weak _nds32_jmptbl_00
.type _nds32_jmptbl_00, @object
_nds32_jmptbl_00:
.word 0
.size _nds32_jmptbl_00, .-_nds32_jmptbl_00

32
libgcc/config/nds32/isr-library/jmptbl_vid01.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.01, "a"
.align 2
.weak _nds32_jmptbl_01
.type _nds32_jmptbl_01, @object
_nds32_jmptbl_01:
.word 0
.size _nds32_jmptbl_01, .-_nds32_jmptbl_01

32
libgcc/config/nds32/isr-library/jmptbl_vid02.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.02, "a"
.align 2
.weak _nds32_jmptbl_02
.type _nds32_jmptbl_02, @object
_nds32_jmptbl_02:
.word 0
.size _nds32_jmptbl_02, .-_nds32_jmptbl_02

32
libgcc/config/nds32/isr-library/jmptbl_vid03.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.03, "a"
.align 2
.weak _nds32_jmptbl_03
.type _nds32_jmptbl_03, @object
_nds32_jmptbl_03:
.word 0
.size _nds32_jmptbl_03, .-_nds32_jmptbl_03

32
libgcc/config/nds32/isr-library/jmptbl_vid04.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.04, "a"
.align 2
.weak _nds32_jmptbl_04
.type _nds32_jmptbl_04, @object
_nds32_jmptbl_04:
.word 0
.size _nds32_jmptbl_04, .-_nds32_jmptbl_04

32
libgcc/config/nds32/isr-library/jmptbl_vid05.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.05, "a"
.align 2
.weak _nds32_jmptbl_05
.type _nds32_jmptbl_05, @object
_nds32_jmptbl_05:
.word 0
.size _nds32_jmptbl_05, .-_nds32_jmptbl_05

32
libgcc/config/nds32/isr-library/jmptbl_vid06.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.06, "a"
.align 2
.weak _nds32_jmptbl_06
.type _nds32_jmptbl_06, @object
_nds32_jmptbl_06:
.word 0
.size _nds32_jmptbl_06, .-_nds32_jmptbl_06

32
libgcc/config/nds32/isr-library/jmptbl_vid07.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.07, "a"
.align 2
.weak _nds32_jmptbl_07
.type _nds32_jmptbl_07, @object
_nds32_jmptbl_07:
.word 0
.size _nds32_jmptbl_07, .-_nds32_jmptbl_07

32
libgcc/config/nds32/isr-library/jmptbl_vid08.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.08, "a"
.align 2
.weak _nds32_jmptbl_08
.type _nds32_jmptbl_08, @object
_nds32_jmptbl_08:
.word 0
.size _nds32_jmptbl_08, .-_nds32_jmptbl_08

32
libgcc/config/nds32/isr-library/jmptbl_vid09.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.09, "a"
.align 2
.weak _nds32_jmptbl_09
.type _nds32_jmptbl_09, @object
_nds32_jmptbl_09:
.word 0
.size _nds32_jmptbl_09, .-_nds32_jmptbl_09

32
libgcc/config/nds32/isr-library/jmptbl_vid10.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.10, "a"
.align 2
.weak _nds32_jmptbl_10
.type _nds32_jmptbl_10, @object
_nds32_jmptbl_10:
.word 0
.size _nds32_jmptbl_10, .-_nds32_jmptbl_10

32
libgcc/config/nds32/isr-library/jmptbl_vid11.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.11, "a"
.align 2
.weak _nds32_jmptbl_11
.type _nds32_jmptbl_11, @object
_nds32_jmptbl_11:
.word 0
.size _nds32_jmptbl_11, .-_nds32_jmptbl_11

32
libgcc/config/nds32/isr-library/jmptbl_vid12.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.12, "a"
.align 2
.weak _nds32_jmptbl_12
.type _nds32_jmptbl_12, @object
_nds32_jmptbl_12:
.word 0
.size _nds32_jmptbl_12, .-_nds32_jmptbl_12

32
libgcc/config/nds32/isr-library/jmptbl_vid13.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.13, "a"
.align 2
.weak _nds32_jmptbl_13
.type _nds32_jmptbl_13, @object
_nds32_jmptbl_13:
.word 0
.size _nds32_jmptbl_13, .-_nds32_jmptbl_13

32
libgcc/config/nds32/isr-library/jmptbl_vid14.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.14, "a"
.align 2
.weak _nds32_jmptbl_14
.type _nds32_jmptbl_14, @object
_nds32_jmptbl_14:
.word 0
.size _nds32_jmptbl_14, .-_nds32_jmptbl_14

32
libgcc/config/nds32/isr-library/jmptbl_vid15.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.15, "a"
.align 2
.weak _nds32_jmptbl_15
.type _nds32_jmptbl_15, @object
_nds32_jmptbl_15:
.word 0
.size _nds32_jmptbl_15, .-_nds32_jmptbl_15

32
libgcc/config/nds32/isr-library/jmptbl_vid16.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.16, "a"
.align 2
.weak _nds32_jmptbl_16
.type _nds32_jmptbl_16, @object
_nds32_jmptbl_16:
.word 0
.size _nds32_jmptbl_16, .-_nds32_jmptbl_16

32
libgcc/config/nds32/isr-library/jmptbl_vid17.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.17, "a"
.align 2
.weak _nds32_jmptbl_17
.type _nds32_jmptbl_17, @object
_nds32_jmptbl_17:
.word 0
.size _nds32_jmptbl_17, .-_nds32_jmptbl_17

32
libgcc/config/nds32/isr-library/jmptbl_vid18.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.18, "a"
.align 2
.weak _nds32_jmptbl_18
.type _nds32_jmptbl_18, @object
_nds32_jmptbl_18:
.word 0
.size _nds32_jmptbl_18, .-_nds32_jmptbl_18

32
libgcc/config/nds32/isr-library/jmptbl_vid19.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.19, "a"
.align 2
.weak _nds32_jmptbl_19
.type _nds32_jmptbl_19, @object
_nds32_jmptbl_19:
.word 0
.size _nds32_jmptbl_19, .-_nds32_jmptbl_19

32
libgcc/config/nds32/isr-library/jmptbl_vid20.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.20, "a"
.align 2
.weak _nds32_jmptbl_20
.type _nds32_jmptbl_20, @object
_nds32_jmptbl_20:
.word 0
.size _nds32_jmptbl_20, .-_nds32_jmptbl_20

32
libgcc/config/nds32/isr-library/jmptbl_vid21.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.21, "a"
.align 2
.weak _nds32_jmptbl_21
.type _nds32_jmptbl_21, @object
_nds32_jmptbl_21:
.word 0
.size _nds32_jmptbl_21, .-_nds32_jmptbl_21

32
libgcc/config/nds32/isr-library/jmptbl_vid22.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.22, "a"
.align 2
.weak _nds32_jmptbl_22
.type _nds32_jmptbl_22, @object
_nds32_jmptbl_22:
.word 0
.size _nds32_jmptbl_22, .-_nds32_jmptbl_22

32
libgcc/config/nds32/isr-library/jmptbl_vid23.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.23, "a"
.align 2
.weak _nds32_jmptbl_23
.type _nds32_jmptbl_23, @object
_nds32_jmptbl_23:
.word 0
.size _nds32_jmptbl_23, .-_nds32_jmptbl_23

32
libgcc/config/nds32/isr-library/jmptbl_vid24.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.24, "a"
.align 2
.weak _nds32_jmptbl_24
.type _nds32_jmptbl_24, @object
_nds32_jmptbl_24:
.word 0
.size _nds32_jmptbl_24, .-_nds32_jmptbl_24

32
libgcc/config/nds32/isr-library/jmptbl_vid25.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.25, "a"
.align 2
.weak _nds32_jmptbl_25
.type _nds32_jmptbl_25, @object
_nds32_jmptbl_25:
.word 0
.size _nds32_jmptbl_25, .-_nds32_jmptbl_25

32
libgcc/config/nds32/isr-library/jmptbl_vid26.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.26, "a"
.align 2
.weak _nds32_jmptbl_26
.type _nds32_jmptbl_26, @object
_nds32_jmptbl_26:
.word 0
.size _nds32_jmptbl_26, .-_nds32_jmptbl_26

32
libgcc/config/nds32/isr-library/jmptbl_vid27.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.27, "a"
.align 2
.weak _nds32_jmptbl_27
.type _nds32_jmptbl_27, @object
_nds32_jmptbl_27:
.word 0
.size _nds32_jmptbl_27, .-_nds32_jmptbl_27

32
libgcc/config/nds32/isr-library/jmptbl_vid28.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.28, "a"
.align 2
.weak _nds32_jmptbl_28
.type _nds32_jmptbl_28, @object
_nds32_jmptbl_28:
.word 0
.size _nds32_jmptbl_28, .-_nds32_jmptbl_28

32
libgcc/config/nds32/isr-library/jmptbl_vid29.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.29, "a"
.align 2
.weak _nds32_jmptbl_29
.type _nds32_jmptbl_29, @object
_nds32_jmptbl_29:
.word 0
.size _nds32_jmptbl_29, .-_nds32_jmptbl_29

32
libgcc/config/nds32/isr-library/jmptbl_vid30.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.30, "a"
.align 2
.weak _nds32_jmptbl_30
.type _nds32_jmptbl_30, @object
_nds32_jmptbl_30:
.word 0
.size _nds32_jmptbl_30, .-_nds32_jmptbl_30

32
libgcc/config/nds32/isr-library/jmptbl_vid31.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.31, "a"
.align 2
.weak _nds32_jmptbl_31
.type _nds32_jmptbl_31, @object
_nds32_jmptbl_31:
.word 0
.size _nds32_jmptbl_31, .-_nds32_jmptbl_31

32
libgcc/config/nds32/isr-library/jmptbl_vid32.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.32, "a"
.align 2
.weak _nds32_jmptbl_32
.type _nds32_jmptbl_32, @object
_nds32_jmptbl_32:
.word 0
.size _nds32_jmptbl_32, .-_nds32_jmptbl_32

32
libgcc/config/nds32/isr-library/jmptbl_vid33.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.33, "a"
.align 2
.weak _nds32_jmptbl_33
.type _nds32_jmptbl_33, @object
_nds32_jmptbl_33:
.word 0
.size _nds32_jmptbl_33, .-_nds32_jmptbl_33

32
libgcc/config/nds32/isr-library/jmptbl_vid34.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.34, "a"
.align 2
.weak _nds32_jmptbl_34
.type _nds32_jmptbl_34, @object
_nds32_jmptbl_34:
.word 0
.size _nds32_jmptbl_34, .-_nds32_jmptbl_34

32
libgcc/config/nds32/isr-library/jmptbl_vid35.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.35, "a"
.align 2
.weak _nds32_jmptbl_35
.type _nds32_jmptbl_35, @object
_nds32_jmptbl_35:
.word 0
.size _nds32_jmptbl_35, .-_nds32_jmptbl_35

32
libgcc/config/nds32/isr-library/jmptbl_vid36.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.36, "a"
.align 2
.weak _nds32_jmptbl_36
.type _nds32_jmptbl_36, @object
_nds32_jmptbl_36:
.word 0
.size _nds32_jmptbl_36, .-_nds32_jmptbl_36

32
libgcc/config/nds32/isr-library/jmptbl_vid37.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.37, "a"
.align 2
.weak _nds32_jmptbl_37
.type _nds32_jmptbl_37, @object
_nds32_jmptbl_37:
.word 0
.size _nds32_jmptbl_37, .-_nds32_jmptbl_37

32
libgcc/config/nds32/isr-library/jmptbl_vid38.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.38, "a"
.align 2
.weak _nds32_jmptbl_38
.type _nds32_jmptbl_38, @object
_nds32_jmptbl_38:
.word 0
.size _nds32_jmptbl_38, .-_nds32_jmptbl_38

32
libgcc/config/nds32/isr-library/jmptbl_vid39.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.39, "a"
.align 2
.weak _nds32_jmptbl_39
.type _nds32_jmptbl_39, @object
_nds32_jmptbl_39:
.word 0
.size _nds32_jmptbl_39, .-_nds32_jmptbl_39

32
libgcc/config/nds32/isr-library/jmptbl_vid40.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.40, "a"
.align 2
.weak _nds32_jmptbl_40
.type _nds32_jmptbl_40, @object
_nds32_jmptbl_40:
.word 0
.size _nds32_jmptbl_40, .-_nds32_jmptbl_40

32
libgcc/config/nds32/isr-library/jmptbl_vid41.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.41, "a"
.align 2
.weak _nds32_jmptbl_41
.type _nds32_jmptbl_41, @object
_nds32_jmptbl_41:
.word 0
.size _nds32_jmptbl_41, .-_nds32_jmptbl_41

32
libgcc/config/nds32/isr-library/jmptbl_vid42.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.42, "a"
.align 2
.weak _nds32_jmptbl_42
.type _nds32_jmptbl_42, @object
_nds32_jmptbl_42:
.word 0
.size _nds32_jmptbl_42, .-_nds32_jmptbl_42

32
libgcc/config/nds32/isr-library/jmptbl_vid43.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.43, "a"
.align 2
.weak _nds32_jmptbl_43
.type _nds32_jmptbl_43, @object
_nds32_jmptbl_43:
.word 0
.size _nds32_jmptbl_43, .-_nds32_jmptbl_43

32
libgcc/config/nds32/isr-library/jmptbl_vid44.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.44, "a"
.align 2
.weak _nds32_jmptbl_44
.type _nds32_jmptbl_44, @object
_nds32_jmptbl_44:
.word 0
.size _nds32_jmptbl_44, .-_nds32_jmptbl_44

32
libgcc/config/nds32/isr-library/jmptbl_vid45.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.45, "a"
.align 2
.weak _nds32_jmptbl_45
.type _nds32_jmptbl_45, @object
_nds32_jmptbl_45:
.word 0
.size _nds32_jmptbl_45, .-_nds32_jmptbl_45

32
libgcc/config/nds32/isr-library/jmptbl_vid46.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.46, "a"
.align 2
.weak _nds32_jmptbl_46
.type _nds32_jmptbl_46, @object
_nds32_jmptbl_46:
.word 0
.size _nds32_jmptbl_46, .-_nds32_jmptbl_46

32
libgcc/config/nds32/isr-library/jmptbl_vid47.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.47, "a"
.align 2
.weak _nds32_jmptbl_47
.type _nds32_jmptbl_47, @object
_nds32_jmptbl_47:
.word 0
.size _nds32_jmptbl_47, .-_nds32_jmptbl_47

32
libgcc/config/nds32/isr-library/jmptbl_vid48.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.48, "a"
.align 2
.weak _nds32_jmptbl_48
.type _nds32_jmptbl_48, @object
_nds32_jmptbl_48:
.word 0
.size _nds32_jmptbl_48, .-_nds32_jmptbl_48

32
libgcc/config/nds32/isr-library/jmptbl_vid49.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.49, "a"
.align 2
.weak _nds32_jmptbl_49
.type _nds32_jmptbl_49, @object
_nds32_jmptbl_49:
.word 0
.size _nds32_jmptbl_49, .-_nds32_jmptbl_49

32
libgcc/config/nds32/isr-library/jmptbl_vid50.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.50, "a"
.align 2
.weak _nds32_jmptbl_50
.type _nds32_jmptbl_50, @object
_nds32_jmptbl_50:
.word 0
.size _nds32_jmptbl_50, .-_nds32_jmptbl_50

32
libgcc/config/nds32/isr-library/jmptbl_vid51.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.51, "a"
.align 2
.weak _nds32_jmptbl_51
.type _nds32_jmptbl_51, @object
_nds32_jmptbl_51:
.word 0
.size _nds32_jmptbl_51, .-_nds32_jmptbl_51

32
libgcc/config/nds32/isr-library/jmptbl_vid52.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.52, "a"
.align 2
.weak _nds32_jmptbl_52
.type _nds32_jmptbl_52, @object
_nds32_jmptbl_52:
.word 0
.size _nds32_jmptbl_52, .-_nds32_jmptbl_52

32
libgcc/config/nds32/isr-library/jmptbl_vid53.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.53, "a"
.align 2
.weak _nds32_jmptbl_53
.type _nds32_jmptbl_53, @object
_nds32_jmptbl_53:
.word 0
.size _nds32_jmptbl_53, .-_nds32_jmptbl_53

32
libgcc/config/nds32/isr-library/jmptbl_vid54.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.54, "a"
.align 2
.weak _nds32_jmptbl_54
.type _nds32_jmptbl_54, @object
_nds32_jmptbl_54:
.word 0
.size _nds32_jmptbl_54, .-_nds32_jmptbl_54

32
libgcc/config/nds32/isr-library/jmptbl_vid55.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.55, "a"
.align 2
.weak _nds32_jmptbl_55
.type _nds32_jmptbl_55, @object
_nds32_jmptbl_55:
.word 0
.size _nds32_jmptbl_55, .-_nds32_jmptbl_55

32
libgcc/config/nds32/isr-library/jmptbl_vid56.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.56, "a"
.align 2
.weak _nds32_jmptbl_56
.type _nds32_jmptbl_56, @object
_nds32_jmptbl_56:
.word 0
.size _nds32_jmptbl_56, .-_nds32_jmptbl_56

32
libgcc/config/nds32/isr-library/jmptbl_vid57.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.57, "a"
.align 2
.weak _nds32_jmptbl_57
.type _nds32_jmptbl_57, @object
_nds32_jmptbl_57:
.word 0
.size _nds32_jmptbl_57, .-_nds32_jmptbl_57

32
libgcc/config/nds32/isr-library/jmptbl_vid58.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.58, "a"
.align 2
.weak _nds32_jmptbl_58
.type _nds32_jmptbl_58, @object
_nds32_jmptbl_58:
.word 0
.size _nds32_jmptbl_58, .-_nds32_jmptbl_58

32
libgcc/config/nds32/isr-library/jmptbl_vid59.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.59, "a"
.align 2
.weak _nds32_jmptbl_59
.type _nds32_jmptbl_59, @object
_nds32_jmptbl_59:
.word 0
.size _nds32_jmptbl_59, .-_nds32_jmptbl_59

32
libgcc/config/nds32/isr-library/jmptbl_vid60.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.60, "a"
.align 2
.weak _nds32_jmptbl_60
.type _nds32_jmptbl_60, @object
_nds32_jmptbl_60:
.word 0
.size _nds32_jmptbl_60, .-_nds32_jmptbl_60

32
libgcc/config/nds32/isr-library/jmptbl_vid61.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.61, "a"
.align 2
.weak _nds32_jmptbl_61
.type _nds32_jmptbl_61, @object
_nds32_jmptbl_61:
.word 0
.size _nds32_jmptbl_61, .-_nds32_jmptbl_61

32
libgcc/config/nds32/isr-library/jmptbl_vid62.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.62, "a"
.align 2
.weak _nds32_jmptbl_62
.type _nds32_jmptbl_62, @object
_nds32_jmptbl_62:
.word 0
.size _nds32_jmptbl_62, .-_nds32_jmptbl_62

32
libgcc/config/nds32/isr-library/jmptbl_vid63.S Normal file
View File

@ -0,0 +1,32 @@
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2013 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.63, "a"
.align 2
.weak _nds32_jmptbl_63
.type _nds32_jmptbl_63, @object
_nds32_jmptbl_63:
.word 0
.size _nds32_jmptbl_63, .-_nds32_jmptbl_63

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