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aarch64: Add support for unpacked SVE ABD
This patch adds support for unpacked SVE SABD and UABD. It also rewrites the patterns so that they match as combine patterns without the need for REG_EQUAL notes. Finally, there was no pattern for merging with the second input, which can be handled by reversing the operands. The type suffix needs to be taken from the element size rather than the container size. gcc/ * config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Extend from SVE_FULL_I to SVE_I. (*aarch64_cond_<su>abd<mode>_2): Likewise. (*aarch64_cond_<su>abd<mode>_any): Likewise. (@aarch64_pred_<su>abd<mode>): Likewise. Use UNSPEC_PRED_X for the max and min but not for the minus. (*aarch64_cond_<su>abd<mode>_3): New pattern. gcc/testsuite/ * g++.target/aarch64/sve/abd_1.C: New test. * g++.target/aarch64/sve/cond_abd_1.C: Likewise. * g++.target/aarch64/sve/cond_abd_2.C: Likewise. * g++.target/aarch64/sve/cond_abd_3.C: Likewise. * g++.target/aarch64/sve/cond_abd_4.C: Likewise.
This commit is contained in:
Richard Sandiford
parent
3f8b0bba03
commit
907ea37955
@ -3973,10 +3973,10 @@
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;; Unpredicated integer absolute difference.
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(define_expand "<su>abd<mode>_3"
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[(use (match_operand:SVE_FULL_I 0 "register_operand"))
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(USMAX:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand")
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(match_operand:SVE_FULL_I 2 "register_operand"))]
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[(use (match_operand:SVE_I 0 "register_operand"))
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(USMAX:SVE_I
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(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "register_operand"))]
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"TARGET_SVE"
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{
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rtx pred = aarch64_ptrue_reg (<VPRED>mode);
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@ -3988,17 +3988,20 @@
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;; Predicated integer absolute difference.
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(define_insn "@aarch64_pred_<su>abd<mode>"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(minus:SVE_FULL_I
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(USMAX:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "%0, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(<max_opp>:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(minus:SVE_I
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(USMAX:SVE_I
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(match_operand:SVE_I 2 "register_operand" "%0, w")
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(match_operand:SVE_I 3 "register_operand" "w, w"))]
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UNSPEC_PRED_X)
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(unspec:SVE_I
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[(match_dup 1)
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(<max_opp>:SVE_I
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(match_dup 2)
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(match_dup 3)))]
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UNSPEC_PRED_X))]
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(match_dup 3))]
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UNSPEC_PRED_X)))]
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"TARGET_SVE"
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"@
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<su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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@ -4033,19 +4036,19 @@
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;; Predicated integer absolute difference, merging with the first input.
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(define_insn_and_rewrite "*aarch64_cond_<su>abd<mode>_2"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(minus:SVE_FULL_I
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(unspec:SVE_FULL_I
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(minus:SVE_I
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(unspec:SVE_I
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[(match_operand 4)
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(USMAX:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "0, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))]
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(USMAX:SVE_I
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(match_operand:SVE_I 2 "register_operand" "0, w")
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(match_operand:SVE_I 3 "register_operand" "w, w"))]
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UNSPEC_PRED_X)
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(unspec:SVE_FULL_I
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(unspec:SVE_I
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[(match_operand 5)
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(<max_opp>:SVE_FULL_I
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(<max_opp>:SVE_I
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(match_dup 2)
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(match_dup 3))]
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UNSPEC_PRED_X))
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@ -4062,25 +4065,56 @@
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[(set_attr "movprfx" "*,yes")]
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)
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;; Predicated integer absolute difference, merging with an independent value.
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(define_insn_and_rewrite "*aarch64_cond_<su>abd<mode>_any"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, &w, ?&w")
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(unspec:SVE_FULL_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl")
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(minus:SVE_FULL_I
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(unspec:SVE_FULL_I
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[(match_operand 5)
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(USMAX:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "0, w, w, w, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, 0, w, w, w"))]
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;; Predicated integer absolute difference, merging with the second input.
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(define_insn_and_rewrite "*aarch64_cond_<su>abd<mode>_3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(minus:SVE_I
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(unspec:SVE_I
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[(match_operand 4)
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(USMAX:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, w")
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(match_operand:SVE_I 3 "register_operand" "0, w"))]
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UNSPEC_PRED_X)
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(unspec:SVE_FULL_I
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[(match_operand 6)
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(<max_opp>:SVE_FULL_I
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(unspec:SVE_I
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[(match_operand 5)
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(<max_opp>:SVE_I
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(match_dup 2)
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(match_dup 3))]
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UNSPEC_PRED_X))
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(match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")]
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(match_dup 3)]
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UNSPEC_SEL))]
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"TARGET_SVE"
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"@
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<su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>
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movprfx\t%0, %3\;<su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>"
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"&& (!CONSTANT_P (operands[4]) || !CONSTANT_P (operands[5]))"
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{
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operands[4] = operands[5] = CONSTM1_RTX (<VPRED>mode);
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}
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[(set_attr "movprfx" "*,yes")]
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)
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;; Predicated integer absolute difference, merging with an independent value.
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(define_insn_and_rewrite "*aarch64_cond_<su>abd<mode>_any"
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[(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, &w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl")
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(minus:SVE_I
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(unspec:SVE_I
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[(match_operand 5)
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(USMAX:SVE_I
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(match_operand:SVE_I 2 "register_operand" "0, w, w, w, w")
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(match_operand:SVE_I 3 "register_operand" "w, 0, w, w, w"))]
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UNSPEC_PRED_X)
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(unspec:SVE_I
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[(match_operand 6)
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(<max_opp>:SVE_I
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(match_dup 2)
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(match_dup 3))]
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UNSPEC_PRED_X))
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(match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")]
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UNSPEC_SEL))]
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"TARGET_SVE
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&& !rtx_equal_p (operands[2], operands[4])
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38
gcc/testsuite/g++.target/aarch64/sve/abd_1.C
Normal file
38
gcc/testsuite/g++.target/aarch64/sve/abd_1.C
Normal file
@ -0,0 +1,38 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b) \
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{ \
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return (a > b ? a : b) - (a < b ? a : b); \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (int8_t, 32)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (int8_t, 64)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (int16_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (int8_t, 128)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (int16_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (int32_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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60
gcc/testsuite/g++.target/aarch64/sve/cond_abd_1.C
Normal file
60
gcc/testsuite/g++.target/aarch64/sve/cond_abd_1.C
Normal file
@ -0,0 +1,60 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
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{ \
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return c == 0 ? (a > b ? a : b) - (a < b ? a : b) : a; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (int8_t, 32)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (int8_t, 64)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (int16_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (int8_t, 128)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (int16_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (int32_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x0\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tsabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tsabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tsabd\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x1\]\n[^L]*\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tsabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tsabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tsabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, \1\.s\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x0\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tuabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tuabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tuabd\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x1\]\n[^L]*\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tuabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tuabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tuabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, \1\.s\n} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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60
gcc/testsuite/g++.target/aarch64/sve/cond_abd_2.C
Normal file
60
gcc/testsuite/g++.target/aarch64/sve/cond_abd_2.C
Normal file
@ -0,0 +1,60 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
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{ \
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return c == 0 ? (a > b ? a : b) - (a < b ? a : b) : b; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
|
||||
typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
|
||||
TEST_OP (TYPE##SIZE)
|
||||
|
||||
TEST_TYPE (int8_t, 32)
|
||||
TEST_TYPE (uint8_t, 32)
|
||||
|
||||
TEST_TYPE (int8_t, 64)
|
||||
TEST_TYPE (uint8_t, 64)
|
||||
TEST_TYPE (int16_t, 64)
|
||||
TEST_TYPE (uint16_t, 64)
|
||||
|
||||
TEST_TYPE (int8_t, 128)
|
||||
TEST_TYPE (uint8_t, 128)
|
||||
TEST_TYPE (int16_t, 128)
|
||||
TEST_TYPE (uint16_t, 128)
|
||||
TEST_TYPE (int32_t, 128)
|
||||
TEST_TYPE (uint32_t, 128)
|
||||
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x1\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tsabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tsabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tsabd\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x0\]\n[^L]*\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tsabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tsabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tsabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, \1\.s\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x1\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x1\]\n[^L]*\tuabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tuabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x1\]\n[^L]*\tuabd\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x0\]\n[^L]*\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, \1\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x0\]\n[^L]*\tuabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tuabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, \1\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x0\]\n[^L]*\tuabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, \1\.s\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
49
gcc/testsuite/g++.target/aarch64/sve/cond_abd_3.C
Normal file
49
gcc/testsuite/g++.target/aarch64/sve/cond_abd_3.C
Normal file
@ -0,0 +1,49 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define TEST_OP(TYPE) \
|
||||
TYPE \
|
||||
test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
|
||||
{ \
|
||||
return c == 0 ? (a > b ? a : b) - (a < b ? a : b) : c; \
|
||||
}
|
||||
|
||||
#define TEST_TYPE(TYPE, SIZE) \
|
||||
typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
|
||||
TEST_OP (TYPE##SIZE)
|
||||
|
||||
TEST_TYPE (int8_t, 32)
|
||||
TEST_TYPE (uint8_t, 32)
|
||||
|
||||
TEST_TYPE (int8_t, 64)
|
||||
TEST_TYPE (uint8_t, 64)
|
||||
TEST_TYPE (int16_t, 64)
|
||||
TEST_TYPE (uint16_t, 64)
|
||||
|
||||
TEST_TYPE (int8_t, 128)
|
||||
TEST_TYPE (uint8_t, 128)
|
||||
TEST_TYPE (int16_t, 128)
|
||||
TEST_TYPE (uint16_t, 128)
|
||||
TEST_TYPE (int32_t, 128)
|
||||
TEST_TYPE (uint32_t, 128)
|
||||
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x2\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x2\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tsabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2\]\n[^L]*\tsabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tsabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tsabd\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x2\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x2\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tuabd\t\1\.b, p[0-7]/m, \1\.b, z[0-9]+\.b\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2\]\n[^L]*\tuabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tuabd\t\1\.h, p[0-7]/m, \1\.h, z[0-9]+\.h\n} } } */
|
||||
/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2\]\n[^L]*\tuabd\t\1\.s, p[0-7]/m, \1\.s, z[0-9]+\.s\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
43
gcc/testsuite/g++.target/aarch64/sve/cond_abd_4.C
Normal file
43
gcc/testsuite/g++.target/aarch64/sve/cond_abd_4.C
Normal file
@ -0,0 +1,43 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define TEST_OP(TYPE) \
|
||||
TYPE \
|
||||
test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c) \
|
||||
{ \
|
||||
return c == 1 ? (a > b ? a : b) - (a < b ? a : b) : 0; \
|
||||
}
|
||||
|
||||
#define TEST_TYPE(TYPE, SIZE) \
|
||||
typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
|
||||
TEST_OP (TYPE##SIZE)
|
||||
|
||||
TEST_TYPE (int8_t, 32)
|
||||
TEST_TYPE (uint8_t, 32)
|
||||
|
||||
TEST_TYPE (int8_t, 64)
|
||||
TEST_TYPE (uint8_t, 64)
|
||||
TEST_TYPE (int16_t, 64)
|
||||
TEST_TYPE (uint16_t, 64)
|
||||
|
||||
TEST_TYPE (int8_t, 128)
|
||||
TEST_TYPE (uint8_t, 128)
|
||||
TEST_TYPE (int16_t, 128)
|
||||
TEST_TYPE (uint16_t, 128)
|
||||
TEST_TYPE (int32_t, 128)
|
||||
TEST_TYPE (uint32_t, 128)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z, z[0-9]+\.b\n} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
Loading…
Reference in New Issue
Block a user