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LoongArch: testsuite: Fix gcc.dg/vect/vect-reduc-mul_{1, 2}.c FAIL.
This FAIL was introduced from r14-6908. The reason is that when merging constant vector permutation implementations, the 128-bit matching situation was not fully considered. In fact, the expansion of 128-bit vectors after merging only supports value-based 4 elements set shuffle, so this time is a complete implementation of the entire 128-bit vector constant permutation, and some structural adjustments have also been made to the code. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust. (loongarch_expand_vselect_vconcat): Ditto. (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement all 128-bit constant permutation situations. (loongarch_expand_lsx_shuffle): Adjust and rename function name. (loongarch_is_imm_set_shuffle): Renamed function name. (loongarch_expand_vec_perm_even_odd): Function forward declaration. (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit extract-even and extract-odd permutations. (loongarch_is_odd_extraction): Delete. (loongarch_is_even_extraction): Ditto. (loongarch_expand_vec_perm_const): Adjust.
This commit is contained in:
Li Wei
Lulu Cheng
parent
2ada8bc53e
commit
8e6ebacc9e
@ -8029,7 +8029,8 @@ struct expand_vec_perm_d
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static bool
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loongarch_expand_vselect (rtx target, rtx op0,
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const unsigned char *perm, unsigned nelt)
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const unsigned char *perm, unsigned nelt,
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bool testing_p)
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{
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rtx rperm[MAX_VECT_LEN], x;
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rtx_insn *insn;
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@ -8048,6 +8049,9 @@ loongarch_expand_vselect (rtx target, rtx op0,
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remove_insn (insn);
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return false;
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}
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if (testing_p)
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remove_insn (insn);
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return true;
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}
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@ -8055,7 +8059,8 @@ loongarch_expand_vselect (rtx target, rtx op0,
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static bool
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loongarch_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
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const unsigned char *perm, unsigned nelt)
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const unsigned char *perm, unsigned nelt,
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bool testing_p)
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{
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machine_mode v2mode;
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rtx x;
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@ -8063,7 +8068,7 @@ loongarch_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
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if (!GET_MODE_2XWIDER_MODE (GET_MODE (op0)).exists (&v2mode))
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return false;
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x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
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return loongarch_expand_vselect (target, x, perm, nelt);
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return loongarch_expand_vselect (target, x, perm, nelt, testing_p);
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}
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static tree
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@ -8317,11 +8322,87 @@ loongarch_set_handled_components (sbitmap components)
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#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
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#undef TARGET_ASM_ALIGNED_DI_OP
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#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
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/* Construct (set target (vec_select op0 (parallel selector))) and
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return true if that's a valid instruction in the active ISA. */
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/* Use the vshuf instruction to implement all 128-bit constant vector
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permuatation. */
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static bool
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loongarch_expand_lsx_shuffle (struct expand_vec_perm_d *d)
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loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d)
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{
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int i;
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rtx target, op0, op1, sel, tmp;
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rtx rperm[MAX_VECT_LEN];
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if (GET_MODE_SIZE (d->vmode) == 16)
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{
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target = d->target;
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op0 = d->op0;
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op1 = d->one_vector_p ? d->op0 : d->op1;
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if (GET_MODE (op0) != GET_MODE (op1)
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|| GET_MODE (op0) != GET_MODE (target))
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return false;
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if (d->testing_p)
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return true;
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for (i = 0; i < d->nelt; i += 1)
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rperm[i] = GEN_INT (d->perm[i]);
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if (d->vmode == E_V2DFmode)
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{
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sel = gen_rtx_CONST_VECTOR (E_V2DImode, gen_rtvec_v (d->nelt, rperm));
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tmp = simplify_gen_subreg (E_V2DImode, d->target, d->vmode, 0);
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emit_move_insn (tmp, sel);
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}
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else if (d->vmode == E_V4SFmode)
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{
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sel = gen_rtx_CONST_VECTOR (E_V4SImode, gen_rtvec_v (d->nelt, rperm));
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tmp = simplify_gen_subreg (E_V4SImode, d->target, d->vmode, 0);
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emit_move_insn (tmp, sel);
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}
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else
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{
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sel = gen_rtx_CONST_VECTOR (d->vmode, gen_rtvec_v (d->nelt, rperm));
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emit_move_insn (d->target, sel);
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}
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switch (d->vmode)
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{
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case E_V2DFmode:
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emit_insn (gen_lsx_vshuf_d_f (target, target, op1, op0));
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break;
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case E_V2DImode:
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emit_insn (gen_lsx_vshuf_d (target, target, op1, op0));
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break;
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case E_V4SFmode:
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emit_insn (gen_lsx_vshuf_w_f (target, target, op1, op0));
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break;
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case E_V4SImode:
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emit_insn (gen_lsx_vshuf_w (target, target, op1, op0));
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break;
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case E_V8HImode:
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emit_insn (gen_lsx_vshuf_h (target, target, op1, op0));
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break;
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case E_V16QImode:
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emit_insn (gen_lsx_vshuf_b (target, op1, op0, target));
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break;
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default:
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break;
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}
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return true;
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}
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return false;
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}
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/* Construct (set target (vec_select op0 (parallel selector))) and
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return true if that's a valid instruction in the active ISA.
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In fact, it matches the special constant vector with repeated
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4-element sets. */
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static bool
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loongarch_is_imm_set_shuffle (struct expand_vec_perm_d *d)
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{
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rtx x, elts[MAX_VECT_LEN];
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rtvec v;
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@ -8340,6 +8421,9 @@ loongarch_expand_lsx_shuffle (struct expand_vec_perm_d *d)
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if (!loongarch_const_vector_shuffle_set_p (x, d->vmode))
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return false;
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if (d->testing_p)
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return true;
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x = gen_rtx_VEC_SELECT (d->vmode, d->op0, x);
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x = gen_rtx_SET (d->target, x);
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@ -8352,6 +8436,27 @@ loongarch_expand_lsx_shuffle (struct expand_vec_perm_d *d)
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return true;
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}
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static bool
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loongarch_expand_vec_perm_even_odd (struct expand_vec_perm_d *);
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/* Try to match and expand all kinds of 128-bit const vector permutation
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cases. */
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static bool
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loongarch_expand_lsx_shuffle (struct expand_vec_perm_d *d)
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{
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if (!ISA_HAS_LSX && GET_MODE_SIZE (d->vmode) != 16)
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return false;
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if (loongarch_is_imm_set_shuffle (d))
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return true;
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if (loongarch_expand_vec_perm_even_odd (d))
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return true;
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return loongarch_try_expand_lsx_vshuf_const (d);
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}
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/* Try to simplify a two vector permutation using 2 intra-lane interleave
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insns and cross-lane shuffle for 32-byte vectors. */
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@ -8444,7 +8549,7 @@ loongarch_expand_vec_perm_interleave (struct expand_vec_perm_d *d)
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return true;
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}
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/* Implement extract-even and extract-odd permutations. */
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/* Implement 128-bit and 256-bit extract-even and extract-odd permutations. */
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static bool
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loongarch_expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd)
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@ -8459,6 +8564,50 @@ loongarch_expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd)
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switch (d->vmode)
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{
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/* 128 bit. */
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case E_V2DFmode:
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if (odd)
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emit_insn (gen_lsx_vilvh_d_f (d->target, d->op0, d->op1));
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else
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emit_insn (gen_lsx_vilvl_d_f (d->target, d->op0, d->op1));
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break;
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case E_V2DImode:
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if (odd)
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emit_insn (gen_lsx_vilvh_d (d->target, d->op0, d->op1));
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else
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emit_insn (gen_lsx_vilvl_d (d->target, d->op0, d->op1));
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break;
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case E_V4SFmode:
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if (odd)
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emit_insn (gen_lsx_vpickod_w_f (d->target, d->op0, d->op1));
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else
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emit_insn (gen_lsx_vpickev_w_f (d->target, d->op0, d->op1));
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break;
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case E_V4SImode:
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if (odd)
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emit_insn (gen_lsx_vpickod_w (d->target, d->op0, d->op1));
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else
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emit_insn (gen_lsx_vpickev_w (d->target, d->op0, d->op1));
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break;
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case E_V8HImode:
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if (odd)
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emit_insn (gen_lsx_vpickod_h (d->target, d->op0, d->op1));
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else
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emit_insn (gen_lsx_vpickev_h (d->target, d->op0, d->op1));
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break;
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case E_V16QImode:
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if (odd)
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emit_insn (gen_lsx_vpickod_b (d->target, d->op0, d->op1));
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else
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emit_insn (gen_lsx_vpickev_b (d->target, d->op0, d->op1));
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break;
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/* 256 bit. */
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case E_V4DFmode:
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/* Shuffle the lanes around into { 0 4 2 6 } and { 1 5 3 7 }. */
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if (odd)
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@ -8533,7 +8682,7 @@ static bool
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loongarch_expand_vec_perm_even_odd (struct expand_vec_perm_d *d)
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{
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unsigned i, odd, nelt = d->nelt;
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if (!ISA_HAS_LASX)
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if (!ISA_HAS_LASX && !ISA_HAS_LSX)
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return false;
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odd = d->perm[0];
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@ -8996,44 +9145,6 @@ loongarch_is_quad_duplicate (struct expand_vec_perm_d *d)
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return result;
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}
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static bool
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loongarch_is_odd_extraction (struct expand_vec_perm_d *d)
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{
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bool result = true;
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unsigned char buf = 1;
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for (int i = 0; i < d->nelt; i += 1)
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{
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if (buf != d->perm[i])
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{
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result = false;
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break;
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}
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buf += 2;
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}
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return result;
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}
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static bool
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loongarch_is_even_extraction (struct expand_vec_perm_d *d)
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{
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bool result = true;
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unsigned char buf = 0;
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for (int i = 0; i < d->nelt; i += 1)
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{
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if (buf != d->perm[i])
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{
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result = false;
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break;
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}
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buf += 2;
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}
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return result;
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}
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static bool
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loongarch_is_extraction_permutation (struct expand_vec_perm_d *d)
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{
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@ -9290,32 +9401,29 @@ loongarch_expand_vec_perm_const (struct expand_vec_perm_d *d)
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for (i = 1; i < d->nelt; i += 2)
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perm2[i] += d->nelt;
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if (loongarch_expand_vselect_vconcat (d->target, d->op0, d->op1,
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perm2, d->nelt))
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perm2, d->nelt, d->testing_p))
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return true;
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}
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else
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{
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if (loongarch_expand_vselect_vconcat (d->target, d->op0, d->op1,
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d->perm, d->nelt))
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d->perm, d->nelt,
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d->testing_p))
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return true;
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/* Try again with swapped operands. */
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for (i = 0; i < d->nelt; ++i)
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perm2[i] = (d->perm[i] + d->nelt) & (2 * d->nelt - 1);
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if (loongarch_expand_vselect_vconcat (d->target, d->op1, d->op0,
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perm2, d->nelt))
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perm2, d->nelt, d->testing_p))
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return true;
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}
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if (loongarch_expand_lsx_shuffle (d))
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if (loongarch_is_imm_set_shuffle (d))
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return true;
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if (loongarch_is_odd_extraction (d)
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|| loongarch_is_even_extraction (d))
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{
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if (loongarch_expand_vec_perm_even_odd (d))
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return true;
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}
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if (loongarch_expand_vec_perm_even_odd (d))
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return true;
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if (loongarch_is_lasx_lowpart_interleave (d)
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|| loongarch_is_lasx_lowpart_interleave_2 (d)
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