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AVR: target/117726 - Better optimizations of ASHIFT:SI insns.
This patch improves the 4-byte ASHIFT insns. 1) It adds a "r,r,C15" alternative for improved long << 15. 2) It adds 3-operand alternatives (depending on options) and splits them after peephole2 / before avr-fuse-move into a 3-operand byte shift and a 2-operand residual bit shift. For better control, it introduces new option -msplit-bit-shift that's activated at -O2 and higher per default. 2) is even performed with -Os, but not with -Oz. PR target/117726 gcc/ * config/avr/avr.opt (-msplit-bit-shift): Add new optimization option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_2_PLUS]: Turn on -msplit-bit-shift. * config/avr/avr.h (machine_function.n_avr_fuse_add_executed): New bool component. * config/avr/avr.md (attr "isa") <2op, 3op>: Add new values. (attr "enabled"): Handle them. (ashlsi3, *ashlsi3, *ashlsi3_const): Add "r,r,C15" alternative. Add "r,0,C4l" and "r,r,C4l" alternatives (depending on 2op / 3op). (define_split) [avr_split_bit_shift]: Add 2 new ashift:ALL4 splitters. (define_peephole2) [ashift:ALL4]: Add (match_dup 3) so that the scratch won't overlap with the output operand of the matched insn. (*ashl<mode>3_const_split): Remove unused ashift:ALL4 splitter. * config/avr/avr-passes.cc (emit_valid_insn) (emit_valid_move_clobbercc): Move out of anonymous namespace. (make_avr_pass_fuse_add) <gate>: Don't override. <execute>: Set n_avr_fuse_add_executed according to func->machine->n_avr_fuse_add_executed. (pass_data avr_pass_data_split_after_peephole2): New object. (avr_pass_split_after_peephole2): New rtl_opt_pass. (avr_emit_shift): New static function. (avr_shift_is_3op, avr_split_shift_p, avr_split_shift) (make_avr_pass_split_after_peephole2): New functions. * config/avr/avr-passes.def (avr_pass_split_after_peephole2): Insert new pass after pass_peephole2. * config/avr/avr-protos.h (n_avr_fuse_add_executed, avr_shift_is_3op, avr_split_shift_p) (avr_split_shift, avr_optimize_size_level) (make_avr_pass_split_after_peephole2): New prototypes. * config/avr/avr.cc (n_avr_fuse_add_executed): New global variable. (avr_optimize_size_level): New function. (avr_set_current_function): Set n_avr_fuse_add_executed according to cfun->machine->n_avr_fuse_add_executed. (ashlsi3_out) [case 15]: Output optimized code for this offset. (avr_rtx_costs_1) [ASHIFT, SImode]: Adjust costs of oggsets 15, 16. * config/avr/constraints.md (C4a, C4r, C4r): New constraints. * pass_manager.h (pass_manager): Adjust comments.
This commit is contained in:
Georg-Johann Lay
parent
938094abec
commit
873cffc792
@ -39,6 +39,7 @@ static const struct default_options avr_option_optimization_table[] =
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{ OPT_LEVELS_2_PLUS, OPT_mfuse_add_, NULL, 2 },
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{ OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_mfuse_move_, NULL, 3 },
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{ OPT_LEVELS_2_PLUS, OPT_mfuse_move_, NULL, 23 },
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{ OPT_LEVELS_2_PLUS, OPT_msplit_bit_shift, NULL, 1 },
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// Stick to the "old" placement of the subreg lowering pass.
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{ OPT_LEVELS_1_PLUS, OPT_fsplit_wide_types_early, NULL, 1 },
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/* Allow optimizer to introduce store data races. This used to be the
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@ -49,6 +49,34 @@
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#define FIRST_GPR (AVR_TINY ? REG_18 : REG_2)
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// Emit pattern PAT, and ICE when the insn is not valid / not recognized.
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static rtx_insn *
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emit_valid_insn (rtx pat)
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{
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rtx_insn *insn = emit_insn (pat);
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if (! valid_insn_p (insn)) // Also runs recog().
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fatal_insn ("emit unrecognizable insn", insn);
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return insn;
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}
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// Emit a single_set with an optional scratch operand. This function
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// asserts that the new insn is valid and recognized.
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static rtx_insn *
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emit_valid_move_clobbercc (rtx dest, rtx src, rtx scratch = NULL_RTX)
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{
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rtx pat = scratch
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? gen_gen_move_clobbercc_scratch (dest, src, scratch)
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: gen_gen_move_clobbercc (dest, src);
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return emit_valid_insn (pat);
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}
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namespace
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{
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@ -116,31 +144,6 @@ single_set_with_scratch (rtx_insn *insn, int ®no_scratch)
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return single_set (insn);
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}
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// Emit pattern PAT, and ICE when the insn is not valid / not recognized.
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static rtx_insn *
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emit_valid_insn (rtx pat)
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{
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rtx_insn *insn = emit_insn (pat);
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if (! valid_insn_p (insn)) // Also runs recog().
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fatal_insn ("emit unrecognizable insn", insn);
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return insn;
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}
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// Emit a single_set with an optional scratch operand. This function
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// asserts that the new insn is valid and recognized.
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static rtx_insn *
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emit_valid_move_clobbercc (rtx dest, rtx src, rtx scratch = NULL_RTX)
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{
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rtx pat = scratch
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? gen_gen_move_clobbercc_scratch (dest, src, scratch)
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: gen_gen_move_clobbercc (dest, src);
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return emit_valid_insn (pat);
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}
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// One bit for each GRP in REG_0 ... REG_31.
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using gprmask_t = uint32_t;
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@ -4213,12 +4216,17 @@ public:
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return make_avr_pass_fuse_add (m_ctxt);
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}
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bool gate (function *) final override
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unsigned int execute (function *func) final override
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{
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return optimize && avr_fuse_add > 0;
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func->machine->n_avr_fuse_add_executed += 1;
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n_avr_fuse_add_executed = func->machine->n_avr_fuse_add_executed;
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if (optimize && avr_fuse_add > 0)
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return execute1 (func);
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return 0;
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}
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unsigned int execute (function *) final override;
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unsigned int execute1 (function *);
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struct Some_Insn
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{
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@ -4697,7 +4705,7 @@ avr_pass_fuse_add::fuse_mem_add (Mem_Insn &mem, Add_Insn &add)
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as PRE_DEC + PRE_DEC for two adjacent locations. */
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unsigned int
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avr_pass_fuse_add::execute (function *func)
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avr_pass_fuse_add::execute1 (function *func)
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{
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df_note_add_problem ();
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df_analyze ();
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@ -4769,6 +4777,146 @@ avr_pass_fuse_add::execute (function *func)
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}
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//////////////////////////////////////////////////////////////////////////////
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// Split insns after peephole2 / befor avr-fuse-move.
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static const pass_data avr_pass_data_split_after_peephole2 =
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{
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RTL_PASS, // type
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"", // name (will be patched)
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OPTGROUP_NONE, // optinfo_flags
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TV_DF_SCAN, // tv_id
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0, // properties_required
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0, // properties_provided
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0, // properties_destroyed
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0, // todo_flags_start
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0 // todo_flags_finish
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};
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class avr_pass_split_after_peephole2 : public rtl_opt_pass
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{
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public:
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avr_pass_split_after_peephole2 (gcc::context *ctxt, const char *name)
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: rtl_opt_pass (avr_pass_data_split_after_peephole2, ctxt)
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{
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this->name = name;
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}
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unsigned int execute (function *) final override
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{
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if (avr_shift_is_3op ())
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split_all_insns ();
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return 0;
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}
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}; // avr_pass_split_after_peephole2
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} // anonymous namespace
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/* Whether some shift insn alternatives are a 3-operand insn or a
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2-operand insn. This 3op alternatives allow the source and the
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destination register of the shift to be different right from the
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start, because the splitter will split the 3op shift into a 3op byte
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shift and a 2op residual bit shift.
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(When the residual shift has an offset of one less than the bitsize,
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then the residual shift is also a 3op insn. */
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bool
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avr_shift_is_3op ()
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{
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// Don't split for OPTIMIZE_SIZE_MAX (-Oz).
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// For OPTIMIZE_SIZE_BALANCED (-Os), we still split because
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// the size overhead (if exists at all) is marginal.
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return (avr_split_bit_shift
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&& optimize > 0
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&& avr_optimize_size_level () < OPTIMIZE_SIZE_MAX);
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}
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/* Implement constraints `C4a', `C4l' and `C4r'.
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Whether we split an N_BYTES shift of code CODE in { ASHIFTRT,
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LSHIFTRT, ASHIFT } into a byte shift and a residual bit shift. */
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bool
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avr_split_shift_p (int n_bytes, int offset, rtx_code)
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{
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gcc_assert (n_bytes == 4);
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return (avr_shift_is_3op ()
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&& offset % 8 != 0 && IN_RANGE (offset, 17, 30));
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}
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static void
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avr_emit_shift (rtx_code code, rtx dest, rtx src, int off, rtx scratch)
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{
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machine_mode mode = GET_MODE (dest);
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rtx shift;
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if (off == GET_MODE_BITSIZE (mode) - 1)
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{
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shift = gen_rtx_fmt_ee (code, mode, src, GEN_INT (off));
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}
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else
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{
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if (REGNO (dest) != REGNO (src))
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emit_valid_move_clobbercc (dest, src);
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shift = gen_rtx_fmt_ee (code, mode, dest, GEN_INT (off));
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}
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emit_valid_move_clobbercc (dest, shift, scratch);
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}
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/* Worker for define_split that run when -msplit-bit-shift is on.
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Split a shift of code CODE into a 3op byte shift and a residual bit shift.
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Return 'true' when a split has been performed and insns have been emitted.
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Otherwise, return 'false'. */
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bool
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avr_split_shift (rtx xop[], rtx scratch, rtx_code code)
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{
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scratch = scratch && REG_P (scratch) ? scratch : NULL_RTX;
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rtx dest = xop[0];
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rtx src = xop[1];
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int ioff = INTVAL (xop[2]);
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gcc_assert (GET_MODE_SIZE (GET_MODE (dest)) == 4);
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if (code == ASHIFT)
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{
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if (ioff >= 25)
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{
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rtx dst8 = avr_byte (dest, 3);
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rtx src8 = avr_byte (src, 0);
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avr_emit_shift (code, dst8, src8, ioff % 8, NULL_RTX);
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emit_valid_move_clobbercc (avr_byte (dest, 2), const0_rtx);
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emit_valid_move_clobbercc (avr_word (dest, 0), const0_rtx);
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return true;
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}
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else if (ioff >= 17)
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{
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rtx dst16 = avr_word (dest, 2);
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rtx src16 = avr_word (src, 0);
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avr_emit_shift (code, dst16, src16, ioff % 16, scratch);
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emit_valid_move_clobbercc (avr_word (dest, 0), const0_rtx);
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return true;
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}
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else
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gcc_unreachable ();
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}
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else
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gcc_unreachable ();
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return false;
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}
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namespace
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{
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//////////////////////////////////////////////////////////////////////////////
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// Determine whether an ISR may use the __gcc_isr pseudo-instruction.
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@ -5125,3 +5273,11 @@ make_avr_pass_fuse_move (gcc::context *ctxt)
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{
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return new avr_pass_fuse_move (ctxt, "avr-fuse-move");
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}
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// Split insns after peephole2 / befor avr-fuse-move.
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rtl_opt_pass *
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make_avr_pass_split_after_peephole2 (gcc::context *ctxt)
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{
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return new avr_pass_split_after_peephole2 (ctxt, "avr-split-after-peephole2");
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}
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@ -104,3 +104,10 @@ INSERT_PASS_BEFORE (pass_split_after_reload, 1, avr_pass_ifelse);
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- The RTL peepholer may optimize insns involving lower registers. */
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INSERT_PASS_AFTER (pass_peephole2, 1, avr_pass_fuse_move);
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/* Run an instance of post-reload split prior to avr-fuse-move.
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Purpose is to split 3-operand shift insns into a 3-operand shift
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with a byte offset, and a 2-operand residual shift after
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RTL peepholes but prior to the avr-fuse-move pass. */
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INSERT_PASS_AFTER (pass_peephole2, 1, avr_pass_split_after_peephole2);
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@ -169,6 +169,13 @@ extern rtx cc_reg_rtx;
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extern rtx ccn_reg_rtx;
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extern rtx cczn_reg_rtx;
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extern int n_avr_fuse_add_executed;
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extern bool avr_shift_is_3op ();
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extern bool avr_split_shift_p (int n_bytes, int offset, rtx_code);
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extern bool avr_split_shift (rtx xop[], rtx xscratch, rtx_code);
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extern int avr_optimize_size_level ();
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#endif /* RTX_CODE */
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#ifdef REAL_VALUE_TYPE
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@ -188,6 +195,7 @@ extern rtl_opt_pass *make_avr_pass_pre_proep (gcc::context *);
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extern rtl_opt_pass *make_avr_pass_recompute_notes (gcc::context *);
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extern rtl_opt_pass *make_avr_pass_casesi (gcc::context *);
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extern rtl_opt_pass *make_avr_pass_ifelse (gcc::context *);
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extern rtl_opt_pass *make_avr_pass_split_after_peephole2 (gcc::context *);
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#ifdef RTX_CODE
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extern bool avr_casei_sequence_check_operands (rtx *xop);
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extern bool avr_split_fake_addressing_move (rtx_insn *insn, rtx *operands);
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@ -229,6 +229,12 @@ bool avr_need_clear_bss_p = false;
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bool avr_need_copy_data_p = false;
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bool avr_has_rodata_p = false;
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/* Counts how often pass avr-fuse-add has been executed. Is is kept in
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sync with cfun->machine->n_avr_fuse_add_executed and serves as an
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insn condition for shift insn splitters. */
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int n_avr_fuse_add_executed = 0;
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/* Transform UP into lowercase and write the result to LO.
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You must provide enough space for LO. Return LO. */
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@ -526,6 +532,14 @@ avr_option_override (void)
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}
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int avr_optimize_size_level ()
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{
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return cfun && cfun->decl
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? opt_for_fn (cfun->decl, optimize_size)
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: optimize_size;
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}
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/* Implement `INIT_EXPANDERS'. */
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/* The function works like a singleton. */
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@ -823,8 +837,12 @@ avr_set_current_function (tree decl)
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if (decl == NULL_TREE
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|| current_function_decl == NULL_TREE
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|| current_function_decl == error_mark_node
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|| ! cfun->machine
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|| cfun->machine->attributes_checked_p)
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|| ! cfun->machine)
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return;
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n_avr_fuse_add_executed = cfun->machine->n_avr_fuse_add_executed;
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if (cfun->machine->attributes_checked_p)
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return;
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location_t loc = DECL_SOURCE_LOCATION (decl);
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@ -6590,7 +6608,7 @@ avr_out_cmp_ext (rtx xop[], rtx_code code, int *plen)
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/* Generate asm equivalent for various shifts. This only handles cases
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that are not already carefully hand-optimized in ?sh??i3_out.
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that are not already carefully hand-optimized in ?sh<mode>3_out.
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OPERANDS[0] resp. %0 in TEMPL is the operand to be shifted.
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OPERANDS[2] is the shift count as CONST_INT, MEM or REG.
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@ -7042,6 +7060,7 @@ ashlsi3_out (rtx_insn *insn, rtx operands[], int *plen)
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{
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int reg0 = true_regnum (operands[0]);
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int reg1 = true_regnum (operands[1]);
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bool reg1_unused_after_p = reg_unused_after (insn, operands[1]);
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if (plen)
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*plen = 0;
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@ -7070,6 +7089,30 @@ ashlsi3_out (rtx_insn *insn, rtx operands[], int *plen)
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"mov %B0,%A1" CR_TAB
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"mov %C0,%B1" CR_TAB
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"mov %D0,%C1", operands, plen, 4);
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case 15:
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avr_asm_len (reg1_unused_after_p
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? "lsr %C1"
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: "bst %C1,0", operands, plen, 1);
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if (reg0 + 2 != reg1)
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{
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if (AVR_HAVE_MOVW)
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avr_asm_len ("movw %C0,%A1", operands, plen, 1);
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else
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avr_asm_len ("mov %C0,%A1" CR_TAB
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"mov %D0,%B1", operands, plen, 2);
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}
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return reg1_unused_after_p
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? avr_asm_len ("clr %A0" CR_TAB
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"clr %B0" CR_TAB
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"ror %D0" CR_TAB
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"ror %C0" CR_TAB
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"ror %B0", operands, plen, 5)
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: avr_asm_len ("clr %A0" CR_TAB
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"clr %B0" CR_TAB
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"lsr %D0" CR_TAB
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"ror %C0" CR_TAB
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"ror %B0" CR_TAB
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"bld %D0,7", operands, plen, 6);
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case 16:
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if (reg0 + 2 == reg1)
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return avr_asm_len ("clr %B0" CR_TAB
|
||||
@ -12392,9 +12435,14 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
|
||||
break;
|
||||
case 1:
|
||||
case 8:
|
||||
case 16:
|
||||
*total = COSTS_N_INSNS (4);
|
||||
break;
|
||||
case 15:
|
||||
*total = COSTS_N_INSNS (8 - AVR_HAVE_MOVW);
|
||||
break;
|
||||
case 16:
|
||||
*total = COSTS_N_INSNS (4 - AVR_HAVE_MOVW);
|
||||
break;
|
||||
case 31:
|
||||
*total = COSTS_N_INSNS (6);
|
||||
break;
|
||||
|
||||
@ -610,6 +610,12 @@ struct GTY(()) machine_function
|
||||
/* 'true' if this function references .L__stack_usage like with
|
||||
__builtin_return_address. */
|
||||
bool use_L__stack_usage;
|
||||
|
||||
/* Counts how many times the execute() method of the avr-fuse-add
|
||||
has been invoked. The count is even increased when the optimization
|
||||
itself is not run. This purpose of this variable is to provide
|
||||
information about where in the pass sequence we are. */
|
||||
int n_avr_fuse_add_executed;
|
||||
};
|
||||
|
||||
/* AVR does not round pushes, but the existence of this macro is
|
||||
|
||||
@ -184,73 +184,75 @@
|
||||
;; no_xmega: non-XMEGA core xmega : XMEGA core
|
||||
;; no_adiw: ISA has no ADIW, SBIW adiw : ISA has ADIW, SBIW
|
||||
|
||||
;; The following ISA attributes are actually not architecture specific,
|
||||
;; but depend on (optimization) options. This is because the "enabled"
|
||||
;; attribut can't depend on more than one other attribute. This means
|
||||
;; that 2op and 3op must work for all ISAs, and hence a 'flat' attribue
|
||||
;; scheme can be used (as opposed to a true cartesian product).
|
||||
|
||||
;; 2op : insn is a 2-operand insn 3op : insn is a 3-operand insn
|
||||
|
||||
(define_attr "isa"
|
||||
"mov,movw, rjmp,jmp, ijmp,eijmp, lpm,lpmx, elpm,elpmx, no_xmega,xmega,
|
||||
no_adiw,adiw,
|
||||
2op,3op,
|
||||
standard"
|
||||
(const_string "standard"))
|
||||
|
||||
(define_attr "enabled" ""
|
||||
(cond [(eq_attr "isa" "standard")
|
||||
(const_int 1)
|
||||
(if_then_else
|
||||
(ior (eq_attr "isa" "standard")
|
||||
|
||||
(and (eq_attr "isa" "mov")
|
||||
(match_test "!AVR_HAVE_MOVW"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "movw")
|
||||
(match_test "AVR_HAVE_MOVW"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "rjmp")
|
||||
(match_test "!AVR_HAVE_JMP_CALL"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "jmp")
|
||||
(match_test "AVR_HAVE_JMP_CALL"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "ijmp")
|
||||
(match_test "!AVR_HAVE_EIJMP_EICALL"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "eijmp")
|
||||
(match_test "AVR_HAVE_EIJMP_EICALL"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "lpm")
|
||||
(match_test "!AVR_HAVE_LPMX"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "lpmx")
|
||||
(match_test "AVR_HAVE_LPMX"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "elpm")
|
||||
(match_test "AVR_HAVE_ELPM && !AVR_HAVE_ELPMX"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "elpmx")
|
||||
(match_test "AVR_HAVE_ELPMX"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "xmega")
|
||||
(match_test "AVR_XMEGA"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "no_xmega")
|
||||
(match_test "!AVR_XMEGA"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "adiw")
|
||||
(match_test "AVR_HAVE_ADIW"))
|
||||
(const_int 1)
|
||||
|
||||
(and (eq_attr "isa" "no_adiw")
|
||||
(match_test "!AVR_HAVE_ADIW"))
|
||||
(const_int 1)
|
||||
|
||||
] (const_int 0)))
|
||||
(and (eq_attr "isa" "2op")
|
||||
(match_test "!avr_shift_is_3op ()"))
|
||||
|
||||
(and (eq_attr "isa" "3op")
|
||||
(match_test "avr_shift_is_3op ()"))
|
||||
)
|
||||
(const_int 1)
|
||||
(const_int 0)))
|
||||
|
||||
|
||||
;; Define mode iterators
|
||||
@ -5257,28 +5259,31 @@
|
||||
;; "ashlsq3" "ashlusq3"
|
||||
;; "ashlsa3" "ashlusa3"
|
||||
(define_insn_and_split "ashl<mode>3"
|
||||
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r ,r,r,r")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r ,0,0,0")
|
||||
(match_operand:QI 2 "nop_general_operand" "r,L,P,O C31,K,n,Qm")))]
|
||||
[(set (match_operand:ALL4 0 "register_operand" "=r,r ,r ,r ,r ,r,r")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,r ,0 ,r ,0,0")
|
||||
(match_operand:QI 2 "nop_general_operand" "r,LPK,O C15 C31,C4l,C4l,n,Qm")))]
|
||||
""
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(ashift:ALL4 (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC REG_CC))])])
|
||||
(clobber (reg:CC REG_CC))])]
|
||||
""
|
||||
[(set_attr "isa" "*,*,*,2op,3op,*,*")])
|
||||
|
||||
(define_insn "*ashl<mode>3"
|
||||
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r ,r,r,r")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r ,0,0,0")
|
||||
(match_operand:QI 2 "nop_general_operand" "r,L,P,O C31,K,n,Qm")))
|
||||
[(set (match_operand:ALL4 0 "register_operand" "=r,r ,r ,r ,r ,r,r")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,r ,0 ,r ,0,0")
|
||||
(match_operand:QI 2 "nop_general_operand" "r,LPK,O C15 C31,C4l,C4l,n,Qm")))
|
||||
(clobber (reg:CC REG_CC))]
|
||||
"reload_completed"
|
||||
{
|
||||
return ashlsi3_out (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "length" "8,0,4,5,8,10,12")
|
||||
(set_attr "adjust_len" "ashlsi")])
|
||||
[(set_attr "length" "12")
|
||||
(set_attr "adjust_len" "ashlsi")
|
||||
(set_attr "isa" "*,*,*,2op,3op,*,*")])
|
||||
|
||||
;; Optimize if a scratch register from LD_REGS happens to be available.
|
||||
|
||||
@ -5380,12 +5385,72 @@
|
||||
[(set_attr "length" "0,2,2,4,10")
|
||||
(set_attr "adjust_len" "ashlhi")])
|
||||
|
||||
|
||||
;; Split shift into a byte shift and a residual bit shift (without scratch)
|
||||
(define_split
|
||||
[(parallel [(set (match_operand:ALL4 0 "register_operand")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand")
|
||||
(match_operand:QI 2 "const_int_operand")))
|
||||
(clobber (reg:CC REG_CC))])]
|
||||
"avr_split_bit_shift
|
||||
&& n_avr_fuse_add_executed >= 1
|
||||
&& satisfies_constraint_C4l (operands[2])"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(ashift:ALL4 (match_dup 1)
|
||||
(match_dup 3)))
|
||||
(clobber (reg:CC REG_CC))])
|
||||
(parallel [(set (match_dup 0)
|
||||
(ashift:ALL4 (match_dup 0)
|
||||
(match_dup 4)))
|
||||
(clobber (reg:CC REG_CC))])]
|
||||
{
|
||||
if (avr_split_shift (operands, NULL_RTX, ASHIFT))
|
||||
DONE;
|
||||
else if (REGNO (operands[0]) == REGNO (operands[1]))
|
||||
FAIL;
|
||||
int offset = INTVAL (operands[2]);
|
||||
operands[3] = GEN_INT (offset & ~7);
|
||||
operands[4] = GEN_INT (offset & 7);
|
||||
})
|
||||
|
||||
;; Split shift into a byte shift and a residual bit shift (with scratch)
|
||||
(define_split
|
||||
[(parallel [(set (match_operand:ALL4 0 "register_operand")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand")
|
||||
(match_operand:QI 2 "const_int_operand")))
|
||||
(clobber (match_operand:QI 3 "scratch_or_d_register_operand"))
|
||||
(clobber (reg:CC REG_CC))])]
|
||||
"avr_split_bit_shift
|
||||
&& n_avr_fuse_add_executed >= 1
|
||||
&& satisfies_constraint_C4l (operands[2])"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(ashift:ALL4 (match_dup 1)
|
||||
(match_dup 4)))
|
||||
(clobber (reg:CC REG_CC))])
|
||||
(parallel [(set (match_dup 0)
|
||||
(ashift:ALL4 (match_dup 0)
|
||||
(match_dup 5)))
|
||||
(clobber (match_dup 3))
|
||||
(clobber (reg:CC REG_CC))])]
|
||||
{
|
||||
if (avr_split_shift (operands, operands[3], ASHIFT))
|
||||
DONE;
|
||||
else if (REGNO (operands[0]) == REGNO (operands[1]))
|
||||
FAIL;
|
||||
int offset = INTVAL (operands[2]);
|
||||
operands[4] = GEN_INT (offset & ~7);
|
||||
operands[5] = GEN_INT (offset & 7);
|
||||
})
|
||||
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:QI 3 "d")
|
||||
(parallel [(set (match_operand:ALL4 0 "register_operand" "")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "")
|
||||
(match_operand:QI 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC REG_CC))])]
|
||||
(clobber (reg:CC REG_CC))])
|
||||
;; $3 must not overlap with the output of the insn above.
|
||||
(match_dup 3)]
|
||||
""
|
||||
[(parallel [(set (match_dup 0)
|
||||
(ashift:ALL4 (match_dup 1)
|
||||
@ -5393,35 +5458,20 @@
|
||||
(clobber (match_dup 3))
|
||||
(clobber (reg:CC REG_CC))])])
|
||||
|
||||
;; "*ashlsi3_const"
|
||||
;; "*ashlsq3_const" "*ashlusq3_const"
|
||||
;; "*ashlsa3_const" "*ashlusa3_const"
|
||||
(define_insn_and_split "*ashl<mode>3_const_split"
|
||||
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r ,r")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r ,0")
|
||||
(match_operand:QI 2 "const_int_operand" "L,P,O C31,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
|
||||
"reload_completed"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(ashift:ALL4 (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (match_dup 3))
|
||||
(clobber (reg:CC REG_CC))])])
|
||||
|
||||
(define_insn "*ashl<mode>3_const"
|
||||
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r ,r")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r ,0")
|
||||
(match_operand:QI 2 "const_int_operand" "L,P,O C31,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))
|
||||
[(set (match_operand:ALL4 0 "register_operand" "=r ,r ,r ,r ,r")
|
||||
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0 ,r ,0 ,r ,0")
|
||||
(match_operand:QI 2 "const_int_operand" "LP,O C15 C31,C4l,C4l,n")))
|
||||
(clobber (match_operand:QI 3 "scratch_or_d_register_operand" "=X ,X ,&d ,&d ,&d"))
|
||||
(clobber (reg:CC REG_CC))]
|
||||
"reload_completed"
|
||||
{
|
||||
return ashlsi3_out (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "length" "0,4,5,10")
|
||||
(set_attr "adjust_len" "ashlsi")])
|
||||
[(set_attr "length" "10")
|
||||
(set_attr "adjust_len" "ashlsi")
|
||||
(set_attr "isa" "*,*,2op,3op,*")])
|
||||
|
||||
(define_expand "ashlpsi3"
|
||||
[(parallel [(set (match_operand:PSI 0 "register_operand" "")
|
||||
|
||||
@ -94,6 +94,10 @@ maccumulate-args
|
||||
Target Mask(ACCUMULATE_OUTGOING_ARGS) Optimization
|
||||
Optimization. Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf.
|
||||
|
||||
msplit-bit-shift
|
||||
Target Var(avr_split_bit_shift) Init(0) Optimization
|
||||
Optimization. Split shifts of 4-byte values into a byte shift and a residual bit shift.
|
||||
|
||||
mstrict-X
|
||||
Target Var(avr_strict_X) Init(0) Optimization
|
||||
Optimization. When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X.
|
||||
|
||||
@ -263,6 +263,22 @@
|
||||
(and (match_code "const_int,symbol_ref,const")
|
||||
(match_test "const_0mod256_operand (op, HImode)")))
|
||||
|
||||
(define_constraint "C4a"
|
||||
"A constant integer shift offset for a 4-byte ASHIFTRT that's opt to being split."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_split_shift_p (4, ival, ASHIFTRT)")))
|
||||
|
||||
(define_constraint "C4r"
|
||||
"A constant integer shift offset for a 4-byte LSHIFTRT that's opt to being split."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_split_shift_p (4, ival, LSHIFTRT)")))
|
||||
|
||||
(define_constraint "C4l"
|
||||
"A constant integer shift offset for a 4-byte ASHIFT that's opt to being split."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_split_shift_p (4, ival, ASHIFT)")))
|
||||
|
||||
|
||||
;; CONST_FIXED is no element of 'n' so cook our own.
|
||||
;; "i" or "s" would match but because the insn uses iterators that cover
|
||||
;; INT_MODE, "i" or "s" is not always possible.
|
||||
|
||||
@ -65,7 +65,7 @@ public:
|
||||
void execute_early_local_passes ();
|
||||
unsigned int execute_pass_mode_switching ();
|
||||
|
||||
/* Various passes are manually cloned by epiphany. */
|
||||
/* Various passes are manually cloned by avr and epiphany. */
|
||||
opt_pass *get_pass_split_all_insns () const {
|
||||
return pass_split_all_insns_1;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user