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Adjust docu of TARGET_VECTORIZE_VEC_PERM_CONST

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gcc/ChangeLog:

	* target.def: in0 and in1 do not need to be registers.
	* doc/tm.texi: Regenerate.
This commit is contained in:
Andreas Krebbel 2021-07-29 08:03:36 +02:00
parent e8de5bad25
commit 841548f0f7
2 changed files with 2 additions and 2 deletions
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2
gcc/doc/tm.texi
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@ -6125,7 +6125,7 @@ vectors of mode @var{mode} using the permutation vector @code{sel}, and
also to emit such a permutation. In the former case @var{in0}, @var{in1}
and @var{out} are all null. In the latter case @var{in0} and @var{in1} are
the source vectors and @var{out} is the destination vector; all three are
registers of mode @var{mode}. @var{in1} is the same as @var{in0} if
operands of mode @var{mode}. @var{in1} is the same as @var{in0} if
@var{sel} describes a permutation on one vector instead of two.
Return true if the operation is possible, emitting instructions for it

2
gcc/target.def
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@ -1861,7 +1861,7 @@ vectors of mode @var{mode} using the permutation vector @code{sel}, and\n\
also to emit such a permutation. In the former case @var{in0}, @var{in1}\n\
and @var{out} are all null. In the latter case @var{in0} and @var{in1} are\n\
the source vectors and @var{out} is the destination vector; all three are\n\
registers of mode @var{mode}. @var{in1} is the same as @var{in0} if\n\
operands of mode @var{mode}. @var{in1} is the same as @var{in0} if\n\
@var{sel} describes a permutation on one vector instead of two.\n\
\n\
Return true if the operation is possible, emitting instructions for it\n\