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Rename f_load to f_fpa_loads patch

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2011-01-20  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config/arm/arm.md (define_attr type): Rename f_load
	and f_store to f_fpa_load and f_fpa_store. Update.
	(write_conflict): Deal with rename fallout.
	(*push_fp_multi): Likewise.
	* config/arm/fpa.md (f_load): Use f_fpa_load.
	(f_store): Use f_fpa_store.
	(*movsf_fpa): Likewise.
	(*movdf_fpa): Likewise.
	(*movxf_fpa): Likewise.
	(*thumb2_movsf_fpa): Likewise.
	(*thumb2_movdf_fpa): Likewise.
	(*thumb2_movxf_fpa): Likewise.
	* config/arm/vfp.md (*thumb2_movdf_vfp): Fix attribute to
	f_loadd and f_stored.
	(*thumb2_movdi_vfp): Likewise.
	(*thumb2_movsf_vfp): Fix attribute to f_loads.
	(*thumb2_movsi_vfp): Likewise.
	* config/arm/cortex-m4-fpu.md (cortex_m4_f_load):
	Use f_loads instead of f_load.
	* config/arm/cortex-a5.md (cortex_a5_f_loads): Remove f_load.

From-SVN: r169071
This commit is contained in:
Ramana Radhakrishnan 2011-01-20 22:03:29 +00:00 committed by Ramana Radhakrishnan
parent aaab40fa2a
commit 837b01f66f
6 changed files with 46 additions and 23 deletions
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23
gcc/ChangeLog
View File

@ -1,3 +1,26 @@
2011-01-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.md (define_attr type): Rename f_load
and f_store to f_fpa_load and f_fpa_store. Update.
(write_conflict): Deal with rename fallout.
(*push_fp_multi): Likewise.
* config/arm/fpa.md (f_load): Use f_fpa_load.
(f_store): Use f_fpa_store.
(*movsf_fpa): Likewise.
(*movdf_fpa): Likewise.
(*movxf_fpa): Likewise.
(*thumb2_movsf_fpa): Likewise.
(*thumb2_movdf_fpa): Likewise.
(*thumb2_movxf_fpa): Likewise.
* config/arm/vfp.md (*thumb2_movdf_vfp): Fix attribute to
f_loadd and f_stored.
(*thumb2_movdi_vfp): Likewise.
(*thumb2_movsf_vfp): Fix attribute to f_loads.
(*thumb2_movsi_vfp): Likewise.
* config/arm/cortex-m4-fpu.md (cortex_m4_f_load):
Use f_loads instead of f_load.
* config/arm/cortex-a5.md (cortex_a5_f_loads): Remove f_load.
2011-01-20 Anatoly Sokolov <aesok@post.ru>
* config/xtensa/xtensa.h (GO_IF_MODE_DEPENDENT_ADDRESS): Remove.

14
gcc/config/arm/arm.md
View File

@ -299,10 +299,10 @@
; ffarith Fast floating point arithmetic (2 cycle)
; float_em a floating point arithmetic operation that is normally emulated
; even on a machine with an fpa.
; f_load a floating point load from memory
; f_store a floating point store to memory
; f_load[sd] single/double load from memory
; f_store[sd] single/double store to memory
; f_fpa_load a floating point load from memory. Only for the FPA.
; f_fpa_store a floating point store to memory. Only for the FPA.
; f_load[sd] A single/double load from memory. Used for VFP unit.
; f_store[sd] A single/double store to memory. Used for VFP unit.
; f_flag a transfer of co-processor flags to the CPSR
; f_mem_r a transfer of a floating point register to a real reg via mem
; r_mem_f the reverse of f_mem_r
@ -326,7 +326,7 @@
;
(define_attr "type"
"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_load,f_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
(if_then_else
(eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
(const_string "mult")
@ -450,7 +450,7 @@
; to stall the processor. Used with model_wbuf above.
(define_attr "write_conflict" "no,yes"
(if_then_else (eq_attr "type"
"block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load1")
"block,float_em,f_fpa_load,f_fpa_store,f_mem_r,r_mem_f,call,load1")
(const_string "yes")
(const_string "no")))
@ -10285,7 +10285,7 @@
output_asm_insn (pattern, operands);
return \"\";
}"
[(set_attr "type" "f_store")]
[(set_attr "type" "f_fpa_store")]
)
;; Special patterns for dealing with the constant pool

4
gcc/config/arm/cortex-a5.md
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@ -270,7 +270,7 @@
(define_insn_reservation "cortex_a5_f_loadd" 5
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "f_load,f_loadd"))
(eq_attr "type" "f_loadd"))
"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
(define_insn_reservation "cortex_a5_f_stores" 0
@ -280,7 +280,7 @@
(define_insn_reservation "cortex_a5_f_stored" 0
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "f_store,f_stored"))
(eq_attr "type" "f_stored"))
"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
;; Load-to-use for floating-point values has a penalty of one cycle,

4
gcc/config/arm/cortex-m4-fpu.md
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@ -76,12 +76,12 @@
(define_insn_reservation "cortex_m4_f_load" 2
(and (eq_attr "tune" "cortexm4")
(eq_attr "type" "f_load"))
(eq_attr "type" "f_loads"))
"cortex_m4_ex_v*2")
(define_insn_reservation "cortex_m4_f_store" 2
(and (eq_attr "tune" "cortexm4")
(eq_attr "type" "f_store"))
(eq_attr "type" "f_stores"))
"cortex_m4_ex_v*2")
(define_insn_reservation "cortex_m4_f_loadd" 3

16
gcc/config/arm/fpa.md
View File

@ -83,11 +83,11 @@
"core+fpa*2")
(define_insn_reservation "f_load" 3
(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load"))
(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_load"))
"fpa_mem+core*3")
(define_insn_reservation "f_store" 4
(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store"))
(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_store"))
"core*4")
(define_insn_reservation "r_mem_f" 6
@ -545,7 +545,7 @@
[(set_attr "length" "4,4,4,4,8,8,4,4,4")
(set_attr "predicable" "yes")
(set_attr "type"
"ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1")
"ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
(set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
(set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
)
@ -580,7 +580,7 @@
[(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
(set_attr "predicable" "yes")
(set_attr "type"
"load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
"load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
(set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
)
@ -609,7 +609,7 @@
"
[(set_attr "length" "4,4,4")
(set_attr "predicable" "yes")
(set_attr "type" "ffarith,f_load,f_store")]
(set_attr "type" "ffarith,f_fpa_load,f_fpa_store")]
)
;; stfs/ldfs always use a conditional infix. This works around the
@ -635,7 +635,7 @@
(set_attr "ce_count" "1,1,1,1,2,2,1,1,1")
(set_attr "predicable" "yes")
(set_attr "type"
"ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1")
"ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
(set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
(set_attr "neg_pool_range" "*,*,1012,*,*,*,*,0,*")]
)
@ -669,7 +669,7 @@
"
[(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
(set_attr "type"
"load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
"load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
(set_attr "pool_range" "*,*,*,*,4092,*,*,1024,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,0,*,*,1020,*,*,*")]
)
@ -698,7 +698,7 @@
}
"
[(set_attr "length" "4,4,4,4,8,8,12")
(set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")
(set_attr "type" "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*")
(set_attr "pool_range" "*,*,1024,*,*,*,*")
(set_attr "neg_pool_range" "*,*,1004,*,*,*,*")]
)

8
gcc/config/arm/vfp.md
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@ -124,7 +124,7 @@
}
"
[(set_attr "predicable" "yes")
(set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
(set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
@ -200,7 +200,7 @@
abort ();
}
"
[(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
[(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
(set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
(eq_attr "alternative" "5")
(if_then_else
@ -391,7 +391,7 @@
"
[(set_attr "predicable" "yes")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
(set_attr "insn" "*,*,*,*,*,*,*,*,mov")
(set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
@ -478,7 +478,7 @@
}
"
[(set_attr "type"
"r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
"r_2_f,f_2_r,fconstd,load2,store2,f_loadd,f_stored,ffarithd,*")
(set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else