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pa.c (emit_hpdiv_const): Return reg is r2 for 64-bit millicode.
* config/pa/pa.c (emit_hpdiv_const): Return reg is r2 for 64-bit millicode. (insn_refs_are_delayed): Correct comment. * config/pa/pa.h (INSN_REFERENCES_ARE_DELAYED): Likewise. * config/pa/pa.md (mulsi3): If TARGET_64BIT, clobber r2 instead of r31. Make associated insn !TARGET_64BIT, and provide an additional 64-bit insn that clobbers r2. (divsi3): Likewise. (udivsi3): Likewise. (modsi3): Likewise. (umodsi3): Likewise. From-SVN: r44003
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Alan Modra
Alan Modra
parent
1ed672dd7c
commit
7d8b141211
@ -1,3 +1,17 @@
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2001-07-14 Alan Modra <amodra@bigpond.net.au>
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* config/pa/pa.c (emit_hpdiv_const): Return reg is r2 for 64-bit
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millicode.
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(insn_refs_are_delayed): Correct comment.
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* config/pa/pa.h (INSN_REFERENCES_ARE_DELAYED): Likewise.
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* config/pa/pa.md (mulsi3): If TARGET_64BIT, clobber r2
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instead of r31. Make associated insn !TARGET_64BIT, and
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provide an additional 64-bit insn that clobbers r2.
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(divsi3): Likewise.
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(udivsi3): Likewise.
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(modsi3): Likewise.
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(umodsi3): Likewise.
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Sat Jul 14 02:58:38 CEST 2001 Jan Hubicka <jh@suse.cz>
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* bb-reorder.c (skip_insn_after_block): Get past the line number notes.
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@ -4450,6 +4450,8 @@ emit_hpdiv_const (operands, unsignedp)
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&& INTVAL (operands[2]) < 16
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&& magic_milli[INTVAL (operands[2])])
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{
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rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
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emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
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emit
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(gen_rtx
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@ -4463,7 +4465,7 @@ emit_hpdiv_const (operands, unsignedp)
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gen_rtx_CLOBBER (VOIDmode, operands[3]),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
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gen_rtx_CLOBBER (VOIDmode, ret))));
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emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
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return 1;
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}
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@ -6904,12 +6906,18 @@ pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
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Millicode calls always expect their arguments in the integer argument
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registers, and always return their result in %r29 (ret1). They
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are expected to clobber their arguments, %r1, %r29, and %r31 and
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nothing else.
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are expected to clobber their arguments, %r1, %r29, and the return
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pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
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By considering this effects delayed reorg reorg can put insns
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which set the argument registers into the delay slot of the millicode
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call -- thus they act more like traditional CALL_INSNs.
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This function tells reorg that the references to arguments and
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millicode calls do not appear to happen until after the millicode call.
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This allows reorg to put insns which set the argument registers into the
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delay slot of the millicode call -- thus they act more like traditional
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CALL_INSNs.
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Note we can not consider side effects of the insn to be delayed because
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the branch and link insn will clobber the return pointer. If we happened
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to use the return pointer in the delay slot of the call, then we lose.
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get_attr_type will try to recognize the given insn, so make sure to
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filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
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@ -1691,8 +1691,8 @@ while (0)
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Millicode calls always expect their arguments in the integer argument
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registers, and always return their result in %r29 (ret1). They
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are expected to clobber their arguments, %r1, %r29, and %r31 and
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nothing else.
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are expected to clobber their arguments, %r1, %r29, and the return
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pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
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This macro tells reorg that the references to arguments and
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millicode calls do not appear to happen until after the millicode call.
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@ -3869,11 +3869,12 @@
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(clobber (match_dup 3))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))])
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(clobber (match_dup 4))])
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(set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
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""
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"
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{
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operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
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if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
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{
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rtx scratch = gen_reg_rtx (DImode);
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@ -3930,7 +3931,7 @@
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))]
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""
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"!TARGET_64BIT"
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"* return output_mul_insn (0, insn);"
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[(set_attr "type" "milli")
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(set (attr "length")
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@ -3955,6 +3956,17 @@
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;; Out of reach, can use ble
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(const_int 12)))])
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(define_insn ""
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[(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
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(clobber (match_operand:SI 0 "register_operand" "=a"))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 2))]
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"TARGET_64BIT"
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"* return output_mul_insn (0, insn);"
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[(set_attr "type" "milli")
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(set (attr "length") (const_int 4))])
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(define_expand "muldi3"
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[(set (match_operand:DI 0 "register_operand" "")
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(mult:DI (match_operand:DI 1 "register_operand" "")
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@ -4012,15 +4024,22 @@
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(clobber (match_dup 4))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))])
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(clobber (match_dup 5))])
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(set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
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""
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"
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{
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operands[3] = gen_reg_rtx (SImode);
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operands[4] = gen_reg_rtx (SImode);
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if (TARGET_64BIT)
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operands[4] = gen_rtx_REG (SImode, 2);
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{
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operands[5] = gen_rtx_REG (SImode, 2);
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operands[4] = operands[5];
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}
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else
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{
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operands[5] = gen_rtx_REG (SImode, 31);
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operands[4] = gen_reg_rtx (SImode);
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}
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if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
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DONE;
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}")
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@ -4033,7 +4052,7 @@
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))]
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""
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"!TARGET_64BIT"
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"*
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return output_div_insn (operands, 0, insn);"
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[(set_attr "type" "milli")
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@ -4059,6 +4078,20 @@
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;; Out of reach, can use ble
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(const_int 12)))])
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(define_insn ""
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[(set (reg:SI 29)
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(div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
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(clobber (match_operand:SI 1 "register_operand" "=a"))
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(clobber (match_operand:SI 2 "register_operand" "=&r"))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 2))]
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"TARGET_64BIT"
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"*
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return output_div_insn (operands, 0, insn);"
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[(set_attr "type" "milli")
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(set (attr "length") (const_int 4))])
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(define_expand "udivsi3"
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[(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
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(set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
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@ -4067,15 +4100,22 @@
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(clobber (match_dup 4))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))])
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(clobber (match_dup 5))])
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(set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
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""
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"
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{
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operands[3] = gen_reg_rtx (SImode);
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operands[4] = gen_reg_rtx (SImode);
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if (TARGET_64BIT)
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operands[4] = gen_rtx_REG (SImode, 2);
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{
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operands[5] = gen_rtx_REG (SImode, 2);
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operands[4] = operands[5];
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}
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else
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{
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operands[5] = gen_rtx_REG (SImode, 31);
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operands[4] = gen_reg_rtx (SImode);
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}
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if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
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DONE;
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}")
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@ -4088,7 +4128,7 @@
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))]
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""
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"!TARGET_64BIT"
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"*
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return output_div_insn (operands, 1, insn);"
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[(set_attr "type" "milli")
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@ -4114,6 +4154,20 @@
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;; Out of reach, can use ble
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(const_int 12)))])
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(define_insn ""
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[(set (reg:SI 29)
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(udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
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(clobber (match_operand:SI 1 "register_operand" "=a"))
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(clobber (match_operand:SI 2 "register_operand" "=&r"))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 2))]
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"TARGET_64BIT"
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"*
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return output_div_insn (operands, 1, insn);"
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[(set_attr "type" "milli")
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(set (attr "length") (const_int 4))])
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(define_expand "modsi3"
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[(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
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(set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
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@ -4122,14 +4176,21 @@
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(clobber (match_dup 4))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))])
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(clobber (match_dup 5))])
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(set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
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""
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"
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{
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operands[4] = gen_reg_rtx (SImode);
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if (TARGET_64BIT)
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operands[4] = gen_rtx_REG (SImode, 2);
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{
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operands[5] = gen_rtx_REG (SImode, 2);
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operands[4] = operands[5];
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}
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else
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{
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operands[5] = gen_rtx_REG (SImode, 31);
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operands[4] = gen_reg_rtx (SImode);
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}
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operands[3] = gen_reg_rtx (SImode);
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}")
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@ -4140,7 +4201,7 @@
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))]
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""
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"!TARGET_64BIT"
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"*
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return output_mod_insn (0, insn);"
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[(set_attr "type" "milli")
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@ -4166,6 +4227,19 @@
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;; Out of reach, can use ble
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(const_int 12)))])
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(define_insn ""
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[(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
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(clobber (match_operand:SI 0 "register_operand" "=a"))
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(clobber (match_operand:SI 1 "register_operand" "=&r"))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 2))]
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"TARGET_64BIT"
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"*
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return output_mod_insn (0, insn);"
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[(set_attr "type" "milli")
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(set (attr "length") (const_int 4))])
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(define_expand "umodsi3"
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[(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
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(set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
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@ -4174,14 +4248,21 @@
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(clobber (match_dup 4))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))])
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(clobber (match_dup 5))])
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(set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
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""
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"
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{
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operands[4] = gen_reg_rtx (SImode);
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if (TARGET_64BIT)
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operands[4] = gen_rtx_REG (SImode, 2);
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{
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operands[5] = gen_rtx_REG (SImode, 2);
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operands[4] = operands[5];
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}
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else
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{
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operands[5] = gen_rtx_REG (SImode, 31);
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operands[4] = gen_reg_rtx (SImode);
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}
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operands[3] = gen_reg_rtx (SImode);
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}")
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@ -4192,7 +4273,7 @@
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 31))]
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""
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"!TARGET_64BIT"
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"*
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return output_mod_insn (1, insn);"
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[(set_attr "type" "milli")
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@ -4218,6 +4299,19 @@
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;; Out of reach, can use ble
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(const_int 12)))])
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(define_insn ""
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[(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
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(clobber (match_operand:SI 0 "register_operand" "=a"))
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(clobber (match_operand:SI 1 "register_operand" "=&r"))
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(clobber (reg:SI 26))
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(clobber (reg:SI 25))
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(clobber (reg:SI 2))]
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"TARGET_64BIT"
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"*
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return output_mod_insn (1, insn);"
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[(set_attr "type" "milli")
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(set (attr "length") (const_int 4))])
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;;- and instructions
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;; We define DImode `and` so with DImode `not` we can get
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;; DImode `andn`. Other combinations are possible.
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