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Small housekeeping work in SPARC back-end
gcc/ * config/sparc/sparc.c (gen_load_pcrel_sym): Delete. (load_got_register): Do the PIC dance here. (sparc_legitimize_tls_address): Simplify. (sparc_emit_probe_stack_range): Likewise. (sparc32_initialize_trampoline): Likewise. (sparc64_initialize_trampoline): Likewise. * config/sparc/sparc.md (load_pcrel_sym<P:mode>): Add @ marker. (probe_stack_range<P:mode>): Likewise. (flush<P:mode>): Likewise. (tgd_hi22<P:mode>): Likewise. (tgd_lo10<P:mode>): Likewise. (tgd_add<P:mode>): Likewise. (tgd_call<P:mode>): Likewise. (tldm_hi22<P:mode>): Likewise. (tldm_lo10<P:mode>): Likewise. (tldm_add<P:mode>): Likewise. (tldm_call<P:mode>): Likewise. (tldo_hix22<P:mode>): Likewise. (tldo_lox10<P:mode>): Likewise. (tldo_add<P:mode>): Likewise. (tie_hi22<P:mode>): Likewise. (tie_lo10<P:mode>): Likewise. (tie_add<P:mode>): Likewise. (tle_hix22<P:mode>): Likewise. (tle_lox10<P:mode>): Likewise. (stack_protect_setsi): Rename to... (stack_protect_set32): ...this. (stack_protect_setdi): Rename to... (stack_protect_set64): ...this. (stack_protect_set): Adjust calls to above. (stack_protect_testsi): Rename to... (stack_protect_test32): ...this. (stack_protect_testdi): Rename to... (stack_protect_test64): ...this. (stack_protect_test): Adjust calls to above.
This commit is contained in:
Eric Botcazou
parent
985b3a6837
commit
7d6f7aa409
@ -4213,26 +4213,7 @@ sparc_got (void)
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return got_symbol_rtx;
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}
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/* Wrapper around the load_pcrel_sym{si,di} patterns. */
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static rtx
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gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
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{
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int orig_flag_pic = flag_pic;
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rtx insn;
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/* The load_pcrel_sym{si,di} patterns require absolute addressing. */
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flag_pic = 0;
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if (TARGET_ARCH64)
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insn = gen_load_pcrel_symdi (op0, op1, op2, GEN_INT (REGNO (op0)));
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else
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insn = gen_load_pcrel_symsi (op0, op1, op2, GEN_INT (REGNO (op0)));
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flag_pic = orig_flag_pic;
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return insn;
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}
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/* Output the load_pcrel_sym{si,di} patterns. */
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/* Output the load_pcrel_sym pattern. */
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const char *
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output_load_pcrel_sym (rtx *operands)
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@ -4299,8 +4280,15 @@ load_got_register (void)
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got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
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}
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insn
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= gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
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/* The load_pcrel_sym{si,di} patterns require absolute addressing. */
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const int orig_flag_pic = flag_pic;
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flag_pic = 0;
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insn = gen_load_pcrel_sym (Pmode,
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got_register_rtx,
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sparc_got (),
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got_helper_rtx,
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GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM));
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flag_pic = orig_flag_pic;
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}
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emit_insn (insn);
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@ -4680,22 +4668,11 @@ sparc_legitimize_tls_address (rtx addr)
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ret = gen_reg_rtx (Pmode);
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o0 = gen_rtx_REG (Pmode, 8);
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got = sparc_tls_got ();
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if (TARGET_ARCH32)
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{
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emit_insn (gen_tgd_hi22si (temp1, addr));
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emit_insn (gen_tgd_lo10si (temp2, temp1, addr));
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emit_insn (gen_tgd_addsi (o0, got, temp2, addr));
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insn = emit_call_insn (gen_tgd_callsi (o0, sparc_tls_get_addr (),
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addr, const1_rtx));
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}
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else
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{
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emit_insn (gen_tgd_hi22di (temp1, addr));
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emit_insn (gen_tgd_lo10di (temp2, temp1, addr));
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emit_insn (gen_tgd_adddi (o0, got, temp2, addr));
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insn = emit_call_insn (gen_tgd_calldi (o0, sparc_tls_get_addr (),
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addr, const1_rtx));
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}
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emit_insn (gen_tgd_hi22 (Pmode, temp1, addr));
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emit_insn (gen_tgd_lo10 (Pmode, temp2, temp1, addr));
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emit_insn (gen_tgd_add (Pmode, o0, got, temp2, addr));
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insn = emit_call_insn (gen_tgd_call (Pmode, o0, sparc_tls_get_addr (),
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addr, const1_rtx));
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use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
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RTL_CONST_CALL_P (insn) = 1;
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insn = get_insns ();
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@ -4711,22 +4688,11 @@ sparc_legitimize_tls_address (rtx addr)
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ret = gen_reg_rtx (Pmode);
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o0 = gen_rtx_REG (Pmode, 8);
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got = sparc_tls_got ();
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if (TARGET_ARCH32)
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{
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emit_insn (gen_tldm_hi22si (temp1));
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emit_insn (gen_tldm_lo10si (temp2, temp1));
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emit_insn (gen_tldm_addsi (o0, got, temp2));
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insn = emit_call_insn (gen_tldm_callsi (o0, sparc_tls_get_addr (),
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const1_rtx));
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}
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else
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{
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emit_insn (gen_tldm_hi22di (temp1));
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emit_insn (gen_tldm_lo10di (temp2, temp1));
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emit_insn (gen_tldm_adddi (o0, got, temp2));
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insn = emit_call_insn (gen_tldm_calldi (o0, sparc_tls_get_addr (),
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const1_rtx));
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}
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emit_insn (gen_tldm_hi22 (Pmode, temp1));
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emit_insn (gen_tldm_lo10 (Pmode, temp2, temp1));
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emit_insn (gen_tldm_add (Pmode, o0, got, temp2));
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insn = emit_call_insn (gen_tldm_call (Pmode, o0, sparc_tls_get_addr (),
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const1_rtx));
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use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
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RTL_CONST_CALL_P (insn) = 1;
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insn = get_insns ();
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@ -4738,18 +4704,9 @@ sparc_legitimize_tls_address (rtx addr)
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UNSPEC_TLSLD_BASE));
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temp1 = gen_reg_rtx (Pmode);
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temp2 = gen_reg_rtx (Pmode);
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if (TARGET_ARCH32)
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{
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emit_insn (gen_tldo_hix22si (temp1, addr));
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emit_insn (gen_tldo_lox10si (temp2, temp1, addr));
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emit_insn (gen_tldo_addsi (ret, temp3, temp2, addr));
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}
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else
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{
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emit_insn (gen_tldo_hix22di (temp1, addr));
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emit_insn (gen_tldo_lox10di (temp2, temp1, addr));
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emit_insn (gen_tldo_adddi (ret, temp3, temp2, addr));
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}
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emit_insn (gen_tldo_hix22 (Pmode, temp1, addr));
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emit_insn (gen_tldo_lox10 (Pmode, temp2, temp1, addr));
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emit_insn (gen_tldo_add (Pmode, ret, temp3, temp2, addr));
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break;
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case TLS_MODEL_INITIAL_EXEC:
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@ -4757,27 +4714,17 @@ sparc_legitimize_tls_address (rtx addr)
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temp2 = gen_reg_rtx (Pmode);
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temp3 = gen_reg_rtx (Pmode);
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got = sparc_tls_got ();
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emit_insn (gen_tie_hi22 (Pmode, temp1, addr));
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emit_insn (gen_tie_lo10 (Pmode, temp2, temp1, addr));
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if (TARGET_ARCH32)
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{
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emit_insn (gen_tie_hi22si (temp1, addr));
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emit_insn (gen_tie_lo10si (temp2, temp1, addr));
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emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
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}
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emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
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else
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{
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emit_insn (gen_tie_hi22di (temp1, addr));
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emit_insn (gen_tie_lo10di (temp2, temp1, addr));
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emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
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}
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emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
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if (TARGET_SUN_TLS)
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{
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ret = gen_reg_rtx (Pmode);
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if (TARGET_ARCH32)
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emit_insn (gen_tie_addsi (ret, gen_rtx_REG (Pmode, 7),
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temp3, addr));
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else
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emit_insn (gen_tie_adddi (ret, gen_rtx_REG (Pmode, 7),
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temp3, addr));
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emit_insn (gen_tie_add (Pmode, ret, gen_rtx_REG (Pmode, 7),
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temp3, addr));
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}
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else
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ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
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@ -4786,16 +4733,8 @@ sparc_legitimize_tls_address (rtx addr)
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case TLS_MODEL_LOCAL_EXEC:
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temp1 = gen_reg_rtx (Pmode);
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temp2 = gen_reg_rtx (Pmode);
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if (TARGET_ARCH32)
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{
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emit_insn (gen_tle_hix22si (temp1, addr));
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emit_insn (gen_tle_lox10si (temp2, temp1, addr));
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}
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else
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{
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emit_insn (gen_tle_hix22di (temp1, addr));
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emit_insn (gen_tle_lox10di (temp2, temp1, addr));
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}
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emit_insn (gen_tle_hix22 (Pmode, temp1, addr));
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emit_insn (gen_tle_lox10 (Pmode, temp2, temp1, addr));
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ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
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break;
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@ -5696,10 +5635,7 @@ sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
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probes at FIRST + N * PROBE_INTERVAL for values of N from 1
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until it is equal to ROUNDED_SIZE. */
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if (TARGET_ARCH64)
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emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
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else
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emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
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emit_insn (gen_probe_stack_range (Pmode, g1, g1, g4));
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/* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
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@ -9940,9 +9876,11 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
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GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
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NULL_RTX, 1, OPTAB_DIRECT));
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emit_insn
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(gen_flush (SImode, validize_mem (adjust_address (m_tramp, SImode, 0))));
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/* On UltraSPARC a flush flushes an entire cache line. The trampoline is
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aligned on a 16 byte boundary so one flush clears it all. */
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emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 0))));
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if (sparc_cpu != PROCESSOR_ULTRASPARC
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&& sparc_cpu != PROCESSOR_ULTRASPARC3
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&& sparc_cpu != PROCESSOR_NIAGARA
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@ -9951,7 +9889,8 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
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&& sparc_cpu != PROCESSOR_NIAGARA4
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&& sparc_cpu != PROCESSOR_NIAGARA7
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&& sparc_cpu != PROCESSOR_M8)
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emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8))));
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emit_insn
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(gen_flush (SImode, validize_mem (adjust_address (m_tramp, SImode, 8))));
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/* Call __enable_execute_stack after writing onto the stack to make sure
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the stack address is accessible. */
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@ -9988,8 +9927,11 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
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GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
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emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
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emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
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emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
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emit_insn
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(gen_flush (DImode, validize_mem (adjust_address (m_tramp, DImode, 0))));
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/* On UltraSPARC a flush flushes an entire cache line. The trampoline is
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aligned on a 16 byte boundary so one flush clears it all. */
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if (sparc_cpu != PROCESSOR_ULTRASPARC
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&& sparc_cpu != PROCESSOR_ULTRASPARC3
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&& sparc_cpu != PROCESSOR_NIAGARA
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@ -9998,7 +9940,8 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
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&& sparc_cpu != PROCESSOR_NIAGARA4
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&& sparc_cpu != PROCESSOR_NIAGARA7
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&& sparc_cpu != PROCESSOR_M8)
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emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
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emit_insn
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(gen_flush (DImode, validize_mem (adjust_address (m_tramp, DImode, 8))));
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/* Call __enable_execute_stack after writing onto the stack to make sure
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the stack address is accessible. */
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@ -1592,7 +1592,7 @@
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;; because the RDPC instruction is extremely expensive and incurs a complete
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;; instruction pipeline flush.
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(define_insn "load_pcrel_sym<P:mode>"
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(define_insn "@load_pcrel_sym<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(unspec:P [(match_operand:P 1 "symbolic_operand" "")
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(match_operand:P 2 "call_address_operand" "")
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@ -7290,7 +7290,7 @@ visl")
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= adjust_address (operands[0], GET_MODE (operands[0]), SPARC_STACK_BIAS);
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})
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(define_insn "probe_stack_range<P:mode>"
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(define_insn "@probe_stack_range<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
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(match_operand:P 2 "register_operand" "r")]
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@ -7468,7 +7468,7 @@ visl")
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;; Special pattern for the FLUSH instruction.
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(define_insn "flush<P:mode>"
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(define_insn "@flush<P:mode>"
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[(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)]
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""
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{
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@ -7935,14 +7935,14 @@ visl")
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;; TLS support instructions.
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(define_insn "tgd_hi22<P:mode>"
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(define_insn "@tgd_hi22<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(high:P (unspec:P [(match_operand 1 "tgd_symbolic_operand" "")]
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UNSPEC_TLSGD)))]
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"TARGET_TLS"
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"sethi\\t%%tgd_hi22(%a1), %0")
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(define_insn "tgd_lo10<P:mode>"
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(define_insn "@tgd_lo10<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(lo_sum:P (match_operand:P 1 "register_operand" "r")
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(unspec:P [(match_operand 2 "tgd_symbolic_operand" "")]
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@ -7950,7 +7950,7 @@ visl")
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"TARGET_TLS"
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"add\\t%1, %%tgd_lo10(%a2), %0")
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(define_insn "tgd_add<P:mode>"
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(define_insn "@tgd_add<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(plus:P (match_operand:P 1 "register_operand" "r")
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(unspec:P [(match_operand:P 2 "register_operand" "r")
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@ -7959,7 +7959,7 @@ visl")
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"TARGET_TLS"
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"add\\t%1, %2, %0, %%tgd_add(%a3)")
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(define_insn "tgd_call<P:mode>"
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(define_insn "@tgd_call<P:mode>"
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[(set (match_operand 0 "register_operand" "=r")
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(call (mem:P (unspec:P [(match_operand:P 1 "symbolic_operand" "s")
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(match_operand 2 "tgd_symbolic_operand" "")]
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@ -7972,20 +7972,20 @@ visl")
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(const_string "call")
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(const_string "call_no_delay_slot")))])
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(define_insn "tldm_hi22<P:mode>"
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(define_insn "@tldm_hi22<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(high:P (unspec:P [(const_int 0)] UNSPEC_TLSLDM)))]
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"TARGET_TLS"
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"sethi\\t%%tldm_hi22(%&), %0")
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(define_insn "tldm_lo10<P:mode>"
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(define_insn "@tldm_lo10<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(lo_sum:P (match_operand:P 1 "register_operand" "r")
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(unspec:P [(const_int 0)] UNSPEC_TLSLDM)))]
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"TARGET_TLS"
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"add\\t%1, %%tldm_lo10(%&), %0")
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(define_insn "tldm_add<P:mode>"
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(define_insn "@tldm_add<P:mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(plus:P (match_operand:P 1 "register_operand" "r")
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(unspec:P [(match_operand:P 2 "register_operand" "r")]
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@ -7993,7 +7993,7 @@ visl")
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"TARGET_TLS"
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"add\\t%1, %2, %0, %%tldm_add(%&)")
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(define_insn "tldm_call<P:mode>"
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(define_insn "@tldm_call<P:mode>"
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[(set (match_operand 0 "register_operand" "=r")
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(call (mem:P (unspec:P [(match_operand:P 1 "symbolic_operand" "s")]
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UNSPEC_TLSLDM))
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@ -8005,14 +8005,14 @@ visl")
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(const_string "call")
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(const_string "call_no_delay_slot")))])
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(define_insn "tldo_hix22<P:mode>"
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||||
(define_insn "@tldo_hix22<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(high:P (unspec:P [(match_operand 1 "tld_symbolic_operand" "")]
|
||||
UNSPEC_TLSLDO)))]
|
||||
"TARGET_TLS"
|
||||
"sethi\\t%%tldo_hix22(%a1), %0")
|
||||
|
||||
(define_insn "tldo_lox10<P:mode>"
|
||||
(define_insn "@tldo_lox10<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(lo_sum:P (match_operand:P 1 "register_operand" "r")
|
||||
(unspec:P [(match_operand 2 "tld_symbolic_operand" "")]
|
||||
@ -8020,7 +8020,7 @@ visl")
|
||||
"TARGET_TLS"
|
||||
"xor\\t%1, %%tldo_lox10(%a2), %0")
|
||||
|
||||
(define_insn "tldo_add<P:mode>"
|
||||
(define_insn "@tldo_add<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(plus:P (match_operand:P 1 "register_operand" "r")
|
||||
(unspec:P [(match_operand:P 2 "register_operand" "r")
|
||||
@ -8029,14 +8029,14 @@ visl")
|
||||
"TARGET_TLS"
|
||||
"add\\t%1, %2, %0, %%tldo_add(%a3)")
|
||||
|
||||
(define_insn "tie_hi22<P:mode>"
|
||||
(define_insn "@tie_hi22<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(high:P (unspec:P [(match_operand 1 "tie_symbolic_operand" "")]
|
||||
UNSPEC_TLSIE)))]
|
||||
"TARGET_TLS"
|
||||
"sethi\\t%%tie_hi22(%a1), %0")
|
||||
|
||||
(define_insn "tie_lo10<P:mode>"
|
||||
(define_insn "@tie_lo10<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(lo_sum:P (match_operand:P 1 "register_operand" "r")
|
||||
(unspec:P [(match_operand 2 "tie_symbolic_operand" "")]
|
||||
@ -8068,7 +8068,7 @@ visl")
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "subtype" "regular")])
|
||||
|
||||
(define_insn "tie_add<P:mode>"
|
||||
(define_insn "@tie_add<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(plus:P (match_operand:P 1 "register_operand" "r")
|
||||
(unspec:P [(match_operand:P 2 "register_operand" "r")
|
||||
@ -8077,14 +8077,14 @@ visl")
|
||||
"TARGET_SUN_TLS"
|
||||
"add\\t%1, %2, %0, %%tie_add(%a3)")
|
||||
|
||||
(define_insn "tle_hix22<P:mode>"
|
||||
(define_insn "@tle_hix22<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(high:P (unspec:P [(match_operand 1 "tle_symbolic_operand" "")]
|
||||
UNSPEC_TLSLE)))]
|
||||
"TARGET_TLS"
|
||||
"sethi\\t%%tle_hix22(%a1), %0")
|
||||
|
||||
(define_insn "tle_lox10<P:mode>"
|
||||
(define_insn "@tle_lox10<P:mode>"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(lo_sum:P (match_operand:P 1 "register_operand" "r")
|
||||
(unspec:P [(match_operand 2 "tle_symbolic_operand" "")]
|
||||
@ -8342,13 +8342,13 @@ visl")
|
||||
operands[1] = gen_rtx_MEM (Pmode, addr);
|
||||
#endif
|
||||
if (TARGET_ARCH64)
|
||||
emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
|
||||
emit_insn (gen_stack_protect_set64 (operands[0], operands[1]));
|
||||
else
|
||||
emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
|
||||
emit_insn (gen_stack_protect_set32 (operands[0], operands[1]));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "stack_protect_setsi"
|
||||
(define_insn "stack_protect_set32"
|
||||
[(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
|
||||
(set (match_scratch:SI 2 "=&r") (const_int 0))]
|
||||
@ -8357,7 +8357,7 @@ visl")
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "length" "3")])
|
||||
|
||||
(define_insn "stack_protect_setdi"
|
||||
(define_insn "stack_protect_set64"
|
||||
[(set (match_operand:DI 0 "memory_operand" "=m")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
|
||||
(set (match_scratch:DI 2 "=&r") (const_int 0))]
|
||||
@ -8381,13 +8381,13 @@ visl")
|
||||
if (TARGET_ARCH64)
|
||||
{
|
||||
result = gen_reg_rtx (Pmode);
|
||||
emit_insn (gen_stack_protect_testdi (result, operands[0], operands[1]));
|
||||
emit_insn (gen_stack_protect_test64 (result, operands[0], operands[1]));
|
||||
test = gen_rtx_EQ (VOIDmode, result, const0_rtx);
|
||||
emit_jump_insn (gen_cbranchdi4 (test, result, const0_rtx, operands[2]));
|
||||
}
|
||||
else
|
||||
{
|
||||
emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
|
||||
emit_insn (gen_stack_protect_test32 (operands[0], operands[1]));
|
||||
result = gen_rtx_REG (CCmode, SPARC_ICC_REG);
|
||||
test = gen_rtx_EQ (VOIDmode, result, const0_rtx);
|
||||
emit_jump_insn (gen_cbranchcc4 (test, result, const0_rtx, operands[2]));
|
||||
@ -8395,7 +8395,7 @@ visl")
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "stack_protect_testsi"
|
||||
(define_insn "stack_protect_test32"
|
||||
[(set (reg:CC CC_REG)
|
||||
(unspec:CC [(match_operand:SI 0 "memory_operand" "m")
|
||||
(match_operand:SI 1 "memory_operand" "m")]
|
||||
@ -8407,7 +8407,7 @@ visl")
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn "stack_protect_testdi"
|
||||
(define_insn "stack_protect_test64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "memory_operand" "m")]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user