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i386: Support vectorized BF16 FMA with AVX10.2 instructions
gcc/ChangeLog: * config/i386/sse.md: Add V8BF/V16BF/V32BF to mode iterator FMAMODEM. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-512-bf-vector-fma-1.c: New test. * gcc.target/i386/avx10_2-bf-vector-fma-1.c: New test.
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@ -5677,7 +5677,10 @@
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(HF "TARGET_AVX512FP16")
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(V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
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(V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
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(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")])
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(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
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(V8BF "TARGET_AVX10_2_256")
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(V16BF "TARGET_AVX10_2_256")
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(V32BF "TARGET_AVX10_2_512")])
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(define_expand "fma<mode>4"
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[(set (match_operand:FMAMODEM 0 "register_operand")
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34
gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-fma-1.c
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gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-fma-1.c
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/* { dg-do compile } */
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/* { dg-options "-mavx10.2-512 -O2" } */
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/* { dg-final { scan-assembler-times "vfmadd132nepbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfmsub132nepbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfnmadd132nepbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfnmsub132nepbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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typedef __bf16 v32bf __attribute__ ((__vector_size__ (64)));
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v32bf
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foo_madd (v32bf a, v32bf b, v32bf c)
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{
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return a * b + c;
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}
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v32bf
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foo_msub (v32bf a, v32bf b, v32bf c)
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{
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return a * b - c;
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}
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v32bf
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foo_nmadd (v32bf a, v32bf b, v32bf c)
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{
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return -a * b + c;
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}
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v32bf
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foo_nmsub (v32bf a, v32bf b, v32bf c)
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{
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return -a * b - c;
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}
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63
gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-fma-1.c
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63
gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-fma-1.c
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@ -0,0 +1,63 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx10.2 -O2" } */
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/* { dg-final { scan-assembler-times "vfmadd132nepbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfmsub132nepbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfnmadd132nepbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfnmsub132nepbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfmadd132nepbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfmsub132nepbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfnmadd132nepbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfnmsub132nepbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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typedef __bf16 v16bf __attribute__ ((__vector_size__ (32)));
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typedef __bf16 v8bf __attribute__ ((__vector_size__ (16)));
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v16bf
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foo_madd_256 (v16bf a, v16bf b, v16bf c)
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{
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return a * b + c;
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}
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v16bf
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foo_msub_256 (v16bf a, v16bf b, v16bf c)
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{
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return a * b - c;
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}
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v16bf
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foo_nmadd_256 (v16bf a, v16bf b, v16bf c)
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{
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return -a * b + c;
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}
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v16bf
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foo_nmsub_256 (v16bf a, v16bf b, v16bf c)
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{
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return -a * b - c;
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}
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v8bf
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foo_madd_128 (v8bf a, v8bf b, v8bf c)
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{
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return a * b + c;
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}
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v8bf
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foo_msub_128 (v8bf a, v8bf b, v8bf c)
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{
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return a * b - c;
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}
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v8bf
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foo_nmadd_128 (v8bf a, v8bf b, v8bf c)
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{
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return -a * b + c;
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}
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v8bf
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foo_nmsub_128 (v8bf a, v8bf b, v8bf c)
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{
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return -a * b - c;
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}
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