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alpha: Cleanup sign extension patterns.
Don't bother implementing sub-word sign-extensions for !BWX, since we need to use DImode intermediates anyway. From-SVN: r171435
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Richard Henderson
Richard Henderson
parent
84ee3e269a
commit
6aba5cb489
@ -1,3 +1,10 @@
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2011-02-24 Richard Henderson <rth@redhat.com>
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* config/alpha/alpha.md (extendqihi2): Implement for BWX only.
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(extendqisi2, extendhisi2): Likewise.
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(extendqidi2): Simplify BWX/non-BWX expansions.
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(extendhidi2): Similarly.
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2011-02-24 Richard Henderson <rth@redhat.com>
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* config/alpha/alpha.md (attribute isa): New.
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@ -1413,194 +1413,103 @@
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"sra %r1,%2,%0"
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[(set_attr "type" "shift")])
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(define_expand "extendqihi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:QI 1 "some_operand" "")
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(const_int 56)))
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(set (match_operand:HI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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(const_int 56)))]
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""
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{
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if (TARGET_BWX)
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{
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emit_insn (gen_extendqihi2x (operands[0],
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force_reg (QImode, operands[1])));
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DONE;
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}
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/* If we have an unaligned MEM, extend to DImode (which we do
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specially) and then copy to the result. */
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if (unaligned_memory_operand (operands[1], HImode))
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{
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rtx temp = gen_reg_rtx (DImode);
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emit_insn (gen_extendqidi2 (temp, operands[1]));
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emit_move_insn (operands[0], gen_lowpart (HImode, temp));
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DONE;
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}
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operands[0] = gen_lowpart (DImode, operands[0]);
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operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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})
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(define_insn "extendqidi2x"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextb %1,%0"
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[(set_attr "type" "shift")])
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(define_insn "extendhidi2x"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextw %1,%0"
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[(set_attr "type" "shift")])
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(define_insn "extendqisi2x"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextb %1,%0"
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[(set_attr "type" "shift")])
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(define_insn "extendhisi2x"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextw %1,%0"
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[(set_attr "type" "shift")])
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(define_insn "extendqihi2x"
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(define_insn "extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextb %1,%0"
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[(set_attr "type" "shift")])
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(define_expand "extendqisi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:QI 1 "some_operand" "")
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(const_int 56)))
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(set (match_operand:SI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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(const_int 56)))]
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""
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{
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if (TARGET_BWX)
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{
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emit_insn (gen_extendqisi2x (operands[0],
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force_reg (QImode, operands[1])));
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DONE;
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}
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/* If we have an unaligned MEM, extend to a DImode form of
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the result (which we do specially). */
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if (unaligned_memory_operand (operands[1], QImode))
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{
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rtx temp = gen_reg_rtx (DImode);
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emit_insn (gen_extendqidi2 (temp, operands[1]));
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emit_move_insn (operands[0], gen_lowpart (SImode, temp));
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DONE;
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}
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operands[0] = gen_lowpart (DImode, operands[0]);
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operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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})
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(define_insn "extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextb %1,%0"
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[(set_attr "type" "shift")])
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(define_expand "extendqidi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:QI 1 "some_operand" "")
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(const_int 56)))
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(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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(const_int 56)))]
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[(set (match_operand:DI 0 "register_operand" "")
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(sign_extend:DI (match_operand:QI 1 "some_operand" "")))]
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""
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{
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if (TARGET_BWX)
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operands[1] = force_reg (QImode, operands[1]);
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else
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{
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emit_insn (gen_extendqidi2x (operands[0],
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force_reg (QImode, operands[1])));
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rtx x, t1, t2, i56;
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if (unaligned_memory_operand (operands[1], QImode))
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{
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x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
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alpha_set_memflags (x, operands[1]);
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emit_insn (x);
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DONE;
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}
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t1 = gen_reg_rtx (DImode);
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t2 = gen_reg_rtx (DImode);
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i56 = GEN_INT (56);
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x = gen_lowpart (DImode, force_reg (QImode, operands[1]));
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emit_move_insn (t1, x);
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emit_insn (gen_ashldi3 (t2, t1, i56));
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emit_insn (gen_ashrdi3 (operands[0], t2, i56));
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DONE;
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}
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if (unaligned_memory_operand (operands[1], QImode))
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{
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rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
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alpha_set_memflags (seq, operands[1]);
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emit_insn (seq);
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DONE;
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}
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operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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})
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(define_expand "extendhisi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:HI 1 "some_operand" "")
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(const_int 48)))
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(set (match_operand:SI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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(const_int 48)))]
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""
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{
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if (TARGET_BWX)
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{
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emit_insn (gen_extendhisi2x (operands[0],
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force_reg (HImode, operands[1])));
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DONE;
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}
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(define_insn "*extendqidi2_bwx"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextb %1,%0"
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[(set_attr "type" "shift")])
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/* If we have an unaligned MEM, extend to a DImode form of
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the result (which we do specially). */
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if (unaligned_memory_operand (operands[1], HImode))
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{
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rtx temp = gen_reg_rtx (DImode);
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emit_insn (gen_extendhidi2 (temp, operands[1]));
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emit_move_insn (operands[0], gen_lowpart (SImode, temp));
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DONE;
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}
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operands[0] = gen_lowpart (DImode, operands[0]);
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operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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})
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(define_insn "extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextw %1,%0"
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[(set_attr "type" "shift")])
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(define_expand "extendhidi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:HI 1 "some_operand" "")
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(const_int 48)))
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(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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(const_int 48)))]
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[(set (match_operand:DI 0 "register_operand" "")
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(sign_extend:DI (match_operand:HI 1 "some_operand" "")))]
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""
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{
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if (TARGET_BWX)
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operands[1] = force_reg (HImode, operands[1]);
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else
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{
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emit_insn (gen_extendhidi2x (operands[0],
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force_reg (HImode, operands[1])));
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rtx x, t1, t2, i48;
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if (unaligned_memory_operand (operands[1], HImode))
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{
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x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
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alpha_set_memflags (x, operands[1]);
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emit_insn (x);
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DONE;
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}
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t1 = gen_reg_rtx (DImode);
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t2 = gen_reg_rtx (DImode);
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i48 = GEN_INT (48);
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x = gen_lowpart (DImode, force_reg (HImode, operands[1]));
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emit_move_insn (t1, x);
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emit_insn (gen_ashldi3 (t2, t1, i48));
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emit_insn (gen_ashrdi3 (operands[0], t2, i48));
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DONE;
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}
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if (unaligned_memory_operand (operands[1], HImode))
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{
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rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
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alpha_set_memflags (seq, operands[1]);
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emit_insn (seq);
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DONE;
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}
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operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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})
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(define_insn "*extendhidi2_bwx"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
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"TARGET_BWX"
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"sextw %1,%0"
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[(set_attr "type" "shift")])
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;; Here's how we sign extend an unaligned byte and halfword. Doing this
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;; as a pattern saves one instruction. The code is similar to that for
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;; the unaligned loads (see below).
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