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i386: Add V2SFmode NEG, ABS and logic insn patterns [PR95046]
gcc/ChangeLog: PR target/95046 * config/i386/mmx.md (<code>v2sf2): New insn pattern. (*mmx_<code>v2sf2): New insn_and_split pattern. (*mmx_nabsv2sf2): Ditto. (*mmx_andnotv2sf3): New insn pattern. (*mmx_<code>v2sf3): Ditto. * config/i386/i386.md (absneg_op): New code attribute. * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode. (ix86_build_signbit_mask): Ditto. testsuite/ChangeLog: PR target/95046 * gcc.target/i386/pr95046-2.c: New test.
This commit is contained in:
Uros Bizjak
parent
998fbe9f1f
commit
6416f67273
@ -15091,6 +15091,7 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value)
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case E_V16SFmode:
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case E_V8SFmode:
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case E_V4SFmode:
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case E_V2SFmode:
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case E_V8DFmode:
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case E_V4DFmode:
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case E_V2DFmode:
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@ -15131,6 +15132,7 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
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case E_V4SImode:
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case E_V8SFmode:
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case E_V4SFmode:
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case E_V2SFmode:
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vec_mode = mode;
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imode = SImode;
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break;
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@ -954,6 +954,9 @@
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;; Mapping of abs neg operators
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(define_code_iterator absneg [abs neg])
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;; Mapping of abs neg operators to logic operation
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(define_code_attr absneg_op [(abs "and") (neg "xor")])
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;; Base name for x87 insn mnemonic.
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(define_code_attr absneg_mnemonic [(abs "fabs") (neg "fchs")])
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@ -238,6 +238,40 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "<code>v2sf2"
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[(set (match_operand:V2SF 0 "register_operand")
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(absneg:V2SF
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(match_operand:V2SF 1 "register_operand")))]
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"TARGET_MMX_WITH_SSE"
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"ix86_expand_fp_absneg_operator (<CODE>, V2SFmode, operands); DONE;")
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(define_insn_and_split "*mmx_<code>v2sf2"
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[(set (match_operand:V2SF 0 "register_operand" "=x,x")
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(absneg:V2SF
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(match_operand:V2SF 1 "register_operand" "%0,x")))
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(use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
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"TARGET_MMX_WITH_SSE"
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(<absneg_op>:V2SF (match_dup 1) (match_dup 2)))]
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""
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[(set_attr "isa" "noavx,avx")])
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(define_insn_and_split "*mmx_nabsv2sf2"
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[(set (match_operand:V2SF 0 "register_operand" "=x,x")
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(neg:V2SF
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(abs:V2SF
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(match_operand:V2SF 1 "register_operand" "%0,x"))))
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(use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
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"TARGET_MMX_WITH_SSE"
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(ior:V2SF (match_dup 1) (match_dup 2)))]
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""
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[(set_attr "isa" "noavx,avx")])
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(define_expand "mmx_addv2sf3"
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[(set (match_operand:V2SF 0 "register_operand")
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(plus:V2SF
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@ -591,6 +625,41 @@
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "V2SF")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel single-precision floating point logical operations
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "*mmx_andnotv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=x,x")
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(and:V2SF
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(not:V2SF
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(match_operand:V2SF 1 "register_operand" "0,x"))
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(match_operand:V2SF 2 "register_operand" "x,x")))]
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"TARGET_MMX_WITH_SSE"
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"@
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andps\t{%2, %0|%0, %2}
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vandps\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "V4SF")])
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(define_insn "*mmx_<code>v2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=x,x")
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(any_logic:V2SF
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(match_operand:V2SF 1 "register_operand" "%0,x")
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(match_operand:V2SF 2 "register_operand" "x,x")))]
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"TARGET_MMX_WITH_SSE"
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"@
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<logic>ps\t{%2, %0|%0, %2}
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v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "V4SF")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel single-precision floating point conversion operations
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@ -1,3 +1,8 @@
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2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
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PR target/95046
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* gcc.target/i386/pr95046-2.c: New test.
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2020-05-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
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* gcc.c-torture/execute/noinit-attribute.c: Skip for msp430
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@ -1,4 +1,4 @@
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/* PR target/94942 */
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/* PR target/95046 */
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O3 -ffast-math -msse2" } */
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@ -12,7 +12,7 @@ test_plus (void)
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r[i] = a[i] + b[i];
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}
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/* { dg-final { scan-assembler "addps" } } */
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/* { dg-final { scan-assembler "\tv?addps" } } */
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void
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test_minus (void)
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@ -21,7 +21,7 @@ test_minus (void)
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r[i] = a[i] - b[i];
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}
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/* { dg-final { scan-assembler "subps" } } */
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/* { dg-final { scan-assembler "\tv?subps" } } */
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void
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test_mult (void)
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@ -30,7 +30,7 @@ test_mult (void)
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r[i] = a[i] * b[i];
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}
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/* { dg-final { scan-assembler "mulps" } } */
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/* { dg-final { scan-assembler "\tv?mulps" } } */
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void
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test_min (void)
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@ -39,7 +39,7 @@ test_min (void)
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r[i] = a[i] < b[i] ? a[i] : b[i];
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}
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/* { dg-final { scan-assembler "minps" } } */
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/* { dg-final { scan-assembler "\tv?minps" } } */
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void
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test_max (void)
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@ -48,7 +48,7 @@ test_max (void)
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r[i] = a[i] > b[i] ? a[i] : b[i];
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}
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/* { dg-final { scan-assembler "maxps" } } */
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/* { dg-final { scan-assembler "\tv?maxps" } } */
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float sqrtf (float);
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@ -59,4 +59,4 @@ test_sqrt (void)
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r[i] = sqrtf (a[i]);
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}
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/* { dg-final { scan-assembler "sqrtps" } } */
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/* { dg-final { scan-assembler "\tv?sqrtps" } } */
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35
gcc/testsuite/gcc.target/i386/pr95046-2.c
Normal file
35
gcc/testsuite/gcc.target/i386/pr95046-2.c
Normal file
@ -0,0 +1,35 @@
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/* PR target/95046 */
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O3 -msse2" } */
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float r[2], a[2];
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float fabsf (float);
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void
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test_abs (void)
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{
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for (int i = 0; i < 2; i++)
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r[i] = fabsf (a[i]);
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}
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/* { dg-final { scan-assembler "\tv?andps" } } */
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void
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test_neg (void)
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{
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for (int i = 0; i < 2; i++)
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r[i] = -a[i];
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}
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/* { dg-final { scan-assembler "\tv?xorps" } } */
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void
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test_nabs (void)
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{
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for (int i = 0; i < 2; i++)
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r[i] = -fabsf (a[i]);
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}
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/* { dg-final { scan-assembler "\tv?orps" } } */
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