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On AArch64 the UXTB and UXTH instructions are aliases of UBFM,

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which does a shift as part of its operation. An AND immediate is a
simpler operation, and might be faster on some implementations, so
it is better to emit this this instead of UBFM.

Benchmarking showed no difference on implementations where UBFM has
the same performance as AND, and minor speedups across several
benchmarks on an implementation where UBFM is slower than AND.

Bootstrapped and tested on aarch64-none-elf.

    gcc/
	* config/aarch64/aarch64.md
	(zero_extend<SHORT:mode><GPI:mode>2_aarch64): Change output
	statement and type.
	(<optab>qihi2_aarch64): Likewise, and split into two.
	(extendqihi2_aarch64): New.
	(zero_extendqihi2_aarch64): New.
	* config/aarch64/iterators.md (ldrxt): Remove.
	* config/aarch64/aarch64.c (aarch64_rtx_costs): Change cost of
	uxtb/uxth.

From-SVN: r238821
This commit is contained in:
Wilco Dijkstra 2016-07-28 14:34:41 +00:00
parent dde23f43f9
commit 63715e5e78
4 changed files with 31 additions and 11 deletions
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13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
2016-07-28 Kristina Martsenko <kristina.martsenko@arm.com>
2016-07-28 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.md
(zero_extend<SHORT:mode><GPI:mode>2_aarch64): Change output
statement and type.
(<optab>qihi2_aarch64): Likewise, and split into two.
(extendqihi2_aarch64): New.
(zero_extendqihi2_aarch64): New.
* config/aarch64/iterators.md (ldrxt): Remove.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Change cost of
uxtb/uxth.
2016-07-28 Kristina Martsenko <kristina.martsenko@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Fix cost of zero extend.

4
gcc/config/aarch64/aarch64.c
View File

@ -6838,8 +6838,8 @@ cost_plus:
}
else
{
/* UXTB/UXTH. */
*cost += extra_cost->alu.extend;
/* We generate an AND instead of UXTB/UXTH. */
*cost += extra_cost->alu.logical;
}
}
return false;

22
gcc/config/aarch64/aarch64.md
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@ -1577,10 +1577,10 @@
(zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))]
""
"@
uxt<SHORT:size>\t%<GPI:w>0, %w1
and\t%<GPI:w>0, %<GPI:w>1, <SHORT:short_mask>
ldr<SHORT:size>\t%w0, %1
ldr\t%<SHORT:size>0, %1"
[(set_attr "type" "extend,load1,load1")]
[(set_attr "type" "logic_imm,load1,load1")]
)
(define_expand "<optab>qihi2"
@ -1589,16 +1589,26 @@
""
)
(define_insn "*<optab>qihi2_aarch64"
(define_insn "*extendqihi2_aarch64"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(ANY_EXTEND:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
""
"@
<su>xtb\t%w0, %w1
<ldrxt>b\t%w0, %1"
sxtb\t%w0, %w1
ldrsb\t%w0, %1"
[(set_attr "type" "extend,load1")]
)
(define_insn "*zero_extendqihi2_aarch64"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
""
"@
and\t%w0, %w1, 255
ldrb\t%w0, %1"
[(set_attr "type" "logic_imm,load1")]
)
;; -------------------------------------------------------------------
;; Simple arithmetic
;; -------------------------------------------------------------------

3
gcc/config/aarch64/iterators.md
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@ -942,9 +942,6 @@
;; Similar, but when not(op)
(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
;; Sign- or zero-extending load
(define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
;; Sign- or zero-extending data-op
(define_code_attr su [(sign_extend "s") (zero_extend "u")
(sign_extract "s") (zero_extract "u")