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support for AMD clzero isa.

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gcc/ChangeLog
2015-12-06  Victoria Stepanyan  <victoria.stepanyan@amd.com>

        * common/config/i386/i386-common.c
        (OPTION_MASK_ISA_CLZERO_SET): New.
        (ix86_handle_option): Handle clzero.
        * config.gcc (i[34567]86-*-*): Add clzerointrin.h,
        (x86_64-*-*): Likewise.
        * config/i386/clzerointrin.h: New header.
        * config/i386/cpuid.h (bit_CLZERO):  Define.
        * config/i386/driver-i386.c (host_detect_local_cpu): Detect
        CLZERO support.
        * config/i386/i386.opt (clzero): New.
        * config/i386/i386-c.c: Define __CLZERO__ if needed.
        * config/i386/i386.c (ix86_target_string): Define -mclzero option.
        (PTA_CLZERO): New.
        (ix86_option_override_internal): Handle new option.
        (processor_alias_table): Added PTA_CLZERO.
        (ix86_valid_target_attribute_inner_p): Add OPT_mclzero.
        (ix86_builtins): Add IX86_BUILTIN_CLZERO, IX86_BUILTIN_CLZERO.
        (ix86_expand_builtin): Handle IX86_BUILTIN_CLZERO and
        IX86_BUILTIN_CLZERO  built-ins.
        * config/i386/i386.h (TARGET_CLZERO):  New.
        * config/i386/i386.md (unspecv): Add UNSPEC_CLZERO.
        (clzero):  New pattern.
        (clzero_<mode>): New pattern.
        * config/i386/x86intrin.h: Include clzerointrin.h.
        * doc/extend.texi: Document clzero builtins.
        * doc/invoke.texi: Document -mclzero option.

gcc/testsuite/ChangeLog
2015-12-06  Victoria Stepanyan  <victoria.stepanyan@amd.com>

        * gcc.target/i386/clzero.c: New.
        * gcc.target/i386/sse-12.c: Add -mclzero.
        * gcc.target/i386/sse-13.c: Ditto.
        * gcc.target/i386/sse-14.c: Ditto.
        * gcc.target/i386/sse-22.c: Ditto.
        * gcc.target/i386/sse-23.c: Ditto.
        * g++.dg/other/i386-2.C: Ditto.
        * g++.dg/other/i386-3.C: Ditto.

From-SVN: r231340
This commit is contained in:
Victoria Stepanyan 2015-12-06 17:02:48 +00:00 committed by Venkataramanan Kumar
parent 2097a8906f
commit 62e56a0d65
19 changed files with 168 additions and 13 deletions
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29
gcc/ChangeLog
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@ -1,3 +1,32 @@
2015-12-06 Victoria Stepanyan <victoria.stepanyan@amd.com>
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_CLZERO_SET): New.
(ix86_handle_option): Handle clzero.
* config.gcc (i[34567]86-*-*): Add clzerointrin.h,
(x86_64-*-*): Likewise.
* config/i386/clzerointrin.h: New header.
* config/i386/cpuid.h (bit_CLZERO): Define.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
CLZERO support.
* config/i386/i386.opt (clzero): New.
* config/i386/i386-c.c: Define __CLZERO__ if needed.
* config/i386/i386.c (ix86_target_string): Define -mclzero option.
(PTA_CLZERO): New.
(ix86_option_override_internal): Handle new option.
(processor_alias_table): Added PTA_CLZERO.
(ix86_valid_target_attribute_inner_p): Add OPT_mclzero.
(ix86_builtins): Add IX86_BUILTIN_CLZERO, IX86_BUILTIN_CLZERO.
(ix86_expand_builtin): Handle IX86_BUILTIN_CLZERO and
IX86_BUILTIN_CLZERO built-ins.
* config/i386/i386.h (TARGET_CLZERO): New.
* config/i386/i386.md (unspecv): Add UNSPEC_CLZERO.
(clzero): New pattern.
(clzero_<mode>): New pattern.
* config/i386/x86intrin.h: Include clzerointrin.h.
* doc/extend.texi: Document clzero builtins.
* doc/invoke.texi: Document -mclzero option.
2015-12-05 Jan Hubicka <hubicka@ucw.cz>
* ipa-icf.c (sem_function::merge): Check that local_original exists.

16
gcc/common/config/i386/i386-common.c
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@ -128,6 +128,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_F16C_SET \
(OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
#define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
/* Define a set of ISAs which aren't available when a given ISA is
disabled. MMX and SSE ISAs are handled separately. */
@ -188,6 +189,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_PCOMMIT_UNSET OPTION_MASK_ISA_PCOMMIT
#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
#define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
#define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@ -947,6 +949,20 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
case OPT_mclzero:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLZERO_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLZERO_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLZERO_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLZERO_UNSET;
}
return true;
/* Comes from final.c -- no real reason to change it. */
#define MAX_CODE_ALIGN 16

4
gcc/config.gcc
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@ -372,7 +372,7 @@ i[34567]86-*-*)
xsavesintrin.h avx512dqintrin.h avx512bwintrin.h
avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h
avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h
avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h mwaitxintrin.h"
avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h mwaitxintrin.h clzerointrin.h"
;;
x86_64-*-*)
cpu_type=i386
@ -393,7 +393,7 @@ x86_64-*-*)
xsavesintrin.h avx512dqintrin.h avx512bwintrin.h
avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h
avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h
avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h mwaitxintrin.h"
avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h mwaitxintrin.h clzerointrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h

44
gcc/config/i386/clzerointrin.h Normal file
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@ -0,0 +1,44 @@
/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _CLZEROINTRIN_H_INCLUDED
#define _CLZEROINTRIN_H_INCLUDED
#ifndef __CLZERO__
#pragma GCC push_options
#pragma GCC target("clzero")
#define __DISABLE_CLZERO__
#endif /* __CLZERO__ */
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_clzero (void * __I)
{
__builtin_ia32_clzero (__I);
}
#ifdef __DISABLE_CLZERO__
#undef __DISABLE_CLZERO__
#pragma GCC pop_options
#endif /* __DISABLE_CLZERO__ */
#endif /* _CLZEROINTRIN_H_INCLUDED */

2
gcc/config/i386/i386-c.c
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@ -439,6 +439,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__CLWB__");
if (isa_flag & OPTION_MASK_ISA_MWAITX)
def_or_undef (parse_in, "__MWAITX__");
if (isa_flag & OPTION_MASK_ISA_CLZERO)
def_or_undef (parse_in, "__CLZERO__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");

17
gcc/config/i386/i386.c
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@ -2501,6 +2501,7 @@ static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx, rtx);
static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
static rtx (*ix86_gen_monitorx) (rtx, rtx, rtx);
static rtx (*ix86_gen_clzero) (rtx);
static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
static rtx (*ix86_gen_allocate_stack_worker) (rtx, rtx);
static rtx (*ix86_gen_adjust_stack_and_probe) (rtx, rtx, rtx);
@ -5370,6 +5371,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_gen_probe_stack_range = gen_probe_stack_rangedi;
ix86_gen_monitor = gen_sse3_monitor_di;
ix86_gen_monitorx = gen_monitorx_di;
ix86_gen_clzero = gen_clzero_di;
}
else
{
@ -5383,6 +5385,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_gen_probe_stack_range = gen_probe_stack_rangesi;
ix86_gen_monitor = gen_sse3_monitor_si;
ix86_gen_monitorx = gen_monitorx_si;
ix86_gen_clzero = gen_clzero_si;
}
#ifdef USE_IX86_CLD
@ -5915,6 +5918,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
IX86_ATTR_ISA ("clwb", OPT_mclwb),
IX86_ATTR_ISA ("pcommit", OPT_mpcommit),
IX86_ATTR_ISA ("mwaitx", OPT_mmwaitx),
IX86_ATTR_ISA ("clzero", OPT_mclzero),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
@ -30009,6 +30013,7 @@ enum ix86_builtins
IX86_BUILTIN_MONITOR,
IX86_BUILTIN_MWAIT,
IX86_BUILTIN_CLZERO,
/* SSSE3. */
IX86_BUILTIN_PHADDW,
@ -35893,6 +35898,10 @@ ix86_init_mmx_sse_builtins (void)
def_builtin (OPTION_MASK_ISA_MWAITX, "__builtin_ia32_mwaitx",
VOID_FTYPE_UNSIGNED_UNSIGNED_UNSIGNED, IX86_BUILTIN_MWAITX);
/* CLZERO. */
def_builtin (OPTION_MASK_ISA_CLZERO, "__builtin_ia32_clzero",
VOID_FTYPE_PCVOID, IX86_BUILTIN_CLZERO);
/* Add FMA4 multi-arg argument instructions */
for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
{
@ -40663,6 +40672,14 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
emit_insn (gen_mwaitx (op0, op1, op2));
return 0;
case IX86_BUILTIN_CLZERO:
arg0 = CALL_EXPR_ARG (exp, 0);
op0 = expand_normal (arg0);
if (!REG_P (op0))
op0 = ix86_zero_extend_to_Pmode (op0);
emit_insn (ix86_gen_clzero (op0));
return 0;
case IX86_BUILTIN_VEC_INIT_V2SI:
case IX86_BUILTIN_VEC_INIT_V4HI:
case IX86_BUILTIN_VEC_INIT_V8QI:

12
gcc/config/i386/i386.md
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@ -265,6 +265,9 @@
UNSPECV_MONITORX
UNSPECV_MWAITX
;; For CLZERO support
UNSPECV_CLZERO
])
;; Constants to represent rounding modes in the ROUND instruction
@ -19120,6 +19123,15 @@
[(set (attr "length")
(symbol_ref ("(Pmode != word_mode) + 3")))])
;; CLZERO
(define_insn "clzero_<mode>"
[(unspec_volatile [(match_operand: P 0 "register_operand" "a")]
UNSPECV_CLZERO)]
"TARGET_CLZERO"
"clzero"
[(set_attr "length" "3")
(set_attr "memory" "unknown")])
;; MPX instructions
(define_expand "<mode>_mk"

8
gcc/config/i386/i386.opt
View File

@ -751,10 +751,6 @@ mclflushopt
Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
Support CLFLUSHOPT instructions.
mclzero
Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save
Support CLZERO instructions.
mclwb
Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
Support CLWB instruction.
@ -876,6 +872,10 @@ mmwaitx
Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags) Save
Support MWAITX and MONITORX built-in functions and code generation.
mclzero
Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save
Support CLZERO built-in functions and code generation.
mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
Use given stack-protector guard.

2
gcc/config/i386/x86intrin.h
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@ -93,6 +93,8 @@
#include <mwaitxintrin.h>
#include <clzerointrin.h>
#endif /* __iamcu__ */
#endif /* _X86INTRIN_H_INCLUDED */

6
gcc/doc/extend.texi
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@ -18337,6 +18337,12 @@ void __builtin_ia32_monitorx (void *, unsigned int, unsigned int)
void __builtin_ia32_mwaitx (unsigned int, unsigned int, unsigned int)
@end smallexample
The following built-in functions are available when @option{-mclzero} is used.
All of them generate the machine instruction that is part of the name.
@smallexample
void __builtin_i32_clzero (void *)
@end smallexample
@node x86 transactional memory intrinsics
@subsection x86 Transactional Memory Intrinsics

5
gcc/doc/invoke.texi
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@ -1101,7 +1101,7 @@ See RS/6000 and PowerPC Options.
-mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
-mprefetchwt1 -mclflushopt -mxsavec -mxsaves @gol
-msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol
-mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx -mthreads @gol
-mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx -mclzero -mthreads @gol
-mms-bitfields -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
-mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol
@ -23216,6 +23216,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@need 200
@itemx -mmwaitx
@opindex mmwaitx
@need 200
@itemx -mclzero
@opindex mclzero
These switches enable the use of instructions in the MMX, SSE,
SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,

11
gcc/testsuite/ChangeLog
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@ -1,3 +1,14 @@
2015-12-06 Victoria Stepanyan <victoria.stepanyan@amd.com>
* gcc.target/i386/clzero.c: New.
* gcc.target/i386/sse-12.c: Add -mclzero.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
2015-12-05 David Edelsohn <dje.gcc@gmail.com>
* gcc.target/powerpc/recip-sqrtf.c: New test.

2
gcc/testsuite/g++.dg/other/i386-2.C
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@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx" } */
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx -mclzero" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,

2
gcc/testsuite/g++.dg/other/i386-3.C
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@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx" } */
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx -mclzero" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,

13
gcc/testsuite/gcc.target/i386/clzero.c Normal file
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@ -0,0 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mclzero" } */
/* Verify that they work in both 32bit and 64bit. */
#include <x86intrin.h>
void
foo (void *k)
{
_mm_clzero (k);
}

2
gcc/testsuite/gcc.target/i386/sse-12.c
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@ -3,7 +3,7 @@
popcntintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx" } */
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx -mclzero" } */
#include <x86intrin.h>

2
gcc/testsuite/gcc.target/i386/sse-13.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx" } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx -mclzero" } */
#include <mm_malloc.h>

2
gcc/testsuite/gcc.target/i386/sse-14.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx" } */
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx -mclzero" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>

2
gcc/testsuite/gcc.target/i386/sse-23.c
View File

@ -594,6 +594,6 @@
#define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D)
#define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D)
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,clwb,pcommit,mwaitx")
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,clwb,pcommit,mwaitx,clzero")
#include <x86intrin.h>