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re PR tree-optimization/63563 (ICE: in vectorizable_store, at tree-vect-stmts.c:5106 with -mavx2)
PR tree-optimization/63563 * tree-vect-data-refs.c (vect_analyze_data_ref_accesses): Bail out if either dra or drb stmts are not normal loads/stores. * gcc.target/i386/pr63563.c: New test. From-SVN: r216507
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2014-10-21 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/63563
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* tree-vect-data-refs.c (vect_analyze_data_ref_accesses): Bail out
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if either dra or drb stmts are not normal loads/stores.
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2014-10-21 Ilya Tocar <ilya.tocar@intel.com>
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* config/i386/i386.c (expand_vec_perm_1): Fix
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@ -1,3 +1,8 @@
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2014-10-21 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/63563
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* gcc.target/i386/pr63563.c: New test.
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2014-10-20 Richard Biener <rguenther@suse.de>
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* gcc.dg/tree-ssa/slsr-19.c: Make robust against operand order changes.
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17
gcc/testsuite/gcc.target/i386/pr63563.c
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gcc/testsuite/gcc.target/i386/pr63563.c
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/* PR tree-optimization/63563 */
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/* { dg-do compile } */
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/* { dg-options "-O3 -mavx2" } */
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struct A { unsigned long a, b, c, d; } a[1024] = { { 0, 1, 2, 3 } }, b;
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void
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foo (void)
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{
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int i;
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for (i = 0; i < 1024; i++)
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{
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a[i].a = a[i].b = a[i].c = b.c;
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if (a[i].d)
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a[i].d = b.d;
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}
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}
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@ -2551,11 +2551,14 @@ vect_analyze_data_ref_accesses (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo)
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over them. The we can just skip ahead to the next DR here. */
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/* Check that the data-refs have same first location (except init)
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and they are both either store or load (not load and store). */
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and they are both either store or load (not load and store,
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not masked loads or stores). */
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if (DR_IS_READ (dra) != DR_IS_READ (drb)
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|| !operand_equal_p (DR_BASE_ADDRESS (dra),
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DR_BASE_ADDRESS (drb), 0)
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|| !dr_equal_offsets_p (dra, drb))
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|| !dr_equal_offsets_p (dra, drb)
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|| !gimple_assign_single_p (DR_STMT (dra))
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|| !gimple_assign_single_p (DR_STMT (drb)))
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break;
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/* Check that the data-refs have the same constant size and step. */
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