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[2/77] Add an E_ prefix to case statements

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All case statements need to be updated to use the prefixed names,
since the unprefixed names will eventually not be integer constant
expressions.  This patch does a mechanical substitution over the whole
codebase.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type):
	Prefix mode names with E_ in case statements.
	* config/aarch64/aarch64-elf.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
	* config/aarch64/aarch64.c (aarch64_split_simd_combine): Likewise.
	(aarch64_split_simd_move): Likewise.
	(aarch64_gen_storewb_pair): Likewise.
	(aarch64_gen_loadwb_pair): Likewise.
	(aarch64_gen_store_pair): Likewise.
	(aarch64_gen_load_pair): Likewise.
	(aarch64_get_condition_code_1): Likewise.
	(aarch64_constant_pool_reload_icode): Likewise.
	(get_rsqrte_type): Likewise.
	(get_rsqrts_type): Likewise.
	(get_recpe_type): Likewise.
	(get_recps_type): Likewise.
	(aarch64_gimplify_va_arg_expr): Likewise.
	(aarch64_simd_container_mode): Likewise.
	(aarch64_emit_load_exclusive): Likewise.
	(aarch64_emit_store_exclusive): Likewise.
	(aarch64_expand_compare_and_swap): Likewise.
	(aarch64_gen_atomic_cas): Likewise.
	(aarch64_emit_bic): Likewise.
	(aarch64_emit_atomic_swap): Likewise.
	(aarch64_emit_atomic_load_op): Likewise.
	(aarch64_evpc_trn): Likewise.
	(aarch64_evpc_uzp): Likewise.
	(aarch64_evpc_zip): Likewise.
	(aarch64_evpc_ext): Likewise.
	(aarch64_evpc_rev): Likewise.
	(aarch64_evpc_dup): Likewise.
	(aarch64_gen_ccmp_first): Likewise.
	(aarch64_gen_ccmp_next): Likewise.
	* config/alpha/alpha.c (alpha_scalar_mode_supported_p): Likewise.
	(alpha_emit_xfloating_libcall): Likewise.
	(emit_insxl): Likewise.
	(alpha_arg_type): Likewise.
	* config/arc/arc.c (arc_vector_mode_supported_p): Likewise.
	(arc_preferred_simd_mode): Likewise.
	(arc_secondary_reload): Likewise.
	(get_arc_condition_code): Likewise.
	(arc_print_operand): Likewise.
	(arc_legitimate_constant_p): Likewise.
	* config/arc/arc.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
	* config/arc/arc.md (casesi_load): Likewise.
	(casesi_compact_jump): Likewise.
	* config/arc/predicates.md (proper_comparison_operator): Likewise.
	(cc_use_register): Likewise.
	* config/arm/aout.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
	* config/arm/arm-builtins.c (arm_simd_builtin_std_type): Likewise.
	(arm_init_iwmmxt_builtins): Likewise.
	* config/arm/arm.c (thumb1_size_rtx_costs): Likewise.
	(neon_expand_vector_init): Likewise.
	(arm_attr_length_move_neon): Likewise.
	(maybe_get_arm_condition_code): Likewise.
	(arm_emit_vector_const): Likewise.
	(arm_preferred_simd_mode): Likewise.
	(arm_output_iwmmxt_tinsr): Likewise.
	(thumb1_output_casesi): Likewise.
	(thumb2_output_casesi): Likewise.
	(arm_emit_load_exclusive): Likewise.
	(arm_emit_store_exclusive): Likewise.
	(arm_expand_compare_and_swap): Likewise.
	(arm_evpc_neon_vuzp): Likewise.
	(arm_evpc_neon_vzip): Likewise.
	(arm_evpc_neon_vrev): Likewise.
	(arm_evpc_neon_vtrn): Likewise.
	(arm_evpc_neon_vext): Likewise.
	(arm_validize_comparison): Likewise.
	* config/arm/neon.md (neon_vc<cmp_op><mode>): Likewise.
	* config/avr/avr-c.c (avr_resolve_overloaded_builtin): Likewise.
	* config/avr/avr.c (avr_rtx_costs_1): Likewise.
	* config/c6x/c6x.c (c6x_vector_mode_supported_p): Likewise.
	(c6x_preferred_simd_mode): Likewise.
	* config/epiphany/epiphany.c (get_epiphany_condition_code): Likewise.
	(epiphany_rtx_costs): Likewise.
	* config/epiphany/predicates.md (proper_comparison_operator):
	Likewise.
	* config/frv/frv.c (condexec_memory_operand): Likewise.
	(frv_emit_move): Likewise.
	(output_move_single): Likewise.
	(output_condmove_single): Likewise.
	(frv_hard_regno_mode_ok): Likewise.
	(frv_matching_accg_mode): Likewise.
	* config/h8300/h8300.c (split_adds_subs): Likewise.
	(h8300_rtx_costs): Likewise.
	(h8300_print_operand): Likewise.
	(compute_mov_length): Likewise.
	(output_logical_op): Likewise.
	(compute_logical_op_length): Likewise.
	(compute_logical_op_cc): Likewise.
	(h8300_shift_needs_scratch_p): Likewise.
	(output_a_shift): Likewise.
	(compute_a_shift_length): Likewise.
	(compute_a_shift_cc): Likewise.
	(expand_a_rotate): Likewise.
	(output_a_rotate): Likewise.
	* config/i386/i386.c (classify_argument): Likewise.
	(function_arg_advance_32): Likewise.
	(function_arg_32): Likewise.
	(function_arg_64): Likewise.
	(function_value_64): Likewise.
	(ix86_gimplify_va_arg): Likewise.
	(ix86_legitimate_constant_p): Likewise.
	(put_condition_code): Likewise.
	(split_double_mode): Likewise.
	(ix86_avx256_split_vector_move_misalign): Likewise.
	(ix86_expand_vector_logical_operator): Likewise.
	(ix86_split_idivmod): Likewise.
	(ix86_expand_adjust_ufix_to_sfix_si): Likewise.
	(ix86_build_const_vector): Likewise.
	(ix86_build_signbit_mask): Likewise.
	(ix86_match_ccmode): Likewise.
	(ix86_cc_modes_compatible): Likewise.
	(ix86_expand_branch): Likewise.
	(ix86_expand_sse_cmp): Likewise.
	(ix86_expand_sse_movcc): Likewise.
	(ix86_expand_int_sse_cmp): Likewise.
	(ix86_expand_vec_perm_vpermi2): Likewise.
	(ix86_expand_vec_perm): Likewise.
	(ix86_expand_sse_unpack): Likewise.
	(ix86_expand_int_addcc): Likewise.
	(ix86_split_to_parts): Likewise.
	(ix86_vectorize_builtin_gather): Likewise.
	(ix86_vectorize_builtin_scatter): Likewise.
	(avx_vpermilp_parallel): Likewise.
	(inline_memory_move_cost): Likewise.
	(ix86_tieable_integer_mode_p): Likewise.
	(x86_maybe_negate_const_int): Likewise.
	(ix86_expand_vector_init_duplicate): Likewise.
	(ix86_expand_vector_init_one_nonzero): Likewise.
	(ix86_expand_vector_init_one_var): Likewise.
	(ix86_expand_vector_init_concat): Likewise.
	(ix86_expand_vector_init_interleave): Likewise.
	(ix86_expand_vector_init_general): Likewise.
	(ix86_expand_vector_set): Likewise.
	(ix86_expand_vector_extract): Likewise.
	(emit_reduc_half): Likewise.
	(ix86_emit_i387_round): Likewise.
	(ix86_mangle_type): Likewise.
	(ix86_expand_round_sse4): Likewise.
	(expand_vec_perm_blend): Likewise.
	(canonicalize_vector_int_perm): Likewise.
	(ix86_expand_vec_one_operand_perm_avx512): Likewise.
	(expand_vec_perm_1): Likewise.
	(expand_vec_perm_interleave3): Likewise.
	(expand_vec_perm_even_odd_pack): Likewise.
	(expand_vec_perm_even_odd_1): Likewise.
	(expand_vec_perm_broadcast_1): Likewise.
	(ix86_vectorize_vec_perm_const_ok): Likewise.
	(ix86_expand_vecop_qihi): Likewise.
	(ix86_expand_mul_widen_hilo): Likewise.
	(ix86_expand_sse2_abs): Likewise.
	(ix86_expand_pextr): Likewise.
	(ix86_expand_pinsr): Likewise.
	(ix86_preferred_simd_mode): Likewise.
	(ix86_simd_clone_compute_vecsize_and_simdlen): Likewise.
	* config/i386/sse.md (*andnot<mode>3): Likewise.
	(<mask_codefor><code><mode>3<mask_name>): Likewise.
	(*<code><mode>3): Likewise.
	* config/ia64/ia64.c (ia64_expand_vecint_compare): Likewise.
	(ia64_expand_atomic_op): Likewise.
	(ia64_arg_type): Likewise.
	(ia64_mode_to_int): Likewise.
	(ia64_scalar_mode_supported_p): Likewise.
	(ia64_vector_mode_supported_p): Likewise.
	(expand_vec_perm_broadcast): Likewise.
	* config/iq2000/iq2000.c (iq2000_move_1word): Likewise.
	(iq2000_function_arg_advance): Likewise.
	(iq2000_function_arg): Likewise.
	* config/m32c/m32c.c (m32c_preferred_reload_class): Likewise.
	* config/m68k/m68k.c (output_dbcc_and_branch): Likewise.
	(m68k_libcall_value): Likewise.
	(m68k_function_value): Likewise.
	(sched_attr_op_type): Likewise.
	* config/mcore/mcore.c (mcore_output_move): Likewise.
	* config/microblaze/microblaze.c (microblaze_function_arg_advance):
	Likewise.
	(microblaze_function_arg): Likewise.
	* config/mips/mips.c (mips16_build_call_stub): Likewise.
	(mips_print_operand): Likewise.
	(mips_mode_ok_for_mov_fmt_p): Likewise.
	(mips_vector_mode_supported_p): Likewise.
	(mips_preferred_simd_mode): Likewise.
	(mips_expand_vpc_loongson_even_odd): Likewise.
	(mips_expand_vec_unpack): Likewise.
	(mips_expand_vi_broadcast): Likewise.
	(mips_expand_vector_init): Likewise.
	(mips_expand_vec_reduc): Likewise.
	(mips_expand_msa_cmp): Likewise.
	* config/mips/mips.md (casesi_internal_mips16_<mode>): Likewise.
	* config/mn10300/mn10300.c (mn10300_print_operand): Likewise.
	(cc_flags_for_mode): Likewise.
	* config/msp430/msp430.c (msp430_print_operand): Likewise.
	* config/nds32/nds32-md-auxiliary.c (nds32_mem_format): Likewise.
	(nds32_output_casesi_pc_relative): Likewise.
	* config/nds32/nds32.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
	* config/nvptx/nvptx.c (nvptx_ptx_type_from_mode): Likewise.
	(nvptx_gen_unpack): Likewise.
	(nvptx_gen_pack): Likewise.
	(nvptx_gen_shuffle): Likewise.
	(nvptx_gen_wcast): Likewise.
	(nvptx_preferred_simd_mode): Likewise.
	* config/pa/pa.c (pa_secondary_reload): Likewise.
	* config/pa/predicates.md (base14_operand): Likewise.
	* config/powerpcspe/powerpcspe-c.c
	(altivec_resolve_overloaded_builtin): Likewise.
	* config/powerpcspe/powerpcspe.c (rs6000_setup_reg_addr_masks):
	Likewise.
	(rs6000_preferred_simd_mode): Likewise.
	(output_vec_const_move): Likewise.
	(rs6000_expand_vector_extract): Likewise.
	(rs6000_split_vec_extract_var): Likewise.
	(reg_offset_addressing_ok_p): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_emit_set_const): Likewise.
	(rs6000_const_vec): Likewise.
	(rs6000_emit_move): Likewise.
	(spe_build_register_parallel): Likewise.
	(rs6000_darwin64_record_arg_recurse): Likewise.
	(swap_selector_for_mode): Likewise.
	(spe_init_builtins): Likewise.
	(paired_init_builtins): Likewise.
	(altivec_init_builtins): Likewise.
	(do_load_for_compare): Likewise.
	(rs6000_generate_compare): Likewise.
	(rs6000_expand_float128_convert): Likewise.
	(emit_load_locked): Likewise.
	(emit_store_conditional): Likewise.
	(rs6000_output_function_epilogue): Likewise.
	(rs6000_handle_altivec_attribute): Likewise.
	(rs6000_function_value): Likewise.
	(emit_fusion_gpr_load): Likewise.
	(emit_fusion_p9_load): Likewise.
	(emit_fusion_p9_store): Likewise.
	* config/powerpcspe/predicates.md (easy_fp_constant): Likewise.
	(fusion_gpr_mem_load): Likewise.
	(fusion_addis_mem_combo_load): Likewise.
	(fusion_addis_mem_combo_store): Likewise.
	* config/rs6000/predicates.md (easy_fp_constant): Likewise.
	(fusion_gpr_mem_load): Likewise.
	(fusion_addis_mem_combo_load): Likewise.
	(fusion_addis_mem_combo_store): Likewise.
	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
	Likewise.
	* config/rs6000/rs6000-string.c (do_load_for_compare): Likewise.
	* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise.
	(rs6000_preferred_simd_mode): Likewise.
	(output_vec_const_move): Likewise.
	(rs6000_expand_vector_extract): Likewise.
	(rs6000_split_vec_extract_var): Likewise.
	(reg_offset_addressing_ok_p): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_emit_set_const): Likewise.
	(rs6000_const_vec): Likewise.
	(rs6000_emit_move): Likewise.
	(rs6000_darwin64_record_arg_recurse): Likewise.
	(swap_selector_for_mode): Likewise.
	(paired_init_builtins): Likewise.
	(altivec_init_builtins): Likewise.
	(rs6000_expand_float128_convert): Likewise.
	(emit_load_locked): Likewise.
	(emit_store_conditional): Likewise.
	(rs6000_output_function_epilogue): Likewise.
	(rs6000_handle_altivec_attribute): Likewise.
	(rs6000_function_value): Likewise.
	(emit_fusion_gpr_load): Likewise.
	(emit_fusion_p9_load): Likewise.
	(emit_fusion_p9_store): Likewise.
	* config/rx/rx.c (rx_gen_move_template): Likewise.
	(flags_from_mode): Likewise.
	* config/s390/predicates.md (s390_alc_comparison): Likewise.
	(s390_slb_comparison): Likewise.
	* config/s390/s390.c (s390_handle_vectorbool_attribute): Likewise.
	(s390_vector_mode_supported_p): Likewise.
	(s390_cc_modes_compatible): Likewise.
	(s390_match_ccmode_set): Likewise.
	(s390_canonicalize_comparison): Likewise.
	(s390_emit_compare_and_swap): Likewise.
	(s390_branch_condition_mask): Likewise.
	(s390_rtx_costs): Likewise.
	(s390_secondary_reload): Likewise.
	(__SECONDARY_RELOAD_CASE): Likewise.
	(s390_expand_cs): Likewise.
	(s390_preferred_simd_mode): Likewise.
	* config/s390/vx-builtins.md (vec_packsu_u<mode>): Likewise.
	* config/sh/sh.c (sh_print_operand): Likewise.
	(dump_table): Likewise.
	(sh_secondary_reload): Likewise.
	* config/sh/sh.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
	* config/sh/sh.md (casesi_worker_1): Likewise.
	(casesi_worker_2): Likewise.
	* config/sparc/predicates.md (icc_comparison_operator): Likewise.
	(fcc_comparison_operator): Likewise.
	* config/sparc/sparc.c (sparc_expand_move): Likewise.
	(emit_soft_tfmode_cvt): Likewise.
	(sparc_preferred_simd_mode): Likewise.
	(output_cbranch): Likewise.
	(sparc_print_operand): Likewise.
	(sparc_expand_vec_perm_bmask): Likewise.
	(vector_init_bshuffle): Likewise.
	* config/spu/spu.c (spu_scalar_mode_supported_p): Likewise.
	(spu_vector_mode_supported_p): Likewise.
	(spu_expand_insv): Likewise.
	(spu_emit_branch_or_set): Likewise.
	(spu_handle_vector_attribute): Likewise.
	(spu_builtin_splats): Likewise.
	(spu_builtin_extract): Likewise.
	(spu_builtin_promote): Likewise.
	(spu_expand_sign_extend): Likewise.
	* config/tilegx/tilegx.c (tilegx_scalar_mode_supported_p): Likewise.
	(tilegx_simd_int): Likewise.
	* config/tilepro/tilepro.c (tilepro_scalar_mode_supported_p): Likewise.
	(tilepro_simd_int): Likewise.
	* config/v850/v850.c (const_double_split): Likewise.
	(v850_print_operand): Likewise.
	(ep_memory_offset): Likewise.
	* config/vax/vax.c (vax_rtx_costs): Likewise.
	(vax_output_int_move): Likewise.
	(vax_output_int_add): Likewise.
	(vax_output_int_subtract): Likewise.
	* config/visium/predicates.md (visium_branch_operator): Likewise.
	* config/visium/visium.c (rtx_ok_for_offset_p): Likewise.
	(visium_print_operand_address): Likewise.
	* config/visium/visium.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
	* config/xtensa/xtensa.c (xtensa_mem_offset): Likewise.
	(xtensa_expand_conditional_branch): Likewise.
	(xtensa_copy_incoming_a7): Likewise.
	(xtensa_output_literal): Likewise.
	* dfp.c (decimal_real_maxval): Likewise.
	* targhooks.c (default_libgcc_floating_mode_supported_p): Likewise.

gcc/c-family/
	* c-cppbuiltin.c (mode_has_fma): Prefix mode names with E_ in
	case statements.

gcc/objc/
	* objc-encoding.c (encode_gnu_bitfield): Prefix mode names with E_ in
	case statements.

libobjc/
	* encoding.c (_darwin_rs6000_special_round_type_align): Prefix mode
	names with E_ in case statements.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251453
This commit is contained in:
Richard Sandiford 2017-08-30 11:08:28 +00:00 committed by Richard Sandiford
parent 0d4a1197ba
commit 4e10a5a74b
70 changed files with 2991 additions and 2624 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

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@ -1,3 +1,340 @@
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type):
Prefix mode names with E_ in case statements.
* config/aarch64/aarch64-elf.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/aarch64/aarch64.c (aarch64_split_simd_combine): Likewise.
(aarch64_split_simd_move): Likewise.
(aarch64_gen_storewb_pair): Likewise.
(aarch64_gen_loadwb_pair): Likewise.
(aarch64_gen_store_pair): Likewise.
(aarch64_gen_load_pair): Likewise.
(aarch64_get_condition_code_1): Likewise.
(aarch64_constant_pool_reload_icode): Likewise.
(get_rsqrte_type): Likewise.
(get_rsqrts_type): Likewise.
(get_recpe_type): Likewise.
(get_recps_type): Likewise.
(aarch64_gimplify_va_arg_expr): Likewise.
(aarch64_simd_container_mode): Likewise.
(aarch64_emit_load_exclusive): Likewise.
(aarch64_emit_store_exclusive): Likewise.
(aarch64_expand_compare_and_swap): Likewise.
(aarch64_gen_atomic_cas): Likewise.
(aarch64_emit_bic): Likewise.
(aarch64_emit_atomic_swap): Likewise.
(aarch64_emit_atomic_load_op): Likewise.
(aarch64_evpc_trn): Likewise.
(aarch64_evpc_uzp): Likewise.
(aarch64_evpc_zip): Likewise.
(aarch64_evpc_ext): Likewise.
(aarch64_evpc_rev): Likewise.
(aarch64_evpc_dup): Likewise.
(aarch64_gen_ccmp_first): Likewise.
(aarch64_gen_ccmp_next): Likewise.
* config/alpha/alpha.c (alpha_scalar_mode_supported_p): Likewise.
(alpha_emit_xfloating_libcall): Likewise.
(emit_insxl): Likewise.
(alpha_arg_type): Likewise.
* config/arc/arc.c (arc_vector_mode_supported_p): Likewise.
(arc_preferred_simd_mode): Likewise.
(arc_secondary_reload): Likewise.
(get_arc_condition_code): Likewise.
(arc_print_operand): Likewise.
(arc_legitimate_constant_p): Likewise.
* config/arc/arc.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/arc/arc.md (casesi_load): Likewise.
(casesi_compact_jump): Likewise.
* config/arc/predicates.md (proper_comparison_operator): Likewise.
(cc_use_register): Likewise.
* config/arm/aout.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/arm/arm-builtins.c (arm_simd_builtin_std_type): Likewise.
(arm_init_iwmmxt_builtins): Likewise.
* config/arm/arm.c (thumb1_size_rtx_costs): Likewise.
(neon_expand_vector_init): Likewise.
(arm_attr_length_move_neon): Likewise.
(maybe_get_arm_condition_code): Likewise.
(arm_emit_vector_const): Likewise.
(arm_preferred_simd_mode): Likewise.
(arm_output_iwmmxt_tinsr): Likewise.
(thumb1_output_casesi): Likewise.
(thumb2_output_casesi): Likewise.
(arm_emit_load_exclusive): Likewise.
(arm_emit_store_exclusive): Likewise.
(arm_expand_compare_and_swap): Likewise.
(arm_evpc_neon_vuzp): Likewise.
(arm_evpc_neon_vzip): Likewise.
(arm_evpc_neon_vrev): Likewise.
(arm_evpc_neon_vtrn): Likewise.
(arm_evpc_neon_vext): Likewise.
(arm_validize_comparison): Likewise.
* config/arm/neon.md (neon_vc<cmp_op><mode>): Likewise.
* config/avr/avr-c.c (avr_resolve_overloaded_builtin): Likewise.
* config/avr/avr.c (avr_rtx_costs_1): Likewise.
* config/c6x/c6x.c (c6x_vector_mode_supported_p): Likewise.
(c6x_preferred_simd_mode): Likewise.
* config/epiphany/epiphany.c (get_epiphany_condition_code): Likewise.
(epiphany_rtx_costs): Likewise.
* config/epiphany/predicates.md (proper_comparison_operator):
Likewise.
* config/frv/frv.c (condexec_memory_operand): Likewise.
(frv_emit_move): Likewise.
(output_move_single): Likewise.
(output_condmove_single): Likewise.
(frv_hard_regno_mode_ok): Likewise.
(frv_matching_accg_mode): Likewise.
* config/h8300/h8300.c (split_adds_subs): Likewise.
(h8300_rtx_costs): Likewise.
(h8300_print_operand): Likewise.
(compute_mov_length): Likewise.
(output_logical_op): Likewise.
(compute_logical_op_length): Likewise.
(compute_logical_op_cc): Likewise.
(h8300_shift_needs_scratch_p): Likewise.
(output_a_shift): Likewise.
(compute_a_shift_length): Likewise.
(compute_a_shift_cc): Likewise.
(expand_a_rotate): Likewise.
(output_a_rotate): Likewise.
* config/i386/i386.c (classify_argument): Likewise.
(function_arg_advance_32): Likewise.
(function_arg_32): Likewise.
(function_arg_64): Likewise.
(function_value_64): Likewise.
(ix86_gimplify_va_arg): Likewise.
(ix86_legitimate_constant_p): Likewise.
(put_condition_code): Likewise.
(split_double_mode): Likewise.
(ix86_avx256_split_vector_move_misalign): Likewise.
(ix86_expand_vector_logical_operator): Likewise.
(ix86_split_idivmod): Likewise.
(ix86_expand_adjust_ufix_to_sfix_si): Likewise.
(ix86_build_const_vector): Likewise.
(ix86_build_signbit_mask): Likewise.
(ix86_match_ccmode): Likewise.
(ix86_cc_modes_compatible): Likewise.
(ix86_expand_branch): Likewise.
(ix86_expand_sse_cmp): Likewise.
(ix86_expand_sse_movcc): Likewise.
(ix86_expand_int_sse_cmp): Likewise.
(ix86_expand_vec_perm_vpermi2): Likewise.
(ix86_expand_vec_perm): Likewise.
(ix86_expand_sse_unpack): Likewise.
(ix86_expand_int_addcc): Likewise.
(ix86_split_to_parts): Likewise.
(ix86_vectorize_builtin_gather): Likewise.
(ix86_vectorize_builtin_scatter): Likewise.
(avx_vpermilp_parallel): Likewise.
(inline_memory_move_cost): Likewise.
(ix86_tieable_integer_mode_p): Likewise.
(x86_maybe_negate_const_int): Likewise.
(ix86_expand_vector_init_duplicate): Likewise.
(ix86_expand_vector_init_one_nonzero): Likewise.
(ix86_expand_vector_init_one_var): Likewise.
(ix86_expand_vector_init_concat): Likewise.
(ix86_expand_vector_init_interleave): Likewise.
(ix86_expand_vector_init_general): Likewise.
(ix86_expand_vector_set): Likewise.
(ix86_expand_vector_extract): Likewise.
(emit_reduc_half): Likewise.
(ix86_emit_i387_round): Likewise.
(ix86_mangle_type): Likewise.
(ix86_expand_round_sse4): Likewise.
(expand_vec_perm_blend): Likewise.
(canonicalize_vector_int_perm): Likewise.
(ix86_expand_vec_one_operand_perm_avx512): Likewise.
(expand_vec_perm_1): Likewise.
(expand_vec_perm_interleave3): Likewise.
(expand_vec_perm_even_odd_pack): Likewise.
(expand_vec_perm_even_odd_1): Likewise.
(expand_vec_perm_broadcast_1): Likewise.
(ix86_vectorize_vec_perm_const_ok): Likewise.
(ix86_expand_vecop_qihi): Likewise.
(ix86_expand_mul_widen_hilo): Likewise.
(ix86_expand_sse2_abs): Likewise.
(ix86_expand_pextr): Likewise.
(ix86_expand_pinsr): Likewise.
(ix86_preferred_simd_mode): Likewise.
(ix86_simd_clone_compute_vecsize_and_simdlen): Likewise.
* config/i386/sse.md (*andnot<mode>3): Likewise.
(<mask_codefor><code><mode>3<mask_name>): Likewise.
(*<code><mode>3): Likewise.
* config/ia64/ia64.c (ia64_expand_vecint_compare): Likewise.
(ia64_expand_atomic_op): Likewise.
(ia64_arg_type): Likewise.
(ia64_mode_to_int): Likewise.
(ia64_scalar_mode_supported_p): Likewise.
(ia64_vector_mode_supported_p): Likewise.
(expand_vec_perm_broadcast): Likewise.
* config/iq2000/iq2000.c (iq2000_move_1word): Likewise.
(iq2000_function_arg_advance): Likewise.
(iq2000_function_arg): Likewise.
* config/m32c/m32c.c (m32c_preferred_reload_class): Likewise.
* config/m68k/m68k.c (output_dbcc_and_branch): Likewise.
(m68k_libcall_value): Likewise.
(m68k_function_value): Likewise.
(sched_attr_op_type): Likewise.
* config/mcore/mcore.c (mcore_output_move): Likewise.
* config/microblaze/microblaze.c (microblaze_function_arg_advance):
Likewise.
(microblaze_function_arg): Likewise.
* config/mips/mips.c (mips16_build_call_stub): Likewise.
(mips_print_operand): Likewise.
(mips_mode_ok_for_mov_fmt_p): Likewise.
(mips_vector_mode_supported_p): Likewise.
(mips_preferred_simd_mode): Likewise.
(mips_expand_vpc_loongson_even_odd): Likewise.
(mips_expand_vec_unpack): Likewise.
(mips_expand_vi_broadcast): Likewise.
(mips_expand_vector_init): Likewise.
(mips_expand_vec_reduc): Likewise.
(mips_expand_msa_cmp): Likewise.
* config/mips/mips.md (casesi_internal_mips16_<mode>): Likewise.
* config/mn10300/mn10300.c (mn10300_print_operand): Likewise.
(cc_flags_for_mode): Likewise.
* config/msp430/msp430.c (msp430_print_operand): Likewise.
* config/nds32/nds32-md-auxiliary.c (nds32_mem_format): Likewise.
(nds32_output_casesi_pc_relative): Likewise.
* config/nds32/nds32.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/nvptx/nvptx.c (nvptx_ptx_type_from_mode): Likewise.
(nvptx_gen_unpack): Likewise.
(nvptx_gen_pack): Likewise.
(nvptx_gen_shuffle): Likewise.
(nvptx_gen_wcast): Likewise.
(nvptx_preferred_simd_mode): Likewise.
* config/pa/pa.c (pa_secondary_reload): Likewise.
* config/pa/predicates.md (base14_operand): Likewise.
* config/powerpcspe/powerpcspe-c.c
(altivec_resolve_overloaded_builtin): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_setup_reg_addr_masks):
Likewise.
(rs6000_preferred_simd_mode): Likewise.
(output_vec_const_move): Likewise.
(rs6000_expand_vector_extract): Likewise.
(rs6000_split_vec_extract_var): Likewise.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_emit_set_const): Likewise.
(rs6000_const_vec): Likewise.
(rs6000_emit_move): Likewise.
(spe_build_register_parallel): Likewise.
(rs6000_darwin64_record_arg_recurse): Likewise.
(swap_selector_for_mode): Likewise.
(spe_init_builtins): Likewise.
(paired_init_builtins): Likewise.
(altivec_init_builtins): Likewise.
(do_load_for_compare): Likewise.
(rs6000_generate_compare): Likewise.
(rs6000_expand_float128_convert): Likewise.
(emit_load_locked): Likewise.
(emit_store_conditional): Likewise.
(rs6000_output_function_epilogue): Likewise.
(rs6000_handle_altivec_attribute): Likewise.
(rs6000_function_value): Likewise.
(emit_fusion_gpr_load): Likewise.
(emit_fusion_p9_load): Likewise.
(emit_fusion_p9_store): Likewise.
* config/powerpcspe/predicates.md (easy_fp_constant): Likewise.
(fusion_gpr_mem_load): Likewise.
(fusion_addis_mem_combo_load): Likewise.
(fusion_addis_mem_combo_store): Likewise.
* config/rs6000/predicates.md (easy_fp_constant): Likewise.
(fusion_gpr_mem_load): Likewise.
(fusion_addis_mem_combo_load): Likewise.
(fusion_addis_mem_combo_store): Likewise.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Likewise.
* config/rs6000/rs6000-string.c (do_load_for_compare): Likewise.
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise.
(rs6000_preferred_simd_mode): Likewise.
(output_vec_const_move): Likewise.
(rs6000_expand_vector_extract): Likewise.
(rs6000_split_vec_extract_var): Likewise.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_emit_set_const): Likewise.
(rs6000_const_vec): Likewise.
(rs6000_emit_move): Likewise.
(rs6000_darwin64_record_arg_recurse): Likewise.
(swap_selector_for_mode): Likewise.
(paired_init_builtins): Likewise.
(altivec_init_builtins): Likewise.
(rs6000_expand_float128_convert): Likewise.
(emit_load_locked): Likewise.
(emit_store_conditional): Likewise.
(rs6000_output_function_epilogue): Likewise.
(rs6000_handle_altivec_attribute): Likewise.
(rs6000_function_value): Likewise.
(emit_fusion_gpr_load): Likewise.
(emit_fusion_p9_load): Likewise.
(emit_fusion_p9_store): Likewise.
* config/rx/rx.c (rx_gen_move_template): Likewise.
(flags_from_mode): Likewise.
* config/s390/predicates.md (s390_alc_comparison): Likewise.
(s390_slb_comparison): Likewise.
* config/s390/s390.c (s390_handle_vectorbool_attribute): Likewise.
(s390_vector_mode_supported_p): Likewise.
(s390_cc_modes_compatible): Likewise.
(s390_match_ccmode_set): Likewise.
(s390_canonicalize_comparison): Likewise.
(s390_emit_compare_and_swap): Likewise.
(s390_branch_condition_mask): Likewise.
(s390_rtx_costs): Likewise.
(s390_secondary_reload): Likewise.
(__SECONDARY_RELOAD_CASE): Likewise.
(s390_expand_cs): Likewise.
(s390_preferred_simd_mode): Likewise.
* config/s390/vx-builtins.md (vec_packsu_u<mode>): Likewise.
* config/sh/sh.c (sh_print_operand): Likewise.
(dump_table): Likewise.
(sh_secondary_reload): Likewise.
* config/sh/sh.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/sh/sh.md (casesi_worker_1): Likewise.
(casesi_worker_2): Likewise.
* config/sparc/predicates.md (icc_comparison_operator): Likewise.
(fcc_comparison_operator): Likewise.
* config/sparc/sparc.c (sparc_expand_move): Likewise.
(emit_soft_tfmode_cvt): Likewise.
(sparc_preferred_simd_mode): Likewise.
(output_cbranch): Likewise.
(sparc_print_operand): Likewise.
(sparc_expand_vec_perm_bmask): Likewise.
(vector_init_bshuffle): Likewise.
* config/spu/spu.c (spu_scalar_mode_supported_p): Likewise.
(spu_vector_mode_supported_p): Likewise.
(spu_expand_insv): Likewise.
(spu_emit_branch_or_set): Likewise.
(spu_handle_vector_attribute): Likewise.
(spu_builtin_splats): Likewise.
(spu_builtin_extract): Likewise.
(spu_builtin_promote): Likewise.
(spu_expand_sign_extend): Likewise.
* config/tilegx/tilegx.c (tilegx_scalar_mode_supported_p): Likewise.
(tilegx_simd_int): Likewise.
* config/tilepro/tilepro.c (tilepro_scalar_mode_supported_p): Likewise.
(tilepro_simd_int): Likewise.
* config/v850/v850.c (const_double_split): Likewise.
(v850_print_operand): Likewise.
(ep_memory_offset): Likewise.
* config/vax/vax.c (vax_rtx_costs): Likewise.
(vax_output_int_move): Likewise.
(vax_output_int_add): Likewise.
(vax_output_int_subtract): Likewise.
* config/visium/predicates.md (visium_branch_operator): Likewise.
* config/visium/visium.c (rtx_ok_for_offset_p): Likewise.
(visium_print_operand_address): Likewise.
* config/visium/visium.h (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/xtensa/xtensa.c (xtensa_mem_offset): Likewise.
(xtensa_expand_conditional_branch): Likewise.
(xtensa_copy_incoming_a7): Likewise.
(xtensa_output_literal): Likewise.
* dfp.c (decimal_real_maxval): Likewise.
* targhooks.c (default_libgcc_floating_mode_supported_p): Likewise.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>

7
gcc/c-family/ChangeLog
View File

@ -1,3 +1,10 @@
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* c-cppbuiltin.c (mode_has_fma): Prefix mode names with E_ in
case statements.
2017-08-29 Martin Liska <mliska@suse.cz>
PR other/39851

8
gcc/c-family/c-cppbuiltin.c
View File

@ -73,22 +73,22 @@ mode_has_fma (machine_mode mode)
switch (mode)
{
#ifdef HAVE_fmasf4
case SFmode:
case E_SFmode:
return !!HAVE_fmasf4;
#endif
#ifdef HAVE_fmadf4
case DFmode:
case E_DFmode:
return !!HAVE_fmadf4;
#endif
#ifdef HAVE_fmaxf4
case XFmode:
case E_XFmode:
return !!HAVE_fmaxf4;
#endif
#ifdef HAVE_fmatf4
case TFmode:
case E_TFmode:
return !!HAVE_fmatf4;
#endif

22
gcc/config/aarch64/aarch64-builtins.c
View File

@ -537,27 +537,27 @@ aarch64_simd_builtin_std_type (machine_mode mode,
((q == qualifier_none) ? int##M##_type_node : unsigned_int##M##_type_node);
switch (mode)
{
case QImode:
case E_QImode:
return QUAL_TYPE (QI);
case HImode:
case E_HImode:
return QUAL_TYPE (HI);
case SImode:
case E_SImode:
return QUAL_TYPE (SI);
case DImode:
case E_DImode:
return QUAL_TYPE (DI);
case TImode:
case E_TImode:
return QUAL_TYPE (TI);
case OImode:
case E_OImode:
return aarch64_simd_intOI_type_node;
case CImode:
case E_CImode:
return aarch64_simd_intCI_type_node;
case XImode:
case E_XImode:
return aarch64_simd_intXI_type_node;
case HFmode:
case E_HFmode:
return aarch64_fp16_type_node;
case SFmode:
case E_SFmode:
return float_type_node;
case DFmode:
case E_DFmode:
return double_type_node;
default:
gcc_unreachable ();

8
gcc/config/aarch64/aarch64-elf.h
View File

@ -74,16 +74,16 @@
do { \
switch (GET_MODE (BODY)) \
{ \
case QImode: \
case E_QImode: \
asm_fprintf (STREAM, "\t.byte\t(%LL%d - %LLrtx%d) / 4\n", \
VALUE, REL); \
break; \
case HImode: \
case E_HImode: \
asm_fprintf (STREAM, "\t.2byte\t(%LL%d - %LLrtx%d) / 4\n", \
VALUE, REL); \
break; \
case SImode: \
case DImode: /* See comment in aarch64_output_casesi. */ \
case E_SImode: \
case E_DImode: /* See comment in aarch64_output_casesi. */ \
asm_fprintf (STREAM, "\t.word\t(%LL%d - %LLrtx%d) / 4\n", \
VALUE, REL); \
break; \

468
gcc/config/aarch64/aarch64.c
View File

@ -1698,25 +1698,25 @@ aarch64_split_simd_combine (rtx dst, rtx src1, rtx src2)
switch (src_mode)
{
case V8QImode:
case E_V8QImode:
gen = gen_aarch64_simd_combinev8qi;
break;
case V4HImode:
case E_V4HImode:
gen = gen_aarch64_simd_combinev4hi;
break;
case V2SImode:
case E_V2SImode:
gen = gen_aarch64_simd_combinev2si;
break;
case V4HFmode:
case E_V4HFmode:
gen = gen_aarch64_simd_combinev4hf;
break;
case V2SFmode:
case E_V2SFmode:
gen = gen_aarch64_simd_combinev2sf;
break;
case DImode:
case E_DImode:
gen = gen_aarch64_simd_combinedi;
break;
case DFmode:
case E_DFmode:
gen = gen_aarch64_simd_combinedf;
break;
default:
@ -1745,25 +1745,25 @@ aarch64_split_simd_move (rtx dst, rtx src)
switch (src_mode)
{
case V16QImode:
case E_V16QImode:
gen = gen_aarch64_split_simd_movv16qi;
break;
case V8HImode:
case E_V8HImode:
gen = gen_aarch64_split_simd_movv8hi;
break;
case V4SImode:
case E_V4SImode:
gen = gen_aarch64_split_simd_movv4si;
break;
case V2DImode:
case E_V2DImode:
gen = gen_aarch64_split_simd_movv2di;
break;
case V8HFmode:
case E_V8HFmode:
gen = gen_aarch64_split_simd_movv8hf;
break;
case V4SFmode:
case E_V4SFmode:
gen = gen_aarch64_split_simd_movv4sf;
break;
case V2DFmode:
case E_V2DFmode:
gen = gen_aarch64_split_simd_movv2df;
break;
default:
@ -3086,11 +3086,11 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
{
switch (mode)
{
case DImode:
case E_DImode:
return gen_storewb_pairdi_di (base, base, reg, reg2,
GEN_INT (-adjustment),
GEN_INT (UNITS_PER_WORD - adjustment));
case DFmode:
case E_DFmode:
return gen_storewb_pairdf_di (base, base, reg, reg2,
GEN_INT (-adjustment),
GEN_INT (UNITS_PER_WORD - adjustment));
@ -3130,10 +3130,10 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
{
switch (mode)
{
case DImode:
case E_DImode:
return gen_loadwb_pairdi_di (base, base, reg, reg2, GEN_INT (adjustment),
GEN_INT (UNITS_PER_WORD));
case DFmode:
case E_DFmode:
return gen_loadwb_pairdf_di (base, base, reg, reg2, GEN_INT (adjustment),
GEN_INT (UNITS_PER_WORD));
default:
@ -3178,10 +3178,10 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
{
switch (mode)
{
case DImode:
case E_DImode:
return gen_store_pairdi (mem1, reg1, mem2, reg2);
case DFmode:
case E_DFmode:
return gen_store_pairdf (mem1, reg1, mem2, reg2);
default:
@ -3198,10 +3198,10 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
{
switch (mode)
{
case DImode:
case E_DImode:
return gen_load_pairdi (reg1, mem1, reg2, mem2);
case DFmode:
case E_DFmode:
return gen_load_pairdf (reg1, mem1, reg2, mem2);
default:
@ -4994,8 +4994,8 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
{
switch (mode)
{
case CCFPmode:
case CCFPEmode:
case E_CCFPmode:
case E_CCFPEmode:
switch (comp_code)
{
case GE: return AARCH64_GE;
@ -5014,7 +5014,7 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
}
break;
case CCmode:
case E_CCmode:
switch (comp_code)
{
case NE: return AARCH64_NE;
@ -5031,7 +5031,7 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
}
break;
case CC_SWPmode:
case E_CC_SWPmode:
switch (comp_code)
{
case NE: return AARCH64_NE;
@ -5048,7 +5048,7 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
}
break;
case CC_NZmode:
case E_CC_NZmode:
switch (comp_code)
{
case NE: return AARCH64_NE;
@ -5059,7 +5059,7 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
}
break;
case CC_Zmode:
case E_CC_Zmode:
switch (comp_code)
{
case NE: return AARCH64_NE;
@ -5068,7 +5068,7 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
}
break;
case CC_Cmode:
case E_CC_Cmode:
switch (comp_code)
{
case NE: return AARCH64_CS;
@ -5776,37 +5776,37 @@ aarch64_constant_pool_reload_icode (machine_mode mode)
{
switch (mode)
{
case SFmode:
case E_SFmode:
return CODE_FOR_aarch64_reload_movcpsfdi;
case DFmode:
case E_DFmode:
return CODE_FOR_aarch64_reload_movcpdfdi;
case TFmode:
case E_TFmode:
return CODE_FOR_aarch64_reload_movcptfdi;
case V8QImode:
case E_V8QImode:
return CODE_FOR_aarch64_reload_movcpv8qidi;
case V16QImode:
case E_V16QImode:
return CODE_FOR_aarch64_reload_movcpv16qidi;
case V4HImode:
case E_V4HImode:
return CODE_FOR_aarch64_reload_movcpv4hidi;
case V8HImode:
case E_V8HImode:
return CODE_FOR_aarch64_reload_movcpv8hidi;
case V2SImode:
case E_V2SImode:
return CODE_FOR_aarch64_reload_movcpv2sidi;
case V4SImode:
case E_V4SImode:
return CODE_FOR_aarch64_reload_movcpv4sidi;
case V2DImode:
case E_V2DImode:
return CODE_FOR_aarch64_reload_movcpv2didi;
case V2DFmode:
case E_V2DFmode:
return CODE_FOR_aarch64_reload_movcpv2dfdi;
default:
@ -8222,11 +8222,11 @@ get_rsqrte_type (machine_mode mode)
{
switch (mode)
{
case DFmode: return gen_aarch64_rsqrtedf;
case SFmode: return gen_aarch64_rsqrtesf;
case V2DFmode: return gen_aarch64_rsqrtev2df;
case V2SFmode: return gen_aarch64_rsqrtev2sf;
case V4SFmode: return gen_aarch64_rsqrtev4sf;
case E_DFmode: return gen_aarch64_rsqrtedf;
case E_SFmode: return gen_aarch64_rsqrtesf;
case E_V2DFmode: return gen_aarch64_rsqrtev2df;
case E_V2SFmode: return gen_aarch64_rsqrtev2sf;
case E_V4SFmode: return gen_aarch64_rsqrtev4sf;
default: gcc_unreachable ();
}
}
@ -8240,11 +8240,11 @@ get_rsqrts_type (machine_mode mode)
{
switch (mode)
{
case DFmode: return gen_aarch64_rsqrtsdf;
case SFmode: return gen_aarch64_rsqrtssf;
case V2DFmode: return gen_aarch64_rsqrtsv2df;
case V2SFmode: return gen_aarch64_rsqrtsv2sf;
case V4SFmode: return gen_aarch64_rsqrtsv4sf;
case E_DFmode: return gen_aarch64_rsqrtsdf;
case E_SFmode: return gen_aarch64_rsqrtssf;
case E_V2DFmode: return gen_aarch64_rsqrtsv2df;
case E_V2SFmode: return gen_aarch64_rsqrtsv2sf;
case E_V4SFmode: return gen_aarch64_rsqrtsv4sf;
default: gcc_unreachable ();
}
}
@ -8349,12 +8349,12 @@ get_recpe_type (machine_mode mode)
{
switch (mode)
{
case SFmode: return (gen_aarch64_frecpesf);
case V2SFmode: return (gen_aarch64_frecpev2sf);
case V4SFmode: return (gen_aarch64_frecpev4sf);
case DFmode: return (gen_aarch64_frecpedf);
case V2DFmode: return (gen_aarch64_frecpev2df);
default: gcc_unreachable ();
case E_SFmode: return (gen_aarch64_frecpesf);
case E_V2SFmode: return (gen_aarch64_frecpev2sf);
case E_V4SFmode: return (gen_aarch64_frecpev4sf);
case E_DFmode: return (gen_aarch64_frecpedf);
case E_V2DFmode: return (gen_aarch64_frecpev2df);
default: gcc_unreachable ();
}
}
@ -8367,12 +8367,12 @@ get_recps_type (machine_mode mode)
{
switch (mode)
{
case SFmode: return (gen_aarch64_frecpssf);
case V2SFmode: return (gen_aarch64_frecpsv2sf);
case V4SFmode: return (gen_aarch64_frecpsv4sf);
case DFmode: return (gen_aarch64_frecpsdf);
case V2DFmode: return (gen_aarch64_frecpsv2df);
default: gcc_unreachable ();
case E_SFmode: return (gen_aarch64_frecpssf);
case E_V2SFmode: return (gen_aarch64_frecpsv2sf);
case E_V4SFmode: return (gen_aarch64_frecpsv4sf);
case E_DFmode: return (gen_aarch64_frecpsdf);
case E_V2DFmode: return (gen_aarch64_frecpsv2df);
default: gcc_unreachable ();
}
}
@ -10743,24 +10743,24 @@ aarch64_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
/* Establish the base type. */
switch (ag_mode)
{
case SFmode:
case E_SFmode:
field_t = float_type_node;
field_ptr_t = float_ptr_type_node;
break;
case DFmode:
case E_DFmode:
field_t = double_type_node;
field_ptr_t = double_ptr_type_node;
break;
case TFmode:
case E_TFmode:
field_t = long_double_type_node;
field_ptr_t = long_double_ptr_type_node;
break;
case HFmode:
case E_HFmode:
field_t = aarch64_fp16_type_node;
field_ptr_t = aarch64_fp16_ptr_type_node;
break;
case V2SImode:
case V4SImode:
case E_V2SImode:
case E_V4SImode:
{
tree innertype = make_signed_type (GET_MODE_PRECISION (SImode));
field_t = build_vector_type_for_mode (innertype, ag_mode);
@ -11217,19 +11217,19 @@ aarch64_simd_container_mode (machine_mode mode, unsigned width)
if (width == 128)
switch (mode)
{
case DFmode:
case E_DFmode:
return V2DFmode;
case SFmode:
case E_SFmode:
return V4SFmode;
case HFmode:
case E_HFmode:
return V8HFmode;
case SImode:
case E_SImode:
return V4SImode;
case HImode:
case E_HImode:
return V8HImode;
case QImode:
case E_QImode:
return V16QImode;
case DImode:
case E_DImode:
return V2DImode;
default:
break;
@ -11237,15 +11237,15 @@ aarch64_simd_container_mode (machine_mode mode, unsigned width)
else
switch (mode)
{
case SFmode:
case E_SFmode:
return V2SFmode;
case HFmode:
case E_HFmode:
return V4HFmode;
case SImode:
case E_SImode:
return V2SImode;
case HImode:
case E_HImode:
return V4HImode;
case QImode:
case E_QImode:
return V8QImode;
default:
break;
@ -12211,10 +12211,10 @@ aarch64_emit_load_exclusive (machine_mode mode, rtx rval,
switch (mode)
{
case QImode: gen = gen_aarch64_load_exclusiveqi; break;
case HImode: gen = gen_aarch64_load_exclusivehi; break;
case SImode: gen = gen_aarch64_load_exclusivesi; break;
case DImode: gen = gen_aarch64_load_exclusivedi; break;
case E_QImode: gen = gen_aarch64_load_exclusiveqi; break;
case E_HImode: gen = gen_aarch64_load_exclusivehi; break;
case E_SImode: gen = gen_aarch64_load_exclusivesi; break;
case E_DImode: gen = gen_aarch64_load_exclusivedi; break;
default:
gcc_unreachable ();
}
@ -12232,10 +12232,10 @@ aarch64_emit_store_exclusive (machine_mode mode, rtx bval,
switch (mode)
{
case QImode: gen = gen_aarch64_store_exclusiveqi; break;
case HImode: gen = gen_aarch64_store_exclusivehi; break;
case SImode: gen = gen_aarch64_store_exclusivesi; break;
case DImode: gen = gen_aarch64_store_exclusivedi; break;
case E_QImode: gen = gen_aarch64_store_exclusiveqi; break;
case E_HImode: gen = gen_aarch64_store_exclusivehi; break;
case E_SImode: gen = gen_aarch64_store_exclusivesi; break;
case E_DImode: gen = gen_aarch64_store_exclusivedi; break;
default:
gcc_unreachable ();
}
@ -12298,8 +12298,8 @@ aarch64_expand_compare_and_swap (rtx operands[])
switch (mode)
{
case QImode:
case HImode:
case E_QImode:
case E_HImode:
/* For short modes, we're going to perform the comparison in SImode,
so do the zero-extension now. */
cmp_mode = SImode;
@ -12307,8 +12307,8 @@ aarch64_expand_compare_and_swap (rtx operands[])
oldval = convert_modes (SImode, mode, oldval, true);
/* Fall through. */
case SImode:
case DImode:
case E_SImode:
case E_DImode:
/* Force the value into a register if needed. */
if (!aarch64_plus_operand (oldval, mode))
oldval = force_reg (cmp_mode, oldval);
@ -12320,10 +12320,10 @@ aarch64_expand_compare_and_swap (rtx operands[])
switch (mode)
{
case QImode: idx = 0; break;
case HImode: idx = 1; break;
case SImode: idx = 2; break;
case DImode: idx = 3; break;
case E_QImode: idx = 0; break;
case E_HImode: idx = 1; break;
case E_SImode: idx = 2; break;
case E_DImode: idx = 3; break;
default:
gcc_unreachable ();
}
@ -12402,10 +12402,10 @@ aarch64_gen_atomic_cas (rtx rval, rtx mem,
switch (mode)
{
case QImode: gen = gen_aarch64_atomic_casqi; break;
case HImode: gen = gen_aarch64_atomic_cashi; break;
case SImode: gen = gen_aarch64_atomic_cassi; break;
case DImode: gen = gen_aarch64_atomic_casdi; break;
case E_QImode: gen = gen_aarch64_atomic_casqi; break;
case E_HImode: gen = gen_aarch64_atomic_cashi; break;
case E_SImode: gen = gen_aarch64_atomic_cassi; break;
case E_DImode: gen = gen_aarch64_atomic_casdi; break;
default:
gcc_unreachable ();
}
@ -12528,8 +12528,8 @@ aarch64_emit_bic (machine_mode mode, rtx dst, rtx s1, rtx s2, int shift)
switch (mode)
{
case SImode: gen = gen_and_one_cmpl_lshrsi3; break;
case DImode: gen = gen_and_one_cmpl_lshrdi3; break;
case E_SImode: gen = gen_and_one_cmpl_lshrsi3; break;
case E_DImode: gen = gen_and_one_cmpl_lshrdi3; break;
default:
gcc_unreachable ();
}
@ -12547,10 +12547,10 @@ aarch64_emit_atomic_swap (machine_mode mode, rtx dst, rtx value,
switch (mode)
{
case QImode: gen = gen_aarch64_atomic_swpqi; break;
case HImode: gen = gen_aarch64_atomic_swphi; break;
case SImode: gen = gen_aarch64_atomic_swpsi; break;
case DImode: gen = gen_aarch64_atomic_swpdi; break;
case E_QImode: gen = gen_aarch64_atomic_swpqi; break;
case E_HImode: gen = gen_aarch64_atomic_swphi; break;
case E_SImode: gen = gen_aarch64_atomic_swpsi; break;
case E_DImode: gen = gen_aarch64_atomic_swpdi; break;
default:
gcc_unreachable ();
}
@ -12609,10 +12609,10 @@ aarch64_emit_atomic_load_op (enum aarch64_atomic_load_op_code code,
switch (mode)
{
case QImode: idx = 0; break;
case HImode: idx = 1; break;
case SImode: idx = 2; break;
case DImode: idx = 3; break;
case E_QImode: idx = 0; break;
case E_HImode: idx = 1; break;
case E_SImode: idx = 2; break;
case E_DImode: idx = 3; break;
default:
gcc_unreachable ();
}
@ -13243,18 +13243,18 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
{
switch (vmode)
{
case V16QImode: gen = gen_aarch64_trn2v16qi; break;
case V8QImode: gen = gen_aarch64_trn2v8qi; break;
case V8HImode: gen = gen_aarch64_trn2v8hi; break;
case V4HImode: gen = gen_aarch64_trn2v4hi; break;
case V4SImode: gen = gen_aarch64_trn2v4si; break;
case V2SImode: gen = gen_aarch64_trn2v2si; break;
case V2DImode: gen = gen_aarch64_trn2v2di; break;
case V4HFmode: gen = gen_aarch64_trn2v4hf; break;
case V8HFmode: gen = gen_aarch64_trn2v8hf; break;
case V4SFmode: gen = gen_aarch64_trn2v4sf; break;
case V2SFmode: gen = gen_aarch64_trn2v2sf; break;
case V2DFmode: gen = gen_aarch64_trn2v2df; break;
case E_V16QImode: gen = gen_aarch64_trn2v16qi; break;
case E_V8QImode: gen = gen_aarch64_trn2v8qi; break;
case E_V8HImode: gen = gen_aarch64_trn2v8hi; break;
case E_V4HImode: gen = gen_aarch64_trn2v4hi; break;
case E_V4SImode: gen = gen_aarch64_trn2v4si; break;
case E_V2SImode: gen = gen_aarch64_trn2v2si; break;
case E_V2DImode: gen = gen_aarch64_trn2v2di; break;
case E_V4HFmode: gen = gen_aarch64_trn2v4hf; break;
case E_V8HFmode: gen = gen_aarch64_trn2v8hf; break;
case E_V4SFmode: gen = gen_aarch64_trn2v4sf; break;
case E_V2SFmode: gen = gen_aarch64_trn2v2sf; break;
case E_V2DFmode: gen = gen_aarch64_trn2v2df; break;
default:
return false;
}
@ -13263,18 +13263,18 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
{
switch (vmode)
{
case V16QImode: gen = gen_aarch64_trn1v16qi; break;
case V8QImode: gen = gen_aarch64_trn1v8qi; break;
case V8HImode: gen = gen_aarch64_trn1v8hi; break;
case V4HImode: gen = gen_aarch64_trn1v4hi; break;
case V4SImode: gen = gen_aarch64_trn1v4si; break;
case V2SImode: gen = gen_aarch64_trn1v2si; break;
case V2DImode: gen = gen_aarch64_trn1v2di; break;
case V4HFmode: gen = gen_aarch64_trn1v4hf; break;
case V8HFmode: gen = gen_aarch64_trn1v8hf; break;
case V4SFmode: gen = gen_aarch64_trn1v4sf; break;
case V2SFmode: gen = gen_aarch64_trn1v2sf; break;
case V2DFmode: gen = gen_aarch64_trn1v2df; break;
case E_V16QImode: gen = gen_aarch64_trn1v16qi; break;
case E_V8QImode: gen = gen_aarch64_trn1v8qi; break;
case E_V8HImode: gen = gen_aarch64_trn1v8hi; break;
case E_V4HImode: gen = gen_aarch64_trn1v4hi; break;
case E_V4SImode: gen = gen_aarch64_trn1v4si; break;
case E_V2SImode: gen = gen_aarch64_trn1v2si; break;
case E_V2DImode: gen = gen_aarch64_trn1v2di; break;
case E_V4HFmode: gen = gen_aarch64_trn1v4hf; break;
case E_V8HFmode: gen = gen_aarch64_trn1v8hf; break;
case E_V4SFmode: gen = gen_aarch64_trn1v4sf; break;
case E_V2SFmode: gen = gen_aarch64_trn1v2sf; break;
case E_V2DFmode: gen = gen_aarch64_trn1v2df; break;
default:
return false;
}
@ -13330,18 +13330,18 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
{
switch (vmode)
{
case V16QImode: gen = gen_aarch64_uzp2v16qi; break;
case V8QImode: gen = gen_aarch64_uzp2v8qi; break;
case V8HImode: gen = gen_aarch64_uzp2v8hi; break;
case V4HImode: gen = gen_aarch64_uzp2v4hi; break;
case V4SImode: gen = gen_aarch64_uzp2v4si; break;
case V2SImode: gen = gen_aarch64_uzp2v2si; break;
case V2DImode: gen = gen_aarch64_uzp2v2di; break;
case V4HFmode: gen = gen_aarch64_uzp2v4hf; break;
case V8HFmode: gen = gen_aarch64_uzp2v8hf; break;
case V4SFmode: gen = gen_aarch64_uzp2v4sf; break;
case V2SFmode: gen = gen_aarch64_uzp2v2sf; break;
case V2DFmode: gen = gen_aarch64_uzp2v2df; break;
case E_V16QImode: gen = gen_aarch64_uzp2v16qi; break;
case E_V8QImode: gen = gen_aarch64_uzp2v8qi; break;
case E_V8HImode: gen = gen_aarch64_uzp2v8hi; break;
case E_V4HImode: gen = gen_aarch64_uzp2v4hi; break;
case E_V4SImode: gen = gen_aarch64_uzp2v4si; break;
case E_V2SImode: gen = gen_aarch64_uzp2v2si; break;
case E_V2DImode: gen = gen_aarch64_uzp2v2di; break;
case E_V4HFmode: gen = gen_aarch64_uzp2v4hf; break;
case E_V8HFmode: gen = gen_aarch64_uzp2v8hf; break;
case E_V4SFmode: gen = gen_aarch64_uzp2v4sf; break;
case E_V2SFmode: gen = gen_aarch64_uzp2v2sf; break;
case E_V2DFmode: gen = gen_aarch64_uzp2v2df; break;
default:
return false;
}
@ -13350,18 +13350,18 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
{
switch (vmode)
{
case V16QImode: gen = gen_aarch64_uzp1v16qi; break;
case V8QImode: gen = gen_aarch64_uzp1v8qi; break;
case V8HImode: gen = gen_aarch64_uzp1v8hi; break;
case V4HImode: gen = gen_aarch64_uzp1v4hi; break;
case V4SImode: gen = gen_aarch64_uzp1v4si; break;
case V2SImode: gen = gen_aarch64_uzp1v2si; break;
case V2DImode: gen = gen_aarch64_uzp1v2di; break;
case V4HFmode: gen = gen_aarch64_uzp1v4hf; break;
case V8HFmode: gen = gen_aarch64_uzp1v8hf; break;
case V4SFmode: gen = gen_aarch64_uzp1v4sf; break;
case V2SFmode: gen = gen_aarch64_uzp1v2sf; break;
case V2DFmode: gen = gen_aarch64_uzp1v2df; break;
case E_V16QImode: gen = gen_aarch64_uzp1v16qi; break;
case E_V8QImode: gen = gen_aarch64_uzp1v8qi; break;
case E_V8HImode: gen = gen_aarch64_uzp1v8hi; break;
case E_V4HImode: gen = gen_aarch64_uzp1v4hi; break;
case E_V4SImode: gen = gen_aarch64_uzp1v4si; break;
case E_V2SImode: gen = gen_aarch64_uzp1v2si; break;
case E_V2DImode: gen = gen_aarch64_uzp1v2di; break;
case E_V4HFmode: gen = gen_aarch64_uzp1v4hf; break;
case E_V8HFmode: gen = gen_aarch64_uzp1v8hf; break;
case E_V4SFmode: gen = gen_aarch64_uzp1v4sf; break;
case E_V2SFmode: gen = gen_aarch64_uzp1v2sf; break;
case E_V2DFmode: gen = gen_aarch64_uzp1v2df; break;
default:
return false;
}
@ -13422,18 +13422,18 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
{
switch (vmode)
{
case V16QImode: gen = gen_aarch64_zip2v16qi; break;
case V8QImode: gen = gen_aarch64_zip2v8qi; break;
case V8HImode: gen = gen_aarch64_zip2v8hi; break;
case V4HImode: gen = gen_aarch64_zip2v4hi; break;
case V4SImode: gen = gen_aarch64_zip2v4si; break;
case V2SImode: gen = gen_aarch64_zip2v2si; break;
case V2DImode: gen = gen_aarch64_zip2v2di; break;
case V4HFmode: gen = gen_aarch64_zip2v4hf; break;
case V8HFmode: gen = gen_aarch64_zip2v8hf; break;
case V4SFmode: gen = gen_aarch64_zip2v4sf; break;
case V2SFmode: gen = gen_aarch64_zip2v2sf; break;
case V2DFmode: gen = gen_aarch64_zip2v2df; break;
case E_V16QImode: gen = gen_aarch64_zip2v16qi; break;
case E_V8QImode: gen = gen_aarch64_zip2v8qi; break;
case E_V8HImode: gen = gen_aarch64_zip2v8hi; break;
case E_V4HImode: gen = gen_aarch64_zip2v4hi; break;
case E_V4SImode: gen = gen_aarch64_zip2v4si; break;
case E_V2SImode: gen = gen_aarch64_zip2v2si; break;
case E_V2DImode: gen = gen_aarch64_zip2v2di; break;
case E_V4HFmode: gen = gen_aarch64_zip2v4hf; break;
case E_V8HFmode: gen = gen_aarch64_zip2v8hf; break;
case E_V4SFmode: gen = gen_aarch64_zip2v4sf; break;
case E_V2SFmode: gen = gen_aarch64_zip2v2sf; break;
case E_V2DFmode: gen = gen_aarch64_zip2v2df; break;
default:
return false;
}
@ -13442,18 +13442,18 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
{
switch (vmode)
{
case V16QImode: gen = gen_aarch64_zip1v16qi; break;
case V8QImode: gen = gen_aarch64_zip1v8qi; break;
case V8HImode: gen = gen_aarch64_zip1v8hi; break;
case V4HImode: gen = gen_aarch64_zip1v4hi; break;
case V4SImode: gen = gen_aarch64_zip1v4si; break;
case V2SImode: gen = gen_aarch64_zip1v2si; break;
case V2DImode: gen = gen_aarch64_zip1v2di; break;
case V4HFmode: gen = gen_aarch64_zip1v4hf; break;
case V8HFmode: gen = gen_aarch64_zip1v8hf; break;
case V4SFmode: gen = gen_aarch64_zip1v4sf; break;
case V2SFmode: gen = gen_aarch64_zip1v2sf; break;
case V2DFmode: gen = gen_aarch64_zip1v2df; break;
case E_V16QImode: gen = gen_aarch64_zip1v16qi; break;
case E_V8QImode: gen = gen_aarch64_zip1v8qi; break;
case E_V8HImode: gen = gen_aarch64_zip1v8hi; break;
case E_V4HImode: gen = gen_aarch64_zip1v4hi; break;
case E_V4SImode: gen = gen_aarch64_zip1v4si; break;
case E_V2SImode: gen = gen_aarch64_zip1v2si; break;
case E_V2DImode: gen = gen_aarch64_zip1v2di; break;
case E_V4HFmode: gen = gen_aarch64_zip1v4hf; break;
case E_V8HFmode: gen = gen_aarch64_zip1v8hf; break;
case E_V4SFmode: gen = gen_aarch64_zip1v4sf; break;
case E_V2SFmode: gen = gen_aarch64_zip1v2sf; break;
case E_V2DFmode: gen = gen_aarch64_zip1v2df; break;
default:
return false;
}
@ -13489,18 +13489,18 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d)
switch (d->vmode)
{
case V16QImode: gen = gen_aarch64_extv16qi; break;
case V8QImode: gen = gen_aarch64_extv8qi; break;
case V4HImode: gen = gen_aarch64_extv4hi; break;
case V8HImode: gen = gen_aarch64_extv8hi; break;
case V2SImode: gen = gen_aarch64_extv2si; break;
case V4SImode: gen = gen_aarch64_extv4si; break;
case V4HFmode: gen = gen_aarch64_extv4hf; break;
case V8HFmode: gen = gen_aarch64_extv8hf; break;
case V2SFmode: gen = gen_aarch64_extv2sf; break;
case V4SFmode: gen = gen_aarch64_extv4sf; break;
case V2DImode: gen = gen_aarch64_extv2di; break;
case V2DFmode: gen = gen_aarch64_extv2df; break;
case E_V16QImode: gen = gen_aarch64_extv16qi; break;
case E_V8QImode: gen = gen_aarch64_extv8qi; break;
case E_V4HImode: gen = gen_aarch64_extv4hi; break;
case E_V8HImode: gen = gen_aarch64_extv8hi; break;
case E_V2SImode: gen = gen_aarch64_extv2si; break;
case E_V4SImode: gen = gen_aarch64_extv4si; break;
case E_V4HFmode: gen = gen_aarch64_extv4hf; break;
case E_V8HFmode: gen = gen_aarch64_extv8hf; break;
case E_V2SFmode: gen = gen_aarch64_extv2sf; break;
case E_V4SFmode: gen = gen_aarch64_extv4sf; break;
case E_V2DImode: gen = gen_aarch64_extv2di; break;
case E_V2DFmode: gen = gen_aarch64_extv2df; break;
default:
return false;
}
@ -13544,8 +13544,8 @@ aarch64_evpc_rev (struct expand_vec_perm_d *d)
case 7:
switch (d->vmode)
{
case V16QImode: gen = gen_aarch64_rev64v16qi; break;
case V8QImode: gen = gen_aarch64_rev64v8qi; break;
case E_V16QImode: gen = gen_aarch64_rev64v16qi; break;
case E_V8QImode: gen = gen_aarch64_rev64v8qi; break;
default:
return false;
}
@ -13553,10 +13553,10 @@ aarch64_evpc_rev (struct expand_vec_perm_d *d)
case 3:
switch (d->vmode)
{
case V16QImode: gen = gen_aarch64_rev32v16qi; break;
case V8QImode: gen = gen_aarch64_rev32v8qi; break;
case V8HImode: gen = gen_aarch64_rev64v8hi; break;
case V4HImode: gen = gen_aarch64_rev64v4hi; break;
case E_V16QImode: gen = gen_aarch64_rev32v16qi; break;
case E_V8QImode: gen = gen_aarch64_rev32v8qi; break;
case E_V8HImode: gen = gen_aarch64_rev64v8hi; break;
case E_V4HImode: gen = gen_aarch64_rev64v4hi; break;
default:
return false;
}
@ -13564,16 +13564,16 @@ aarch64_evpc_rev (struct expand_vec_perm_d *d)
case 1:
switch (d->vmode)
{
case V16QImode: gen = gen_aarch64_rev16v16qi; break;
case V8QImode: gen = gen_aarch64_rev16v8qi; break;
case V8HImode: gen = gen_aarch64_rev32v8hi; break;
case V4HImode: gen = gen_aarch64_rev32v4hi; break;
case V4SImode: gen = gen_aarch64_rev64v4si; break;
case V2SImode: gen = gen_aarch64_rev64v2si; break;
case V4SFmode: gen = gen_aarch64_rev64v4sf; break;
case V2SFmode: gen = gen_aarch64_rev64v2sf; break;
case V8HFmode: gen = gen_aarch64_rev64v8hf; break;
case V4HFmode: gen = gen_aarch64_rev64v4hf; break;
case E_V16QImode: gen = gen_aarch64_rev16v16qi; break;
case E_V8QImode: gen = gen_aarch64_rev16v8qi; break;
case E_V8HImode: gen = gen_aarch64_rev32v8hi; break;
case E_V4HImode: gen = gen_aarch64_rev32v4hi; break;
case E_V4SImode: gen = gen_aarch64_rev64v4si; break;
case E_V2SImode: gen = gen_aarch64_rev64v2si; break;
case E_V4SFmode: gen = gen_aarch64_rev64v4sf; break;
case E_V2SFmode: gen = gen_aarch64_rev64v2sf; break;
case E_V8HFmode: gen = gen_aarch64_rev64v8hf; break;
case E_V4HFmode: gen = gen_aarch64_rev64v4hf; break;
default:
return false;
}
@ -13630,18 +13630,18 @@ aarch64_evpc_dup (struct expand_vec_perm_d *d)
switch (vmode)
{
case V16QImode: gen = gen_aarch64_dup_lanev16qi; break;
case V8QImode: gen = gen_aarch64_dup_lanev8qi; break;
case V8HImode: gen = gen_aarch64_dup_lanev8hi; break;
case V4HImode: gen = gen_aarch64_dup_lanev4hi; break;
case V4SImode: gen = gen_aarch64_dup_lanev4si; break;
case V2SImode: gen = gen_aarch64_dup_lanev2si; break;
case V2DImode: gen = gen_aarch64_dup_lanev2di; break;
case V8HFmode: gen = gen_aarch64_dup_lanev8hf; break;
case V4HFmode: gen = gen_aarch64_dup_lanev4hf; break;
case V4SFmode: gen = gen_aarch64_dup_lanev4sf; break;
case V2SFmode: gen = gen_aarch64_dup_lanev2sf; break;
case V2DFmode: gen = gen_aarch64_dup_lanev2df; break;
case E_V16QImode: gen = gen_aarch64_dup_lanev16qi; break;
case E_V8QImode: gen = gen_aarch64_dup_lanev8qi; break;
case E_V8HImode: gen = gen_aarch64_dup_lanev8hi; break;
case E_V4HImode: gen = gen_aarch64_dup_lanev4hi; break;
case E_V4SImode: gen = gen_aarch64_dup_lanev4si; break;
case E_V2SImode: gen = gen_aarch64_dup_lanev2si; break;
case E_V2DImode: gen = gen_aarch64_dup_lanev2di; break;
case E_V8HFmode: gen = gen_aarch64_dup_lanev8hf; break;
case E_V4HFmode: gen = gen_aarch64_dup_lanev4hf; break;
case E_V4SFmode: gen = gen_aarch64_dup_lanev4sf; break;
case E_V2SFmode: gen = gen_aarch64_dup_lanev2sf; break;
case E_V2DFmode: gen = gen_aarch64_dup_lanev2df; break;
default:
return false;
}
@ -14125,25 +14125,25 @@ aarch64_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn **gen_seq,
switch (op_mode)
{
case QImode:
case HImode:
case SImode:
case E_QImode:
case E_HImode:
case E_SImode:
cmp_mode = SImode;
icode = CODE_FOR_cmpsi;
break;
case DImode:
case E_DImode:
cmp_mode = DImode;
icode = CODE_FOR_cmpdi;
break;
case SFmode:
case E_SFmode:
cmp_mode = SFmode;
cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf;
break;
case DFmode:
case E_DFmode:
cmp_mode = DFmode;
cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf;
@ -14200,25 +14200,25 @@ aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
switch (op_mode)
{
case QImode:
case HImode:
case SImode:
case E_QImode:
case E_HImode:
case E_SImode:
cmp_mode = SImode;
icode = CODE_FOR_ccmpsi;
break;
case DImode:
case E_DImode:
cmp_mode = DImode;
icode = CODE_FOR_ccmpdi;
break;
case SFmode:
case E_SFmode:
cmp_mode = SFmode;
cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf;
break;
case DFmode:
case E_DFmode:
cmp_mode = DFmode;
cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf;

42
gcc/config/alpha/alpha.c
View File

@ -695,18 +695,18 @@ alpha_scalar_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case QImode:
case HImode:
case SImode:
case DImode:
case TImode: /* via optabs.c */
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode: /* via optabs.c */
return true;
case SFmode:
case DFmode:
case E_SFmode:
case E_DFmode:
return true;
case TFmode:
case E_TFmode:
return TARGET_HAS_XFLOATING_LIBS;
default:
@ -3076,20 +3076,20 @@ alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
{
switch (GET_MODE (operands[i]))
{
case TFmode:
case E_TFmode:
reg = gen_rtx_REG (TFmode, regno);
regno += 2;
break;
case DFmode:
case E_DFmode:
reg = gen_rtx_REG (DFmode, regno + 32);
regno += 1;
break;
case VOIDmode:
case E_VOIDmode:
gcc_assert (CONST_INT_P (operands[i]));
/* FALLTHRU */
case DImode:
case E_DImode:
reg = gen_rtx_REG (DImode, regno);
regno += 1;
break;
@ -3104,13 +3104,13 @@ alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
switch (GET_MODE (target))
{
case TFmode:
case E_TFmode:
reg = gen_rtx_REG (TFmode, 16);
break;
case DFmode:
case E_DFmode:
reg = gen_rtx_REG (DFmode, 32);
break;
case DImode:
case E_DImode:
reg = gen_rtx_REG (DImode, 0);
break;
default:
@ -4383,16 +4383,16 @@ emit_insxl (machine_mode mode, rtx op1, rtx op2)
switch (mode)
{
case QImode:
case E_QImode:
fn = gen_insbl;
break;
case HImode:
case E_HImode:
fn = gen_inswl;
break;
case SImode:
case E_SImode:
fn = gen_insll;
break;
case DImode:
case E_DImode:
fn = gen_insql;
break;
default:
@ -9574,9 +9574,9 @@ alpha_arg_type (machine_mode mode)
{
switch (mode)
{
case SFmode:
case E_SFmode:
return TARGET_FLOAT_VAX ? FF : FS;
case DFmode:
case E_DFmode:
return TARGET_FLOAT_VAX ? FD : FT;
default:
return I64;

52
gcc/config/arc/arc.c
View File

@ -315,13 +315,13 @@ arc_vector_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case V2HImode:
case E_V2HImode:
return TARGET_PLUS_DMPY;
case V4HImode:
case V2SImode:
case E_V4HImode:
case E_V2SImode:
return TARGET_PLUS_QMACW;
case V4SImode:
case V8HImode:
case E_V4SImode:
case E_V8HImode:
return TARGET_SIMD_SET;
default:
@ -336,9 +336,9 @@ arc_preferred_simd_mode (machine_mode mode)
{
switch (mode)
{
case HImode:
case E_HImode:
return TARGET_PLUS_QMACW ? V4HImode : V2HImode;
case SImode:
case E_SImode:
return V2SImode;
default:
@ -622,11 +622,11 @@ arc_secondary_reload (bool in_p,
{
switch (mode)
{
case QImode:
case E_QImode:
sri->icode =
in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store;
break;
case HImode:
case E_HImode:
sri->icode =
in_p ? CODE_FOR_reload_hi_load : CODE_FOR_reload_hi_store;
break;
@ -1149,8 +1149,8 @@ get_arc_condition_code (rtx comparison)
{
switch (GET_MODE (XEXP (comparison, 0)))
{
case CCmode:
case SImode: /* For BRcc. */
case E_CCmode:
case E_SImode: /* For BRcc. */
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
@ -1165,7 +1165,7 @@ get_arc_condition_code (rtx comparison)
case GEU : return ARC_CC_HS;
default : gcc_unreachable ();
}
case CC_ZNmode:
case E_CC_ZNmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
@ -1175,21 +1175,21 @@ get_arc_condition_code (rtx comparison)
case GT : return ARC_CC_PNZ;
default : gcc_unreachable ();
}
case CC_Zmode:
case E_CC_Zmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
case NE : return ARC_CC_NE;
default : gcc_unreachable ();
}
case CC_Cmode:
case E_CC_Cmode:
switch (GET_CODE (comparison))
{
case LTU : return ARC_CC_C;
case GEU : return ARC_CC_NC;
default : gcc_unreachable ();
}
case CC_FP_GTmode:
case E_CC_FP_GTmode:
if (TARGET_ARGONAUT_SET && TARGET_SPFP)
switch (GET_CODE (comparison))
{
@ -1204,7 +1204,7 @@ get_arc_condition_code (rtx comparison)
case UNLE : return ARC_CC_LS;
default : gcc_unreachable ();
}
case CC_FP_GEmode:
case E_CC_FP_GEmode:
/* Same for FPX and non-FPX. */
switch (GET_CODE (comparison))
{
@ -1212,21 +1212,21 @@ get_arc_condition_code (rtx comparison)
case UNLT : return ARC_CC_LO;
default : gcc_unreachable ();
}
case CC_FP_UNEQmode:
case E_CC_FP_UNEQmode:
switch (GET_CODE (comparison))
{
case UNEQ : return ARC_CC_EQ;
case LTGT : return ARC_CC_NE;
default : gcc_unreachable ();
}
case CC_FP_ORDmode:
case E_CC_FP_ORDmode:
switch (GET_CODE (comparison))
{
case UNORDERED : return ARC_CC_C;
case ORDERED : return ARC_CC_NC;
default : gcc_unreachable ();
}
case CC_FPXmode:
case E_CC_FPXmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
@ -1237,7 +1237,7 @@ get_arc_condition_code (rtx comparison)
case UNEQ : return ARC_CC_LS;
default : gcc_unreachable ();
}
case CC_FPUmode:
case E_CC_FPUmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
@ -1257,7 +1257,7 @@ get_arc_condition_code (rtx comparison)
case UNEQ : /* Fall through. */
default : gcc_unreachable ();
}
case CC_FPU_UNEQmode:
case E_CC_FPU_UNEQmode:
switch (GET_CODE (comparison))
{
case LTGT : return ARC_CC_NE;
@ -3869,8 +3869,8 @@ arc_print_operand (FILE *file, rtx x, int code)
size_suffix:
switch (GET_MODE (XEXP (x, 0)))
{
case QImode: fputs ("b", file); return;
case HImode: fputs ("w", file); return;
case E_QImode: fputs ("b", file); return;
case E_HImode: fputs ("w", file); return;
default: break;
}
break;
@ -5814,10 +5814,10 @@ arc_legitimate_constant_p (machine_mode mode, rtx x)
case CONST_VECTOR:
switch (mode)
{
case V2HImode:
case E_V2HImode:
return TARGET_PLUS_DMPY;
case V2SImode:
case V4HImode:
case E_V2SImode:
case E_V4HImode:
return TARGET_PLUS_QMACW;
default:
return false;

6
gcc/config/arc/arc.h
View File

@ -1314,9 +1314,9 @@ do { \
ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
switch (GET_MODE (BODY)) \
{ \
case QImode: fprintf (FILE, "\t.byte "); break; \
case HImode: fprintf (FILE, "\t.hword "); break; \
case SImode: fprintf (FILE, "\t.word "); break; \
case E_QImode: fprintf (FILE, "\t.byte "); break; \
case E_HImode: fprintf (FILE, "\t.hword "); break; \
case E_SImode: fprintf (FILE, "\t.word "); break; \
default: gcc_unreachable (); \
} \
assemble_name (FILE, label); \

12
gcc/config/arc/arc.md
View File

@ -4043,13 +4043,13 @@
switch (GET_MODE (diff_vec))
{
case SImode:
case E_SImode:
return \"ld.as %0,[%1,%2]%&\";
case HImode:
case E_HImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
return \"ld%_.as %0,[%1,%2]\";
return \"ld%_.x.as %0,[%1,%2]\";
case QImode:
case E_QImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
return \"ldb%? %0,[%1,%2]%&\";
return \"ldb.x %0,[%1,%2]\";
@ -4112,7 +4112,7 @@
switch (GET_MODE (diff_vec))
{
case SImode:
case E_SImode:
/* Max length can be 12 in this case, but this is OK because
2 of these are for alignment, and are anticipated in the length
of the ADDR_DIFF_VEC. */
@ -4124,7 +4124,7 @@
s = \"add %2,%0,2\n\tld.as %2,[pcl,%2]\";
arc_clear_unalign ();
break;
case HImode:
case E_HImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
{
if (satisfies_constraint_Rcq (xop[0]))
@ -4153,7 +4153,7 @@
}
arc_toggle_unalign ();
break;
case QImode:
case E_QImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
{
if ((rtx_equal_p (xop[2], xop[0])

32
gcc/config/arc/predicates.md
View File

@ -430,37 +430,37 @@
a peephole. */
switch (GET_MODE (XEXP (op, 0)))
{
case CC_ZNmode:
case E_CC_ZNmode:
return (code == EQ || code == NE || code == GE || code == LT
|| code == GT);
case CC_Zmode:
case E_CC_Zmode:
return code == EQ || code == NE;
case CC_Cmode:
case E_CC_Cmode:
return code == LTU || code == GEU;
case CC_FP_GTmode:
case E_CC_FP_GTmode:
return code == GT || code == UNLE;
case CC_FP_GEmode:
case E_CC_FP_GEmode:
return code == GE || code == UNLT;
case CC_FP_ORDmode:
case E_CC_FP_ORDmode:
return code == ORDERED || code == UNORDERED;
case CC_FP_UNEQmode:
case E_CC_FP_UNEQmode:
return code == UNEQ || code == LTGT;
case CC_FPXmode:
case E_CC_FPXmode:
return (code == EQ || code == NE || code == UNEQ || code == LTGT
|| code == ORDERED || code == UNORDERED);
case CC_FPUmode:
case E_CC_FPUmode:
return 1;
case CC_FPU_UNEQmode:
case E_CC_FPU_UNEQmode:
return 1;
case CCmode:
case SImode: /* Used for BRcc. */
case E_CCmode:
case E_SImode: /* Used for BRcc. */
return 1;
/* From combiner. */
case QImode: case HImode: case DImode: case SFmode: case DFmode:
case E_QImode: case E_HImode: case E_DImode: case E_SFmode: case E_DFmode:
return 0;
case VOIDmode:
case E_VOIDmode:
return 0;
default:
gcc_unreachable ();
@ -537,11 +537,11 @@
return 1;
switch (mode)
{
case CC_Zmode:
case E_CC_Zmode:
if (GET_MODE (op) == CC_ZNmode)
return 1;
/* Fall through. */
case CC_ZNmode: case CC_Cmode:
case E_CC_ZNmode: case E_CC_Cmode:
return GET_MODE (op) == CCmode;
default:
gcc_unreachable ();

12
gcc/config/arm/aout.h
View File

@ -196,15 +196,15 @@
{ \
switch (GET_MODE(body)) \
{ \
case QImode: \
case E_QImode: \
asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \
VALUE, REL); \
break; \
case HImode: /* TBH */ \
case E_HImode: /* TBH */ \
asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \
VALUE, REL); \
break; \
case SImode: \
case E_SImode: \
asm_fprintf (STREAM, "\t.word\t%LL%d-%LL%d\n", \
VALUE, REL); \
break; \
@ -219,15 +219,15 @@
{ \
switch (GET_MODE(body)) \
{ \
case QImode: /* TBB */ \
case E_QImode: /* TBB */ \
asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \
VALUE, REL); \
break; \
case HImode: /* TBH */ \
case E_HImode: /* TBH */ \
asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \
VALUE, REL); \
break; \
case SImode: \
case E_SImode: \
if (flag_pic) \
asm_fprintf (STREAM, "\t.word\t%LL%d+1-%LL%d\n", VALUE, REL); \
else \

32
gcc/config/arm/arm-builtins.c
View File

@ -815,29 +815,29 @@ arm_simd_builtin_std_type (machine_mode mode,
((q == qualifier_none) ? int##M##_type_node : unsigned_int##M##_type_node);
switch (mode)
{
case QImode:
case E_QImode:
return QUAL_TYPE (QI);
case HImode:
case E_HImode:
return QUAL_TYPE (HI);
case SImode:
case E_SImode:
return QUAL_TYPE (SI);
case DImode:
case E_DImode:
return QUAL_TYPE (DI);
case TImode:
case E_TImode:
return QUAL_TYPE (TI);
case OImode:
case E_OImode:
return arm_simd_intOI_type_node;
case EImode:
case E_EImode:
return arm_simd_intEI_type_node;
case CImode:
case E_CImode:
return arm_simd_intCI_type_node;
case XImode:
case E_XImode:
return arm_simd_intXI_type_node;
case HFmode:
case E_HFmode:
return arm_fp16_type_node;
case SFmode:
case E_SFmode:
return float_type_node;
case DFmode:
case E_DFmode:
return double_type_node;
default:
gcc_unreachable ();
@ -1677,16 +1677,16 @@ arm_init_iwmmxt_builtins (void)
switch (mode)
{
case V8QImode:
case E_V8QImode:
type = v8qi_ftype_v8qi_v8qi;
break;
case V4HImode:
case E_V4HImode:
type = v4hi_ftype_v4hi_v4hi;
break;
case V2SImode:
case E_V2SImode:
type = v2si_ftype_v2si_v2si;
break;
case DImode:
case E_DImode:
type = di_ftype_di_di;
break;

294
gcc/config/arm/arm.c
View File

@ -9069,15 +9069,15 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
/* XXX still guessing. */
switch (GET_MODE (XEXP (x, 0)))
{
case QImode:
case E_QImode:
return (1 + (mode == DImode ? 4 : 0)
+ (MEM_P (XEXP (x, 0)) ? 10 : 0));
case HImode:
case E_HImode:
return (4 + (mode == DImode ? 4 : 0)
+ (MEM_P (XEXP (x, 0)) ? 10 : 0));
case SImode:
case E_SImode:
return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
default:
@ -12243,31 +12243,31 @@ neon_expand_vector_init (rtx target, rtx vals)
x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
switch (mode)
{
case V8QImode:
case E_V8QImode:
emit_insn (gen_neon_vset_lanev8qi (target, x, target, index));
break;
case V16QImode:
case E_V16QImode:
emit_insn (gen_neon_vset_lanev16qi (target, x, target, index));
break;
case V4HImode:
case E_V4HImode:
emit_insn (gen_neon_vset_lanev4hi (target, x, target, index));
break;
case V8HImode:
case E_V8HImode:
emit_insn (gen_neon_vset_lanev8hi (target, x, target, index));
break;
case V2SImode:
case E_V2SImode:
emit_insn (gen_neon_vset_lanev2si (target, x, target, index));
break;
case V4SImode:
case E_V4SImode:
emit_insn (gen_neon_vset_lanev4si (target, x, target, index));
break;
case V2SFmode:
case E_V2SFmode:
emit_insn (gen_neon_vset_lanev2sf (target, x, target, index));
break;
case V4SFmode:
case E_V4SFmode:
emit_insn (gen_neon_vset_lanev4sf (target, x, target, index));
break;
case V2DImode:
case E_V2DImode:
emit_insn (gen_neon_vset_lanev2di (target, x, target, index));
break;
default:
@ -18699,12 +18699,12 @@ arm_attr_length_move_neon (rtx_insn *insn)
mode = GET_MODE (recog_data.operand[0]);
switch (mode)
{
case EImode:
case OImode:
case E_EImode:
case E_OImode:
return 8;
case CImode:
case E_CImode:
return 12;
case XImode:
case E_XImode:
return 16;
default:
gcc_unreachable ();
@ -22783,16 +22783,16 @@ maybe_get_arm_condition_code (rtx comparison)
switch (mode)
{
case CC_DNEmode: code = ARM_NE; goto dominance;
case CC_DEQmode: code = ARM_EQ; goto dominance;
case CC_DGEmode: code = ARM_GE; goto dominance;
case CC_DGTmode: code = ARM_GT; goto dominance;
case CC_DLEmode: code = ARM_LE; goto dominance;
case CC_DLTmode: code = ARM_LT; goto dominance;
case CC_DGEUmode: code = ARM_CS; goto dominance;
case CC_DGTUmode: code = ARM_HI; goto dominance;
case CC_DLEUmode: code = ARM_LS; goto dominance;
case CC_DLTUmode: code = ARM_CC;
case E_CC_DNEmode: code = ARM_NE; goto dominance;
case E_CC_DEQmode: code = ARM_EQ; goto dominance;
case E_CC_DGEmode: code = ARM_GE; goto dominance;
case E_CC_DGTmode: code = ARM_GT; goto dominance;
case E_CC_DLEmode: code = ARM_LE; goto dominance;
case E_CC_DLTmode: code = ARM_LT; goto dominance;
case E_CC_DGEUmode: code = ARM_CS; goto dominance;
case E_CC_DGTUmode: code = ARM_HI; goto dominance;
case E_CC_DLEUmode: code = ARM_LS; goto dominance;
case E_CC_DLTUmode: code = ARM_CC;
dominance:
if (comp_code == EQ)
@ -22801,7 +22801,7 @@ maybe_get_arm_condition_code (rtx comparison)
return code;
return ARM_NV;
case CC_NOOVmode:
case E_CC_NOOVmode:
switch (comp_code)
{
case NE: return ARM_NE;
@ -22811,7 +22811,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CC_Zmode:
case E_CC_Zmode:
switch (comp_code)
{
case NE: return ARM_NE;
@ -22819,7 +22819,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CC_Nmode:
case E_CC_Nmode:
switch (comp_code)
{
case NE: return ARM_MI;
@ -22827,8 +22827,8 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CCFPEmode:
case CCFPmode:
case E_CCFPEmode:
case E_CCFPmode:
/* We can handle all cases except UNEQ and LTGT. */
switch (comp_code)
{
@ -22850,7 +22850,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CC_SWPmode:
case E_CC_SWPmode:
switch (comp_code)
{
case NE: return ARM_NE;
@ -22866,7 +22866,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CC_Cmode:
case E_CC_Cmode:
switch (comp_code)
{
case LTU: return ARM_CS;
@ -22876,7 +22876,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CC_CZmode:
case E_CC_CZmode:
switch (comp_code)
{
case NE: return ARM_NE;
@ -22888,7 +22888,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CC_NCVmode:
case E_CC_NCVmode:
switch (comp_code)
{
case GE: return ARM_GE;
@ -22898,7 +22898,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CC_Vmode:
case E_CC_Vmode:
switch (comp_code)
{
case NE: return ARM_VS;
@ -22906,7 +22906,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
case CCmode:
case E_CCmode:
switch (comp_code)
{
case NE: return ARM_NE;
@ -26565,9 +26565,9 @@ arm_emit_vector_const (FILE *file, rtx x)
switch (GET_MODE (x))
{
case V2SImode: pattern = "%08x"; break;
case V4HImode: pattern = "%04x"; break;
case V8QImode: pattern = "%02x"; break;
case E_V2SImode: pattern = "%08x"; break;
case E_V4HImode: pattern = "%04x"; break;
case E_V8QImode: pattern = "%02x"; break;
default: gcc_unreachable ();
}
@ -26950,15 +26950,15 @@ arm_preferred_simd_mode (machine_mode mode)
if (TARGET_NEON)
switch (mode)
{
case SFmode:
case E_SFmode:
return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode;
case SImode:
case E_SImode:
return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode;
case HImode:
case E_HImode:
return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode;
case QImode:
case E_QImode:
return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode;
case DImode:
case E_DImode:
if (!TARGET_NEON_VECTORIZE_DOUBLE)
return V2DImode;
break;
@ -26969,11 +26969,11 @@ arm_preferred_simd_mode (machine_mode mode)
if (TARGET_REALLY_IWMMXT)
switch (mode)
{
case SImode:
case E_SImode:
return V2SImode;
case HImode:
case E_HImode:
return V4HImode;
case QImode:
case E_QImode:
return V8QImode;
default:;
@ -27675,13 +27675,13 @@ arm_output_iwmmxt_tinsr (rtx *operands)
{
switch (GET_MODE (operands[0]))
{
case V8QImode:
case E_V8QImode:
sprintf (templ, "tinsrb%%?\t%%0, %%2, #%d", i);
break;
case V4HImode:
case E_V4HImode:
sprintf (templ, "tinsrh%%?\t%%0, %%2, #%d", i);
break;
case V2SImode:
case E_V2SImode:
sprintf (templ, "tinsrw%%?\t%%0, %%2, #%d", i);
break;
default:
@ -27703,13 +27703,13 @@ thumb1_output_casesi (rtx *operands)
switch (GET_MODE(diff_vec))
{
case QImode:
case E_QImode:
return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ?
"bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi");
case HImode:
case E_HImode:
return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ?
"bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi");
case SImode:
case E_SImode:
return "bl\t%___gnu_thumb1_case_si";
default:
gcc_unreachable ();
@ -27728,11 +27728,11 @@ thumb2_output_casesi (rtx *operands)
output_asm_insn ("bhi\t%l3", operands);
switch (GET_MODE(diff_vec))
{
case QImode:
case E_QImode:
return "tbb\t[%|pc, %0]";
case HImode:
case E_HImode:
return "tbh\t[%|pc, %0, lsl #1]";
case SImode:
case E_SImode:
if (flag_pic)
{
output_asm_insn ("adr\t%4, %l2", operands);
@ -28208,10 +28208,10 @@ arm_emit_load_exclusive (machine_mode mode, rtx rval, rtx mem, bool acq)
{
switch (mode)
{
case QImode: gen = gen_arm_load_acquire_exclusiveqi; break;
case HImode: gen = gen_arm_load_acquire_exclusivehi; break;
case SImode: gen = gen_arm_load_acquire_exclusivesi; break;
case DImode: gen = gen_arm_load_acquire_exclusivedi; break;
case E_QImode: gen = gen_arm_load_acquire_exclusiveqi; break;
case E_HImode: gen = gen_arm_load_acquire_exclusivehi; break;
case E_SImode: gen = gen_arm_load_acquire_exclusivesi; break;
case E_DImode: gen = gen_arm_load_acquire_exclusivedi; break;
default:
gcc_unreachable ();
}
@ -28220,10 +28220,10 @@ arm_emit_load_exclusive (machine_mode mode, rtx rval, rtx mem, bool acq)
{
switch (mode)
{
case QImode: gen = gen_arm_load_exclusiveqi; break;
case HImode: gen = gen_arm_load_exclusivehi; break;
case SImode: gen = gen_arm_load_exclusivesi; break;
case DImode: gen = gen_arm_load_exclusivedi; break;
case E_QImode: gen = gen_arm_load_exclusiveqi; break;
case E_HImode: gen = gen_arm_load_exclusivehi; break;
case E_SImode: gen = gen_arm_load_exclusivesi; break;
case E_DImode: gen = gen_arm_load_exclusivedi; break;
default:
gcc_unreachable ();
}
@ -28242,10 +28242,10 @@ arm_emit_store_exclusive (machine_mode mode, rtx bval, rtx rval,
{
switch (mode)
{
case QImode: gen = gen_arm_store_release_exclusiveqi; break;
case HImode: gen = gen_arm_store_release_exclusivehi; break;
case SImode: gen = gen_arm_store_release_exclusivesi; break;
case DImode: gen = gen_arm_store_release_exclusivedi; break;
case E_QImode: gen = gen_arm_store_release_exclusiveqi; break;
case E_HImode: gen = gen_arm_store_release_exclusivehi; break;
case E_SImode: gen = gen_arm_store_release_exclusivesi; break;
case E_DImode: gen = gen_arm_store_release_exclusivedi; break;
default:
gcc_unreachable ();
}
@ -28254,10 +28254,10 @@ arm_emit_store_exclusive (machine_mode mode, rtx bval, rtx rval,
{
switch (mode)
{
case QImode: gen = gen_arm_store_exclusiveqi; break;
case HImode: gen = gen_arm_store_exclusivehi; break;
case SImode: gen = gen_arm_store_exclusivesi; break;
case DImode: gen = gen_arm_store_exclusivedi; break;
case E_QImode: gen = gen_arm_store_exclusiveqi; break;
case E_HImode: gen = gen_arm_store_exclusivehi; break;
case E_SImode: gen = gen_arm_store_exclusivesi; break;
case E_DImode: gen = gen_arm_store_exclusivedi; break;
default:
gcc_unreachable ();
}
@ -28305,22 +28305,22 @@ arm_expand_compare_and_swap (rtx operands[])
switch (mode)
{
case QImode:
case HImode:
case E_QImode:
case E_HImode:
/* For narrow modes, we're going to perform the comparison in SImode,
so do the zero-extension now. */
rval = gen_reg_rtx (SImode);
oldval = convert_modes (SImode, mode, oldval, true);
/* FALLTHRU */
case SImode:
case E_SImode:
/* Force the value into a register if needed. We waited until after
the zero-extension above to do this properly. */
if (!arm_add_operand (oldval, SImode))
oldval = force_reg (SImode, oldval);
break;
case DImode:
case E_DImode:
if (!cmpdi_operand (oldval, mode))
oldval = force_reg (mode, oldval);
break;
@ -28333,10 +28333,10 @@ arm_expand_compare_and_swap (rtx operands[])
{
switch (mode)
{
case QImode: gen = gen_atomic_compare_and_swapt1qi_1; break;
case HImode: gen = gen_atomic_compare_and_swapt1hi_1; break;
case SImode: gen = gen_atomic_compare_and_swapt1si_1; break;
case DImode: gen = gen_atomic_compare_and_swapt1di_1; break;
case E_QImode: gen = gen_atomic_compare_and_swapt1qi_1; break;
case E_HImode: gen = gen_atomic_compare_and_swapt1hi_1; break;
case E_SImode: gen = gen_atomic_compare_and_swapt1si_1; break;
case E_DImode: gen = gen_atomic_compare_and_swapt1di_1; break;
default:
gcc_unreachable ();
}
@ -28345,10 +28345,10 @@ arm_expand_compare_and_swap (rtx operands[])
{
switch (mode)
{
case QImode: gen = gen_atomic_compare_and_swap32qi_1; break;
case HImode: gen = gen_atomic_compare_and_swap32hi_1; break;
case SImode: gen = gen_atomic_compare_and_swap32si_1; break;
case DImode: gen = gen_atomic_compare_and_swap32di_1; break;
case E_QImode: gen = gen_atomic_compare_and_swap32qi_1; break;
case E_HImode: gen = gen_atomic_compare_and_swap32hi_1; break;
case E_SImode: gen = gen_atomic_compare_and_swap32si_1; break;
case E_DImode: gen = gen_atomic_compare_and_swap32di_1; break;
default:
gcc_unreachable ();
}
@ -28769,16 +28769,16 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
switch (d->vmode)
{
case V16QImode: gen = gen_neon_vuzpv16qi_internal; break;
case V8QImode: gen = gen_neon_vuzpv8qi_internal; break;
case V8HImode: gen = gen_neon_vuzpv8hi_internal; break;
case V4HImode: gen = gen_neon_vuzpv4hi_internal; break;
case V8HFmode: gen = gen_neon_vuzpv8hf_internal; break;
case V4HFmode: gen = gen_neon_vuzpv4hf_internal; break;
case V4SImode: gen = gen_neon_vuzpv4si_internal; break;
case V2SImode: gen = gen_neon_vuzpv2si_internal; break;
case V2SFmode: gen = gen_neon_vuzpv2sf_internal; break;
case V4SFmode: gen = gen_neon_vuzpv4sf_internal; break;
case E_V16QImode: gen = gen_neon_vuzpv16qi_internal; break;
case E_V8QImode: gen = gen_neon_vuzpv8qi_internal; break;
case E_V8HImode: gen = gen_neon_vuzpv8hi_internal; break;
case E_V4HImode: gen = gen_neon_vuzpv4hi_internal; break;
case E_V8HFmode: gen = gen_neon_vuzpv8hf_internal; break;
case E_V4HFmode: gen = gen_neon_vuzpv4hf_internal; break;
case E_V4SImode: gen = gen_neon_vuzpv4si_internal; break;
case E_V2SImode: gen = gen_neon_vuzpv2si_internal; break;
case E_V2SFmode: gen = gen_neon_vuzpv2sf_internal; break;
case E_V4SFmode: gen = gen_neon_vuzpv4sf_internal; break;
default:
gcc_unreachable ();
}
@ -28844,16 +28844,16 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
switch (d->vmode)
{
case V16QImode: gen = gen_neon_vzipv16qi_internal; break;
case V8QImode: gen = gen_neon_vzipv8qi_internal; break;
case V8HImode: gen = gen_neon_vzipv8hi_internal; break;
case V4HImode: gen = gen_neon_vzipv4hi_internal; break;
case V8HFmode: gen = gen_neon_vzipv8hf_internal; break;
case V4HFmode: gen = gen_neon_vzipv4hf_internal; break;
case V4SImode: gen = gen_neon_vzipv4si_internal; break;
case V2SImode: gen = gen_neon_vzipv2si_internal; break;
case V2SFmode: gen = gen_neon_vzipv2sf_internal; break;
case V4SFmode: gen = gen_neon_vzipv4sf_internal; break;
case E_V16QImode: gen = gen_neon_vzipv16qi_internal; break;
case E_V8QImode: gen = gen_neon_vzipv8qi_internal; break;
case E_V8HImode: gen = gen_neon_vzipv8hi_internal; break;
case E_V4HImode: gen = gen_neon_vzipv4hi_internal; break;
case E_V8HFmode: gen = gen_neon_vzipv8hf_internal; break;
case E_V4HFmode: gen = gen_neon_vzipv4hf_internal; break;
case E_V4SImode: gen = gen_neon_vzipv4si_internal; break;
case E_V2SImode: gen = gen_neon_vzipv2si_internal; break;
case E_V2SFmode: gen = gen_neon_vzipv2sf_internal; break;
case E_V4SFmode: gen = gen_neon_vzipv4sf_internal; break;
default:
gcc_unreachable ();
}
@ -28889,8 +28889,8 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
case 7:
switch (d->vmode)
{
case V16QImode: gen = gen_neon_vrev64v16qi; break;
case V8QImode: gen = gen_neon_vrev64v8qi; break;
case E_V16QImode: gen = gen_neon_vrev64v16qi; break;
case E_V8QImode: gen = gen_neon_vrev64v8qi; break;
default:
return false;
}
@ -28898,12 +28898,12 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
case 3:
switch (d->vmode)
{
case V16QImode: gen = gen_neon_vrev32v16qi; break;
case V8QImode: gen = gen_neon_vrev32v8qi; break;
case V8HImode: gen = gen_neon_vrev64v8hi; break;
case V4HImode: gen = gen_neon_vrev64v4hi; break;
case V8HFmode: gen = gen_neon_vrev64v8hf; break;
case V4HFmode: gen = gen_neon_vrev64v4hf; break;
case E_V16QImode: gen = gen_neon_vrev32v16qi; break;
case E_V8QImode: gen = gen_neon_vrev32v8qi; break;
case E_V8HImode: gen = gen_neon_vrev64v8hi; break;
case E_V4HImode: gen = gen_neon_vrev64v4hi; break;
case E_V8HFmode: gen = gen_neon_vrev64v8hf; break;
case E_V4HFmode: gen = gen_neon_vrev64v4hf; break;
default:
return false;
}
@ -28911,14 +28911,14 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
case 1:
switch (d->vmode)
{
case V16QImode: gen = gen_neon_vrev16v16qi; break;
case V8QImode: gen = gen_neon_vrev16v8qi; break;
case V8HImode: gen = gen_neon_vrev32v8hi; break;
case V4HImode: gen = gen_neon_vrev32v4hi; break;
case V4SImode: gen = gen_neon_vrev64v4si; break;
case V2SImode: gen = gen_neon_vrev64v2si; break;
case V4SFmode: gen = gen_neon_vrev64v4sf; break;
case V2SFmode: gen = gen_neon_vrev64v2sf; break;
case E_V16QImode: gen = gen_neon_vrev16v16qi; break;
case E_V8QImode: gen = gen_neon_vrev16v8qi; break;
case E_V8HImode: gen = gen_neon_vrev32v8hi; break;
case E_V4HImode: gen = gen_neon_vrev32v4hi; break;
case E_V4SImode: gen = gen_neon_vrev64v4si; break;
case E_V2SImode: gen = gen_neon_vrev64v2si; break;
case E_V4SFmode: gen = gen_neon_vrev64v4sf; break;
case E_V2SFmode: gen = gen_neon_vrev64v2sf; break;
default:
return false;
}
@ -28983,16 +28983,16 @@ arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
switch (d->vmode)
{
case V16QImode: gen = gen_neon_vtrnv16qi_internal; break;
case V8QImode: gen = gen_neon_vtrnv8qi_internal; break;
case V8HImode: gen = gen_neon_vtrnv8hi_internal; break;
case V4HImode: gen = gen_neon_vtrnv4hi_internal; break;
case V8HFmode: gen = gen_neon_vtrnv8hf_internal; break;
case V4HFmode: gen = gen_neon_vtrnv4hf_internal; break;
case V4SImode: gen = gen_neon_vtrnv4si_internal; break;
case V2SImode: gen = gen_neon_vtrnv2si_internal; break;
case V2SFmode: gen = gen_neon_vtrnv2sf_internal; break;
case V4SFmode: gen = gen_neon_vtrnv4sf_internal; break;
case E_V16QImode: gen = gen_neon_vtrnv16qi_internal; break;
case E_V8QImode: gen = gen_neon_vtrnv8qi_internal; break;
case E_V8HImode: gen = gen_neon_vtrnv8hi_internal; break;
case E_V4HImode: gen = gen_neon_vtrnv4hi_internal; break;
case E_V8HFmode: gen = gen_neon_vtrnv8hf_internal; break;
case E_V4HFmode: gen = gen_neon_vtrnv4hf_internal; break;
case E_V4SImode: gen = gen_neon_vtrnv4si_internal; break;
case E_V2SImode: gen = gen_neon_vtrnv2si_internal; break;
case E_V2SFmode: gen = gen_neon_vtrnv2sf_internal; break;
case E_V4SFmode: gen = gen_neon_vtrnv4sf_internal; break;
default:
gcc_unreachable ();
}
@ -29058,17 +29058,17 @@ arm_evpc_neon_vext (struct expand_vec_perm_d *d)
switch (d->vmode)
{
case V16QImode: gen = gen_neon_vextv16qi; break;
case V8QImode: gen = gen_neon_vextv8qi; break;
case V4HImode: gen = gen_neon_vextv4hi; break;
case V8HImode: gen = gen_neon_vextv8hi; break;
case V2SImode: gen = gen_neon_vextv2si; break;
case V4SImode: gen = gen_neon_vextv4si; break;
case V4HFmode: gen = gen_neon_vextv4hf; break;
case V8HFmode: gen = gen_neon_vextv8hf; break;
case V2SFmode: gen = gen_neon_vextv2sf; break;
case V4SFmode: gen = gen_neon_vextv4sf; break;
case V2DImode: gen = gen_neon_vextv2di; break;
case E_V16QImode: gen = gen_neon_vextv16qi; break;
case E_V8QImode: gen = gen_neon_vextv8qi; break;
case E_V4HImode: gen = gen_neon_vextv4hi; break;
case E_V8HImode: gen = gen_neon_vextv8hi; break;
case E_V2SImode: gen = gen_neon_vextv2si; break;
case E_V4SImode: gen = gen_neon_vextv4si; break;
case E_V4HFmode: gen = gen_neon_vextv4hf; break;
case E_V8HFmode: gen = gen_neon_vextv8hf; break;
case E_V2SFmode: gen = gen_neon_vextv2sf; break;
case E_V4SFmode: gen = gen_neon_vextv4sf; break;
case E_V2DImode: gen = gen_neon_vextv2di; break;
default:
return false;
}
@ -29613,21 +29613,21 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
switch (mode)
{
case SImode:
case E_SImode:
if (!arm_add_operand (*op1, mode))
*op1 = force_reg (mode, *op1);
if (!arm_add_operand (*op2, mode))
*op2 = force_reg (mode, *op2);
return true;
case DImode:
case E_DImode:
if (!cmpdi_operand (*op1, mode))
*op1 = force_reg (mode, *op1);
if (!cmpdi_operand (*op2, mode))
*op2 = force_reg (mode, *op2);
return true;
case HFmode:
case E_HFmode:
if (!TARGET_VFP_FP16INST)
break;
/* FP16 comparisons are done in SF mode. */
@ -29635,8 +29635,8 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
*op1 = convert_to_mode (mode, *op1, 1);
*op2 = convert_to_mode (mode, *op2, 1);
/* Fall through. */
case SFmode:
case DFmode:
case E_SFmode:
case E_DFmode:
if (!vfp_compare_operand (*op1, mode))
*op1 = force_reg (mode, *op1);
if (!vfp_compare_operand (*op2, mode))

4
gcc/config/arm/neon.md
View File

@ -2532,12 +2532,12 @@
but we will never expand to UNSPECs for the integer comparisons. */
switch (<MODE>mode)
{
case V2SFmode:
case E_V2SFmode:
emit_insn (gen_neon_vc<cmp_op>v2sf_insn_unspec (operands[0],
operands[1],
operands[2]));
break;
case V4SFmode:
case E_V4SFmode:
emit_insn (gen_neon_vc<cmp_op>v4sf_insn_unspec (operands[0],
operands[1],
operands[2]));

96
gcc/config/avr/avr-c.c
View File

@ -79,24 +79,24 @@ avr_resolve_overloaded_builtin (unsigned int iloc, tree fndecl, void *vargs)
switch (TYPE_MODE (type0))
{
case QQmode: id = AVR_BUILTIN_ABSHR; break;
case HQmode: id = AVR_BUILTIN_ABSR; break;
case SQmode: id = AVR_BUILTIN_ABSLR; break;
case DQmode: id = AVR_BUILTIN_ABSLLR; break;
case E_QQmode: id = AVR_BUILTIN_ABSHR; break;
case E_HQmode: id = AVR_BUILTIN_ABSR; break;
case E_SQmode: id = AVR_BUILTIN_ABSLR; break;
case E_DQmode: id = AVR_BUILTIN_ABSLLR; break;
case HAmode: id = AVR_BUILTIN_ABSHK; break;
case SAmode: id = AVR_BUILTIN_ABSK; break;
case DAmode: id = AVR_BUILTIN_ABSLK; break;
case TAmode: id = AVR_BUILTIN_ABSLLK; break;
case E_HAmode: id = AVR_BUILTIN_ABSHK; break;
case E_SAmode: id = AVR_BUILTIN_ABSK; break;
case E_DAmode: id = AVR_BUILTIN_ABSLK; break;
case E_TAmode: id = AVR_BUILTIN_ABSLLK; break;
case UQQmode:
case UHQmode:
case USQmode:
case UDQmode:
case UHAmode:
case USAmode:
case UDAmode:
case UTAmode:
case E_UQQmode:
case E_UHQmode:
case E_USQmode:
case E_UDQmode:
case E_UHAmode:
case E_USAmode:
case E_UDAmode:
case E_UTAmode:
warning_at (loc, 0, "using %qs with unsigned type has no effect",
"absfx");
return args[0];
@ -147,25 +147,25 @@ avr_resolve_overloaded_builtin (unsigned int iloc, tree fndecl, void *vargs)
switch (TYPE_MODE (type0))
{
case QQmode: id = AVR_BUILTIN_ROUNDHR; break;
case HQmode: id = AVR_BUILTIN_ROUNDR; break;
case SQmode: id = AVR_BUILTIN_ROUNDLR; break;
case DQmode: id = AVR_BUILTIN_ROUNDLLR; break;
case E_QQmode: id = AVR_BUILTIN_ROUNDHR; break;
case E_HQmode: id = AVR_BUILTIN_ROUNDR; break;
case E_SQmode: id = AVR_BUILTIN_ROUNDLR; break;
case E_DQmode: id = AVR_BUILTIN_ROUNDLLR; break;
case UQQmode: id = AVR_BUILTIN_ROUNDUHR; break;
case UHQmode: id = AVR_BUILTIN_ROUNDUR; break;
case USQmode: id = AVR_BUILTIN_ROUNDULR; break;
case UDQmode: id = AVR_BUILTIN_ROUNDULLR; break;
case E_UQQmode: id = AVR_BUILTIN_ROUNDUHR; break;
case E_UHQmode: id = AVR_BUILTIN_ROUNDUR; break;
case E_USQmode: id = AVR_BUILTIN_ROUNDULR; break;
case E_UDQmode: id = AVR_BUILTIN_ROUNDULLR; break;
case HAmode: id = AVR_BUILTIN_ROUNDHK; break;
case SAmode: id = AVR_BUILTIN_ROUNDK; break;
case DAmode: id = AVR_BUILTIN_ROUNDLK; break;
case TAmode: id = AVR_BUILTIN_ROUNDLLK; break;
case E_HAmode: id = AVR_BUILTIN_ROUNDHK; break;
case E_SAmode: id = AVR_BUILTIN_ROUNDK; break;
case E_DAmode: id = AVR_BUILTIN_ROUNDLK; break;
case E_TAmode: id = AVR_BUILTIN_ROUNDLLK; break;
case UHAmode: id = AVR_BUILTIN_ROUNDUHK; break;
case USAmode: id = AVR_BUILTIN_ROUNDUK; break;
case UDAmode: id = AVR_BUILTIN_ROUNDULK; break;
case UTAmode: id = AVR_BUILTIN_ROUNDULLK; break;
case E_UHAmode: id = AVR_BUILTIN_ROUNDUHK; break;
case E_USAmode: id = AVR_BUILTIN_ROUNDUK; break;
case E_UDAmode: id = AVR_BUILTIN_ROUNDULK; break;
case E_UTAmode: id = AVR_BUILTIN_ROUNDULLK; break;
default:
error_at (loc, "no matching fixed-point overload found for %qs",
@ -204,25 +204,25 @@ avr_resolve_overloaded_builtin (unsigned int iloc, tree fndecl, void *vargs)
switch (TYPE_MODE (type0))
{
case QQmode: id = AVR_BUILTIN_COUNTLSHR; break;
case HQmode: id = AVR_BUILTIN_COUNTLSR; break;
case SQmode: id = AVR_BUILTIN_COUNTLSLR; break;
case DQmode: id = AVR_BUILTIN_COUNTLSLLR; break;
case E_QQmode: id = AVR_BUILTIN_COUNTLSHR; break;
case E_HQmode: id = AVR_BUILTIN_COUNTLSR; break;
case E_SQmode: id = AVR_BUILTIN_COUNTLSLR; break;
case E_DQmode: id = AVR_BUILTIN_COUNTLSLLR; break;
case UQQmode: id = AVR_BUILTIN_COUNTLSUHR; break;
case UHQmode: id = AVR_BUILTIN_COUNTLSUR; break;
case USQmode: id = AVR_BUILTIN_COUNTLSULR; break;
case UDQmode: id = AVR_BUILTIN_COUNTLSULLR; break;
case E_UQQmode: id = AVR_BUILTIN_COUNTLSUHR; break;
case E_UHQmode: id = AVR_BUILTIN_COUNTLSUR; break;
case E_USQmode: id = AVR_BUILTIN_COUNTLSULR; break;
case E_UDQmode: id = AVR_BUILTIN_COUNTLSULLR; break;
case HAmode: id = AVR_BUILTIN_COUNTLSHK; break;
case SAmode: id = AVR_BUILTIN_COUNTLSK; break;
case DAmode: id = AVR_BUILTIN_COUNTLSLK; break;
case TAmode: id = AVR_BUILTIN_COUNTLSLLK; break;
case E_HAmode: id = AVR_BUILTIN_COUNTLSHK; break;
case E_SAmode: id = AVR_BUILTIN_COUNTLSK; break;
case E_DAmode: id = AVR_BUILTIN_COUNTLSLK; break;
case E_TAmode: id = AVR_BUILTIN_COUNTLSLLK; break;
case UHAmode: id = AVR_BUILTIN_COUNTLSUHK; break;
case USAmode: id = AVR_BUILTIN_COUNTLSUK; break;
case UDAmode: id = AVR_BUILTIN_COUNTLSULK; break;
case UTAmode: id = AVR_BUILTIN_COUNTLSULLK; break;
case E_UHAmode: id = AVR_BUILTIN_COUNTLSUHK; break;
case E_USAmode: id = AVR_BUILTIN_COUNTLSUK; break;
case E_UDAmode: id = AVR_BUILTIN_COUNTLSULK; break;
case E_UTAmode: id = AVR_BUILTIN_COUNTLSULLK; break;
default:
error_at (loc, "no matching fixed-point overload found for %qs",

70
gcc/config/avr/avr.c
View File

@ -10806,14 +10806,14 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case NEG:
switch (mode)
{
case QImode:
case SFmode:
case E_QImode:
case E_SFmode:
*total = COSTS_N_INSNS (1);
break;
case HImode:
case PSImode:
case SImode:
case E_HImode:
case E_PSImode:
case E_SImode:
*total = COSTS_N_INSNS (2 * GET_MODE_SIZE (mode) - 1);
break;
@ -10826,8 +10826,8 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case ABS:
switch (mode)
{
case QImode:
case SFmode:
case E_QImode:
case E_SFmode:
*total = COSTS_N_INSNS (1);
break;
@ -10859,7 +10859,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case PLUS:
switch (mode)
{
case QImode:
case E_QImode:
if (AVR_HAVE_MUL
&& MULT == GET_CODE (XEXP (x, 0))
&& register_operand (XEXP (x, 1), QImode))
@ -10876,7 +10876,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
*total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, 1, speed);
break;
case HImode:
case E_HImode:
if (AVR_HAVE_MUL
&& (MULT == GET_CODE (XEXP (x, 0))
|| ASHIFT == GET_CODE (XEXP (x, 0)))
@ -10903,7 +10903,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
*total = COSTS_N_INSNS (2);
break;
case PSImode:
case E_PSImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (3);
@ -10916,7 +10916,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
*total = COSTS_N_INSNS (3);
break;
case SImode:
case E_SImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (4);
@ -10994,7 +10994,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case MULT:
switch (mode)
{
case QImode:
case E_QImode:
if (AVR_HAVE_MUL)
*total = COSTS_N_INSNS (!speed ? 3 : 4);
else if (!speed)
@ -11003,7 +11003,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
return false;
break;
case HImode:
case E_HImode:
if (AVR_HAVE_MUL)
{
rtx op0 = XEXP (x, 0);
@ -11047,15 +11047,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
return false;
break;
case PSImode:
case E_PSImode:
if (!speed)
*total = COSTS_N_INSNS (AVR_HAVE_JMP_CALL ? 2 : 1);
else
*total = 10;
break;
case SImode:
case DImode:
case E_SImode:
case E_DImode:
if (AVR_HAVE_MUL)
{
if (!speed)
@ -11113,19 +11113,19 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case ROTATE:
switch (mode)
{
case QImode:
case E_QImode:
if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 4)
*total = COSTS_N_INSNS (1);
break;
case HImode:
case E_HImode:
if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 8)
*total = COSTS_N_INSNS (3);
break;
case SImode:
case E_SImode:
if (CONST_INT_P (XEXP (x, 1)))
switch (INTVAL (XEXP (x, 1)))
{
@ -11148,7 +11148,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case ASHIFT:
switch (mode)
{
case QImode:
case E_QImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 4 : 17);
@ -11167,7 +11167,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case HImode:
case E_HImode:
if (AVR_HAVE_MUL)
{
if (const_2_to_7_operand (XEXP (x, 1), HImode)
@ -11232,7 +11232,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case PSImode:
case E_PSImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 6 : 73);
@ -11257,7 +11257,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case SImode:
case E_SImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 7 : 113);
@ -11300,7 +11300,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case ASHIFTRT:
switch (mode)
{
case QImode:
case E_QImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 4 : 17);
@ -11321,7 +11321,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case HImode:
case E_HImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 5 : 41);
@ -11367,7 +11367,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case PSImode:
case E_PSImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 6 : 73);
@ -11394,7 +11394,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case SImode:
case E_SImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 7 : 113);
@ -11443,7 +11443,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
switch (mode)
{
case QImode:
case E_QImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 4 : 17);
@ -11462,7 +11462,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case HImode:
case E_HImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 5 : 41);
@ -11511,7 +11511,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case PSImode:
case E_PSImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 6 : 73);
@ -11536,7 +11536,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
}
break;
case SImode:
case E_SImode:
if (!CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (!speed ? 7 : 113);
@ -11579,14 +11579,14 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
case COMPARE:
switch (GET_MODE (XEXP (x, 0)))
{
case QImode:
case E_QImode:
*total = COSTS_N_INSNS (1);
if (!CONST_INT_P (XEXP (x, 1)))
*total += avr_operand_rtx_cost (XEXP (x, 1), QImode, code,
1, speed);
break;
case HImode:
case E_HImode:
*total = COSTS_N_INSNS (2);
if (!CONST_INT_P (XEXP (x, 1)))
*total += avr_operand_rtx_cost (XEXP (x, 1), HImode, code,
@ -11595,13 +11595,13 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
*total += COSTS_N_INSNS (1);
break;
case PSImode:
case E_PSImode:
*total = COSTS_N_INSNS (3);
if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) != 0)
*total += COSTS_N_INSNS (2);
break;
case SImode:
case E_SImode:
*total = COSTS_N_INSNS (4);
if (!CONST_INT_P (XEXP (x, 1)))
*total += avr_operand_rtx_cost (XEXP (x, 1), SImode, code,

14
gcc/config/c6x/c6x.c
View File

@ -6226,11 +6226,11 @@ c6x_vector_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case V2HImode:
case V4QImode:
case V2SImode:
case V4HImode:
case V8QImode:
case E_V2HImode:
case E_V4QImode:
case E_V2SImode:
case E_V4HImode:
case E_V8QImode:
return true;
default:
return false;
@ -6243,9 +6243,9 @@ c6x_preferred_simd_mode (machine_mode mode)
{
switch (mode)
{
case HImode:
case E_HImode:
return V2HImode;
case QImode:
case E_QImode:
return V4QImode;
default:

24
gcc/config/epiphany/epiphany.c
View File

@ -270,7 +270,7 @@ get_epiphany_condition_code (rtx comparison)
{
switch (GET_MODE (XEXP (comparison, 0)))
{
case CCmode:
case E_CCmode:
switch (GET_CODE (comparison))
{
case EQ : return 0;
@ -286,28 +286,28 @@ get_epiphany_condition_code (rtx comparison)
default : gcc_unreachable ();
}
case CC_N_NEmode:
case E_CC_N_NEmode:
switch (GET_CODE (comparison))
{
case EQ: return 6;
case NE: return 7;
default: gcc_unreachable ();
}
case CC_C_LTUmode:
case E_CC_C_LTUmode:
switch (GET_CODE (comparison))
{
case GEU: return 2;
case LTU: return 3;
default: gcc_unreachable ();
}
case CC_C_GTUmode:
case E_CC_C_GTUmode:
switch (GET_CODE (comparison))
{
case LEU: return 3;
case GTU: return 2;
default: gcc_unreachable ();
}
case CC_FPmode:
case E_CC_FPmode:
switch (GET_CODE (comparison))
{
case EQ: return 10;
@ -316,14 +316,14 @@ get_epiphany_condition_code (rtx comparison)
case LE: return 13;
default: gcc_unreachable ();
}
case CC_FP_EQmode:
case E_CC_FP_EQmode:
switch (GET_CODE (comparison))
{
case EQ: return 0;
case NE: return 1;
default: gcc_unreachable ();
}
case CC_FP_GTEmode:
case E_CC_FP_GTEmode:
switch (GET_CODE (comparison))
{
case EQ: return 0;
@ -334,14 +334,14 @@ get_epiphany_condition_code (rtx comparison)
case UNLT : return 7;
default: gcc_unreachable ();
}
case CC_FP_ORDmode:
case E_CC_FP_ORDmode:
switch (GET_CODE (comparison))
{
case ORDERED: return 9;
case UNORDERED: return 8;
default: gcc_unreachable ();
}
case CC_FP_UNEQmode:
case E_CC_FP_UNEQmode:
switch (GET_CODE (comparison))
{
case UNEQ: return 9;
@ -803,9 +803,9 @@ epiphany_rtx_costs (rtx x, machine_mode mode, int outer_code,
{
/* There are a number of single-insn combiner patterns that use
the flag side effects of arithmetic. */
case CC_N_NEmode:
case CC_C_LTUmode:
case CC_C_GTUmode:
case E_CC_N_NEmode:
case E_CC_C_LTUmode:
case E_CC_C_GTUmode:
return true;
default:
return false;

24
gcc/config/epiphany/predicates.md
View File

@ -223,31 +223,31 @@
return 0;
switch (GET_MODE (cc))
{
case CC_Zmode:
case CC_N_NEmode:
case CC_FP_EQmode:
case E_CC_Zmode:
case E_CC_N_NEmode:
case E_CC_FP_EQmode:
return REGNO (cc) == CC_REGNUM && (code == EQ || code == NE);
case CC_C_LTUmode:
case E_CC_C_LTUmode:
return REGNO (cc) == CC_REGNUM && (code == LTU || code == GEU);
case CC_C_GTUmode:
case E_CC_C_GTUmode:
return REGNO (cc) == CC_REGNUM && (code == GTU || code == LEU);
case CC_FPmode:
case E_CC_FPmode:
return (REGNO (cc) == CCFP_REGNUM
&& (code == EQ || code == NE || code == LT || code == LE));
case CC_FP_GTEmode:
case E_CC_FP_GTEmode:
return (REGNO (cc) == CC_REGNUM
&& (code == EQ || code == NE || code == GT || code == GE
|| code == UNLE || code == UNLT));
case CC_FP_ORDmode:
case E_CC_FP_ORDmode:
return REGNO (cc) == CC_REGNUM && (code == ORDERED || code == UNORDERED);
case CC_FP_UNEQmode:
case E_CC_FP_UNEQmode:
return REGNO (cc) == CC_REGNUM && (code == UNEQ || code == LTGT);
case CCmode:
case E_CCmode:
return REGNO (cc) == CC_REGNUM;
/* From combiner. */
case QImode: case SImode: case SFmode: case HImode:
case E_QImode: case E_SImode: case E_SFmode: case E_HImode:
/* From cse.c:dead_libcall_p. */
case DFmode:
case E_DFmode:
return 0;
default:
gcc_unreachable ();

100
gcc/config/frv/frv.c
View File

@ -3893,10 +3893,10 @@ condexec_memory_operand (rtx op, machine_mode mode)
default:
return FALSE;
case QImode:
case HImode:
case SImode:
case SFmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_SFmode:
break;
}
@ -3935,16 +3935,16 @@ frv_emit_move (machine_mode mode, rtx dest, rtx src)
switch (mode)
{
case SImode:
case E_SImode:
if (frv_emit_movsi (dest, src))
return;
break;
case QImode:
case HImode:
case DImode:
case SFmode:
case DFmode:
case E_QImode:
case E_HImode:
case E_DImode:
case E_SFmode:
case E_DFmode:
if (!reload_in_progress
&& !reload_completed
&& !register_operand (dest, mode)
@ -4249,14 +4249,14 @@ output_move_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "ldsb%I1%U1 %M1,%0";
case HImode:
case E_HImode:
return "ldsh%I1%U1 %M1,%0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "ld%I1%U1 %M1, %0";
}
}
@ -4323,14 +4323,14 @@ output_move_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "ldbf%I1%U1 %M1,%0";
case HImode:
case E_HImode:
return "ldhf%I1%U1 %M1,%0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "ldf%I1%U1 %M1, %0";
}
}
@ -4368,14 +4368,14 @@ output_move_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "stb%I0%U0 %1, %M0";
case HImode:
case E_HImode:
return "sth%I0%U0 %1, %M0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "st%I0%U0 %1, %M0";
}
}
@ -4387,14 +4387,14 @@ output_move_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "stbf%I0%U0 %1, %M0";
case HImode:
case E_HImode:
return "sthf%I0%U0 %1, %M0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "stf%I0%U0 %1, %M0";
}
}
@ -4407,14 +4407,14 @@ output_move_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "stb%I0%U0 %., %M0";
case HImode:
case E_HImode:
return "sth%I0%U0 %., %M0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "st%I0%U0 %., %M0";
}
}
@ -4591,14 +4591,14 @@ output_condmove_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "cldsb%I3%U3 %M3, %2, %1, %e0";
case HImode:
case E_HImode:
return "cldsh%I3%U3 %M3, %2, %1, %e0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "cld%I3%U3 %M3, %2, %1, %e0";
}
}
@ -4652,14 +4652,14 @@ output_condmove_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "cstb%I2%U2 %3, %M2, %1, %e0";
case HImode:
case E_HImode:
return "csth%I2%U2 %3, %M2, %1, %e0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "cst%I2%U2 %3, %M2, %1, %e0";
}
}
@ -4676,14 +4676,14 @@ output_condmove_single (rtx operands[], rtx insn)
default:
break;
case QImode:
case E_QImode:
return "cstb%I2%U2 %., %M2, %1, %e0";
case HImode:
case E_HImode:
return "csth%I2%U2 %., %M2, %1, %e0";
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return "cst%I2%U2 %., %M2, %1, %e0";
}
}
@ -6579,15 +6579,15 @@ frv_hard_regno_mode_ok (int regno, machine_mode mode)
switch (mode)
{
case CCmode:
case CC_UNSmode:
case CC_NZmode:
case E_CCmode:
case E_CC_UNSmode:
case E_CC_NZmode:
return ICC_P (regno) || GPR_P (regno);
case CC_CCRmode:
case E_CC_CCRmode:
return CR_P (regno) || GPR_P (regno);
case CC_FPmode:
case E_CC_FPmode:
return FCC_P (regno) || GPR_P (regno);
default:
@ -8619,13 +8619,13 @@ frv_matching_accg_mode (machine_mode mode)
{
switch (mode)
{
case V4SImode:
case E_V4SImode:
return V4QImode;
case DImode:
case E_DImode:
return HImode;
case SImode:
case E_SImode:
return QImode;
default:

108
gcc/config/h8300/h8300.c
View File

@ -1033,11 +1033,11 @@ split_adds_subs (machine_mode mode, rtx *operands)
switch (mode)
{
case HImode:
case E_HImode:
gen_add = gen_addhi3;
break;
case SImode:
case E_SImode:
gen_add = gen_addsi3;
break;
@ -1328,12 +1328,12 @@ h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
if (TARGET_H8300SX)
switch (GET_MODE (x))
{
case QImode:
case HImode:
case E_QImode:
case E_HImode:
*total = COSTS_N_INSNS (!speed ? 4 : 10);
return false;
case SImode:
case E_SImode:
*total = COSTS_N_INSNS (!speed ? 4 : 18);
return false;
@ -1347,12 +1347,12 @@ h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
if (TARGET_H8300SX)
switch (GET_MODE (x))
{
case QImode:
case HImode:
case E_QImode:
case E_HImode:
*total = COSTS_N_INSNS (2);
return false;
case SImode:
case E_SImode:
*total = COSTS_N_INSNS (5);
return false;
@ -1697,18 +1697,18 @@ h8300_print_operand (FILE *file, rtx x, int code)
case REG:
switch (GET_MODE (x))
{
case QImode:
case E_QImode:
#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
fprintf (file, "%s", byte_reg (x, 0));
#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
fprintf (file, "%s", names_big[REGNO (x)]);
#endif
break;
case HImode:
case E_HImode:
fprintf (file, "%s", names_big[REGNO (x)]);
break;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
fprintf (file, "%s", names_extended[REGNO (x)]);
break;
default:
@ -2808,7 +2808,7 @@ compute_mov_length (rtx *operands)
switch (mode)
{
case QImode:
case E_QImode:
if (addr == NULL_RTX)
return 2;
@ -2820,7 +2820,7 @@ compute_mov_length (rtx *operands)
base_length = 4;
break;
case HImode:
case E_HImode:
if (addr == NULL_RTX)
{
if (REG_P (src))
@ -2835,7 +2835,7 @@ compute_mov_length (rtx *operands)
base_length = 4;
break;
case SImode:
case E_SImode:
if (addr == NULL_RTX)
{
if (REG_P (src))
@ -2862,7 +2862,7 @@ compute_mov_length (rtx *operands)
base_length = 8;
break;
case SFmode:
case E_SFmode:
if (addr == NULL_RTX)
{
if (REG_P (src))
@ -2914,7 +2914,7 @@ compute_mov_length (rtx *operands)
switch (mode)
{
case QImode:
case E_QImode:
if (addr == NULL_RTX)
return 2;
@ -2926,7 +2926,7 @@ compute_mov_length (rtx *operands)
base_length = 8;
break;
case HImode:
case E_HImode:
if (addr == NULL_RTX)
{
if (REG_P (src))
@ -2941,7 +2941,7 @@ compute_mov_length (rtx *operands)
base_length = 8;
break;
case SImode:
case E_SImode:
if (addr == NULL_RTX)
{
if (REG_P (src))
@ -2982,7 +2982,7 @@ compute_mov_length (rtx *operands)
base_length = 10;
break;
case SFmode:
case E_SFmode:
if (addr == NULL_RTX)
{
if (REG_P (src))
@ -3304,7 +3304,7 @@ output_logical_op (machine_mode mode, rtx *operands)
switch (mode)
{
case HImode:
case E_HImode:
/* First, see if we can finish with one insn. */
if ((TARGET_H8300H || TARGET_H8300S)
&& b0 != 0
@ -3329,7 +3329,7 @@ output_logical_op (machine_mode mode, rtx *operands)
}
}
break;
case SImode:
case E_SImode:
if (TARGET_H8300H || TARGET_H8300S)
{
/* Determine if the lower half can be taken care of in no more
@ -3469,7 +3469,7 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
switch (mode)
{
case HImode:
case E_HImode:
/* First, see if we can finish with one insn. */
if ((TARGET_H8300H || TARGET_H8300S)
&& b0 != 0
@ -3489,7 +3489,7 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
length += 2;
}
break;
case SImode:
case E_SImode:
if (TARGET_H8300H || TARGET_H8300S)
{
/* Determine if the lower half can be taken care of in no more
@ -3613,7 +3613,7 @@ compute_logical_op_cc (machine_mode mode, rtx *operands)
switch (mode)
{
case HImode:
case E_HImode:
/* First, see if we can finish with one insn. */
if ((TARGET_H8300H || TARGET_H8300S)
&& b0 != 0
@ -3622,7 +3622,7 @@ compute_logical_op_cc (machine_mode mode, rtx *operands)
cc = CC_SET_ZNV;
}
break;
case SImode:
case E_SImode:
if (TARGET_H8300H || TARGET_H8300S)
{
/* Determine if the lower half can be taken care of in no more
@ -4533,19 +4533,19 @@ h8300_shift_needs_scratch_p (int count, machine_mode mode)
/* Find the shift algorithm. */
switch (mode)
{
case QImode:
case E_QImode:
a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
break;
case HImode:
case E_HImode:
a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
break;
case SImode:
case E_SImode:
a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
@ -4578,13 +4578,13 @@ output_a_shift (rtx *operands)
switch (mode)
{
case QImode:
case E_QImode:
shift_mode = QIshift;
break;
case HImode:
case E_HImode:
shift_mode = HIshift;
break;
case SImode:
case E_SImode:
shift_mode = SIshift;
break;
default:
@ -4670,11 +4670,11 @@ output_a_shift (rtx *operands)
/* Now mask off the high bits. */
switch (mode)
{
case QImode:
case E_QImode:
sprintf (insn_buf, "and\t#%d,%%X0", mask);
break;
case HImode:
case E_HImode:
gcc_assert (TARGET_H8300H || TARGET_H8300S);
sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
break;
@ -4746,13 +4746,13 @@ compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
switch (mode)
{
case QImode:
case E_QImode:
shift_mode = QIshift;
break;
case HImode:
case E_HImode:
shift_mode = HIshift;
break;
case SImode:
case E_SImode:
shift_mode = SIshift;
break;
default:
@ -4842,13 +4842,13 @@ compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
/* Now mask off the high bits. */
switch (mode)
{
case QImode:
case E_QImode:
wlength += 1;
break;
case HImode:
case E_HImode:
wlength += 2;
break;
case SImode:
case E_SImode:
gcc_assert (!TARGET_H8300);
wlength += 3;
break;
@ -4894,13 +4894,13 @@ compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
switch (mode)
{
case QImode:
case E_QImode:
shift_mode = QIshift;
break;
case HImode:
case E_HImode:
shift_mode = HIshift;
break;
case SImode:
case E_SImode:
shift_mode = SIshift;
break;
default:
@ -5007,13 +5007,13 @@ expand_a_rotate (rtx operands[])
/* Rotate by one bit. */
switch (mode)
{
case QImode:
case E_QImode:
emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
break;
case HImode:
case E_HImode:
emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
break;
case SImode:
case E_SImode:
emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
break;
default:
@ -5035,13 +5035,13 @@ expand_a_rotate (rtx operands[])
/* Rotate by AMOUNT bits. */
switch (mode)
{
case QImode:
case E_QImode:
emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
break;
case HImode:
case E_HImode:
emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
break;
case SImode:
case E_SImode:
emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
break;
default:
@ -5070,13 +5070,13 @@ output_a_rotate (enum rtx_code code, rtx *operands)
switch (mode)
{
case QImode:
case E_QImode:
rotate_mode = QIshift;
break;
case HImode:
case E_HImode:
rotate_mode = HIshift;
break;
case SImode:
case E_SImode:
rotate_mode = SIshift;
break;
default:
@ -5123,13 +5123,13 @@ output_a_rotate (enum rtx_code code, rtx *operands)
{
switch (mode)
{
case HImode:
case E_HImode:
/* This code works on any family. */
insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
output_asm_insn (insn_buf, operands);
break;
case SImode:
case E_SImode:
/* This code works on the H8/300H and H8S. */
insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
output_asm_insn (insn_buf, operands);

1474
gcc/config/i386/i386.c
View File

File diff suppressed because it is too large Load Diff

40
gcc/config/i386/sse.md
View File

@ -11592,20 +11592,20 @@
tmp = "pandn";
switch (<MODE>mode)
{
case V64QImode:
case V32HImode:
case E_V64QImode:
case E_V32HImode:
/* There is no vpandnb or vpandnw instruction, nor vpandn for
512-bit vectors. Use vpandnq instead. */
ssesuffix = "q";
break;
case V16SImode:
case V8DImode:
case E_V16SImode:
case E_V8DImode:
ssesuffix = "<ssemodesuffix>";
break;
case V8SImode:
case V4DImode:
case V4SImode:
case V2DImode:
case E_V8SImode:
case E_V4DImode:
case E_V4SImode:
case E_V2DImode:
ssesuffix = TARGET_AVX512VL ? "<ssemodesuffix>" : "";
break;
default:
@ -11722,14 +11722,14 @@
tmp = "p<logic>";
switch (<MODE>mode)
{
case V16SImode:
case V8DImode:
case E_V16SImode:
case E_V8DImode:
ssesuffix = "<ssemodesuffix>";
break;
case V8SImode:
case V4DImode:
case V4SImode:
case V2DImode:
case E_V8SImode:
case E_V4DImode:
case E_V4SImode:
case E_V2DImode:
ssesuffix = TARGET_AVX512VL ? "<ssemodesuffix>" : "";
break;
default:
@ -11819,14 +11819,14 @@
tmp = "p<logic>";
switch (<MODE>mode)
{
case V64QImode:
case V32HImode:
case E_V64QImode:
case E_V32HImode:
ssesuffix = "q";
break;
case V32QImode:
case V16HImode:
case V16QImode:
case V8HImode:
case E_V32QImode:
case E_V16HImode:
case E_V16QImode:
case E_V8HImode:
ssesuffix = TARGET_AVX512VL ? "q" : "";
break;
default:

80
gcc/config/ia64/ia64.c
View File

@ -1909,7 +1909,7 @@ ia64_expand_vecint_compare (enum rtx_code code, machine_mode mode,
{
switch (mode)
{
case V2SImode:
case E_V2SImode:
{
rtx t1, t2, mask;
@ -1928,8 +1928,8 @@ ia64_expand_vecint_compare (enum rtx_code code, machine_mode mode,
}
break;
case V8QImode:
case V4HImode:
case E_V8QImode:
case E_V4HImode:
/* Perform a parallel unsigned saturating subtraction. */
x = gen_reg_rtx (mode);
emit_insn (gen_rtx_SET (x, gen_rtx_US_MINUS (mode, op0, op1)));
@ -2447,10 +2447,10 @@ ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
case MEMMODEL_CONSUME:
switch (mode)
{
case QImode: icode = CODE_FOR_cmpxchg_acq_qi; break;
case HImode: icode = CODE_FOR_cmpxchg_acq_hi; break;
case SImode: icode = CODE_FOR_cmpxchg_acq_si; break;
case DImode: icode = CODE_FOR_cmpxchg_acq_di; break;
case E_QImode: icode = CODE_FOR_cmpxchg_acq_qi; break;
case E_HImode: icode = CODE_FOR_cmpxchg_acq_hi; break;
case E_SImode: icode = CODE_FOR_cmpxchg_acq_si; break;
case E_DImode: icode = CODE_FOR_cmpxchg_acq_di; break;
default:
gcc_unreachable ();
}
@ -2463,10 +2463,10 @@ ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
case MEMMODEL_SYNC_SEQ_CST:
switch (mode)
{
case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
case E_QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
case E_HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
case E_SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
case E_DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
default:
gcc_unreachable ();
}
@ -4899,9 +4899,9 @@ ia64_arg_type (machine_mode mode)
{
switch (mode)
{
case SFmode:
case E_SFmode:
return FS;
case DFmode:
case E_DFmode:
return FT;
default:
return I64;
@ -7895,15 +7895,15 @@ ia64_mode_to_int (machine_mode mode)
{
switch (mode)
{
case BImode: return 0; /* SPEC_MODE_FIRST */
case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
case HImode: return 2;
case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
case DImode: return 4;
case SFmode: return 5;
case DFmode: return 6;
case XFmode: return 7;
case TImode:
case E_BImode: return 0; /* SPEC_MODE_FIRST */
case E_QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
case E_HImode: return 2;
case E_SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
case E_DImode: return 4;
case E_SFmode: return 5;
case E_DFmode: return 6;
case E_XFmode: return 7;
case E_TImode:
/* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
mentioned in itanium[12].md. Predicate fp_register_operand also
needs to be defined. Bottom line: better disable for now. */
@ -10968,20 +10968,20 @@ ia64_scalar_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
return true;
case SFmode:
case DFmode:
case XFmode:
case RFmode:
case E_SFmode:
case E_DFmode:
case E_XFmode:
case E_RFmode:
return true;
case TFmode:
case E_TFmode:
return true;
default:
@ -10994,12 +10994,12 @@ ia64_vector_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case V8QImode:
case V4HImode:
case V2SImode:
case E_V8QImode:
case E_V4HImode:
case E_V2SImode:
return true;
case V2SFmode:
case E_V2SFmode:
return true;
default:
@ -11438,8 +11438,8 @@ expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
switch (d->vmode)
{
case V2SImode:
case V2SFmode:
case E_V2SImode:
case E_V2SFmode:
/* Implementable by interleave. */
perm2[0] = elt;
perm2[1] = elt + 2;
@ -11447,7 +11447,7 @@ expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
gcc_assert (ok);
break;
case V8QImode:
case E_V8QImode:
/* Implementable by extract + broadcast. */
if (BYTES_BIG_ENDIAN)
elt = 7 - elt;
@ -11458,7 +11458,7 @@ expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp)));
break;
case V4HImode:
case E_V4HImode:
/* Should have been matched directly by vec_select. */
default:
gcc_unreachable ();

70
gcc/config/iq2000/iq2000.c
View File

@ -624,17 +624,17 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
{
default:
break;
case SFmode:
case E_SFmode:
ret = "lw\t%0,%1";
break;
case SImode:
case CCmode:
case E_SImode:
case E_CCmode:
ret = "lw\t%0,%1";
break;
case HImode:
case E_HImode:
ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
break;
case QImode:
case E_QImode:
ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
break;
}
@ -734,10 +734,10 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
{
switch (mode)
{
case SFmode: ret = "sw\t%1,%0"; break;
case SImode: ret = "sw\t%1,%0"; break;
case HImode: ret = "sh\t%1,%0"; break;
case QImode: ret = "sb\t%1,%0"; break;
case E_SFmode: ret = "sw\t%1,%0"; break;
case E_SImode: ret = "sw\t%1,%0"; break;
case E_HImode: ret = "sh\t%1,%0"; break;
case E_QImode: ret = "sb\t%1,%0"; break;
default: break;
}
}
@ -747,10 +747,10 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
{
switch (mode)
{
case SFmode: ret = "sw\t%z1,%0"; break;
case SImode: ret = "sw\t%z1,%0"; break;
case HImode: ret = "sh\t%z1,%0"; break;
case QImode: ret = "sb\t%z1,%0"; break;
case E_SFmode: ret = "sw\t%z1,%0"; break;
case E_SImode: ret = "sw\t%z1,%0"; break;
case E_HImode: ret = "sh\t%z1,%0"; break;
case E_QImode: ret = "sb\t%z1,%0"; break;
default: break;
}
}
@ -759,10 +759,10 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
{
switch (mode)
{
case SFmode: ret = "sw\t%.,%0"; break;
case SImode: ret = "sw\t%.,%0"; break;
case HImode: ret = "sh\t%.,%0"; break;
case QImode: ret = "sb\t%.,%0"; break;
case E_SFmode: ret = "sw\t%.,%0"; break;
case E_SImode: ret = "sw\t%.,%0"; break;
case E_HImode: ret = "sh\t%.,%0"; break;
case E_QImode: ret = "sb\t%.,%0"; break;
default: break;
}
}
@ -1152,7 +1152,7 @@ iq2000_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
cum->arg_number++;
switch (mode)
{
case VOIDmode:
case E_VOIDmode:
break;
default:
@ -1164,37 +1164,37 @@ iq2000_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
/ UNITS_PER_WORD);
break;
case BLKmode:
case E_BLKmode:
cum->gp_reg_found = 1;
cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
/ UNITS_PER_WORD);
break;
case SFmode:
case E_SFmode:
cum->arg_words ++;
if (! cum->gp_reg_found && cum->arg_number <= 2)
cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
break;
case DFmode:
case E_DFmode:
cum->arg_words += 2;
if (! cum->gp_reg_found && cum->arg_number <= 2)
cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
break;
case DImode:
case E_DImode:
cum->gp_reg_found = 1;
cum->arg_words += 2;
break;
case TImode:
case E_TImode:
cum->gp_reg_found = 1;
cum->arg_words += 4;
break;
case QImode:
case HImode:
case SImode:
case E_QImode:
case E_HImode:
case E_SImode:
cum->gp_reg_found = 1;
cum->arg_words ++;
break;
@ -1232,11 +1232,11 @@ iq2000_function_arg (cumulative_args_t cum_v, machine_mode mode,
cum->last_arg_fp = 0;
switch (mode)
{
case SFmode:
case E_SFmode:
regbase = GP_ARG_FIRST;
break;
case DFmode:
case E_DFmode:
cum->arg_words += cum->arg_words & 1;
regbase = GP_ARG_FIRST;
@ -1247,25 +1247,25 @@ iq2000_function_arg (cumulative_args_t cum_v, machine_mode mode,
|| GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT);
/* FALLTHRU */
case BLKmode:
case E_BLKmode:
if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
cum->arg_words += (cum->arg_words & 1);
regbase = GP_ARG_FIRST;
break;
case VOIDmode:
case QImode:
case HImode:
case SImode:
case E_VOIDmode:
case E_QImode:
case E_HImode:
case E_SImode:
regbase = GP_ARG_FIRST;
break;
case DImode:
case E_DImode:
cum->arg_words += (cum->arg_words & 1);
regbase = GP_ARG_FIRST;
break;
case TImode:
case E_TImode:
cum->arg_words += (cum->arg_words & 3);
regbase = GP_ARG_FIRST;
break;

2
gcc/config/m32c/m32c.c
View File

@ -666,7 +666,7 @@ m32c_preferred_reload_class (rtx x, reg_class_t rclass)
{
switch (GET_MODE (x))
{
case QImode:
case E_QImode:
newclass = HL_REGS;
break;
default:

28
gcc/config/m68k/m68k.c
View File

@ -1621,11 +1621,11 @@ output_dbcc_and_branch (rtx *operands)
to compensate for the fact that dbcc decrements in HImode. */
switch (GET_MODE (operands[0]))
{
case SImode:
case E_SImode:
output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
break;
case HImode:
case E_HImode:
break;
default:
@ -5270,9 +5270,9 @@ rtx
m68k_libcall_value (machine_mode mode)
{
switch (mode) {
case SFmode:
case DFmode:
case XFmode:
case E_SFmode:
case E_DFmode:
case E_XFmode:
if (TARGET_68881)
return gen_rtx_REG (mode, FP0_REG);
break;
@ -5293,9 +5293,9 @@ m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
mode = TYPE_MODE (valtype);
switch (mode) {
case SFmode:
case DFmode:
case XFmode:
case E_SFmode:
case E_DFmode:
case E_XFmode:
if (TARGET_68881)
return gen_rtx_REG (mode, FP0_REG);
break;
@ -5521,11 +5521,11 @@ sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
{
switch (GET_MODE (op))
{
case SFmode:
case E_SFmode:
return OP_TYPE_IMM_W;
case VOIDmode:
case DFmode:
case E_VOIDmode:
case E_DFmode:
return OP_TYPE_IMM_L;
default:
@ -5539,13 +5539,13 @@ sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
{
switch (GET_MODE (op))
{
case QImode:
case E_QImode:
return OP_TYPE_IMM_Q;
case HImode:
case E_HImode:
return OP_TYPE_IMM_W;
case SImode:
case E_SImode:
return OP_TYPE_IMM_L;
default:

12
gcc/config/mcore/mcore.c
View File

@ -1282,11 +1282,11 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
switch (GET_MODE (src)) /* r-m */
{
case SImode:
case E_SImode:
return "ldw\t%0,%1";
case HImode:
case E_HImode:
return "ld.h\t%0,%1";
case QImode:
case E_QImode:
return "ld.b\t%0,%1";
default:
gcc_unreachable ();
@ -1313,11 +1313,11 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else if (GET_CODE (dst) == MEM) /* m-r */
switch (GET_MODE (dst))
{
case SImode:
case E_SImode:
return "stw\t%1,%0";
case HImode:
case E_HImode:
return "st.h\t%1,%0";
case QImode:
case E_QImode:
return "st.b\t%1,%0";
default:
gcc_unreachable ();

36
gcc/config/microblaze/microblaze.c
View File

@ -1481,7 +1481,7 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
cum->arg_number++;
switch (mode)
{
case VOIDmode:
case E_VOIDmode:
break;
default:
@ -1493,33 +1493,33 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
/ UNITS_PER_WORD);
break;
case BLKmode:
case E_BLKmode:
cum->gp_reg_found = 1;
cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
/ UNITS_PER_WORD);
break;
case SFmode:
case E_SFmode:
cum->arg_words++;
if (!cum->gp_reg_found && cum->arg_number <= 2)
cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
break;
case DFmode:
case E_DFmode:
cum->arg_words += 2;
if (!cum->gp_reg_found && cum->arg_number <= 2)
cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
break;
case DImode:
case E_DImode:
cum->gp_reg_found = 1;
cum->arg_words += 2;
break;
case QImode:
case HImode:
case SImode:
case TImode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_TImode:
cum->gp_reg_found = 1;
cum->arg_words++;
break;
@ -1543,21 +1543,21 @@ microblaze_function_arg (cumulative_args_t cum_v, machine_mode mode,
cum->last_arg_fp = 0;
switch (mode)
{
case SFmode:
case DFmode:
case VOIDmode:
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case E_SFmode:
case E_DFmode:
case E_VOIDmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
regbase = GP_ARG_FIRST;
break;
default:
gcc_assert (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
|| GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT);
/* FALLTHRU */
case BLKmode:
case E_BLKmode:
regbase = GP_ARG_FIRST;
break;
}

136
gcc/config/mips/mips.c
View File

@ -7611,7 +7611,7 @@ mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
general registers. */
switch (GET_MODE (retval))
{
case SCmode:
case E_SCmode:
mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
TARGET_BIG_ENDIAN
? FP_REG_FIRST + 2
@ -7641,16 +7641,16 @@ mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
}
break;
case SFmode:
case E_SFmode:
mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
break;
case DCmode:
case E_DCmode:
mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
FP_REG_FIRST + 2);
/* FALLTHRU */
case DFmode:
case V2SFmode:
case E_DFmode:
case E_V2SFmode:
gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| GET_MODE (retval) != V2SFmode);
mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
@ -9116,18 +9116,18 @@ mips_print_operand (FILE *file, rtx op, int letter)
case 'v':
switch (GET_MODE (op))
{
case V16QImode:
case E_V16QImode:
fprintf (file, "b");
break;
case V8HImode:
case E_V8HImode:
fprintf (file, "h");
break;
case V4SImode:
case V4SFmode:
case E_V4SImode:
case E_V4SFmode:
fprintf (file, "w");
break;
case V2DImode:
case V2DFmode:
case E_V2DImode:
case E_V2DFmode:
fprintf (file, "d");
break;
default:
@ -12974,14 +12974,14 @@ mips_mode_ok_for_mov_fmt_p (machine_mode mode)
{
switch (mode)
{
case CCFmode:
case SFmode:
case E_CCFmode:
case E_SFmode:
return TARGET_HARD_FLOAT;
case DFmode:
case E_DFmode:
return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
case V2SFmode:
case E_V2SFmode:
return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
default:
@ -13286,22 +13286,22 @@ mips_vector_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case V2SFmode:
case E_V2SFmode:
return TARGET_PAIRED_SINGLE_FLOAT;
case V2HImode:
case V4QImode:
case V2HQmode:
case V2UHQmode:
case V2HAmode:
case V2UHAmode:
case V4QQmode:
case V4UQQmode:
case E_V2HImode:
case E_V4QImode:
case E_V2HQmode:
case E_V2UHQmode:
case E_V2HAmode:
case E_V2UHAmode:
case E_V4QQmode:
case E_V4UQQmode:
return TARGET_DSP;
case V2SImode:
case V4HImode:
case V8QImode:
case E_V2SImode:
case E_V4HImode:
case E_V8QImode:
return TARGET_LOONGSON_VECTORS;
default:
@ -13335,19 +13335,19 @@ mips_preferred_simd_mode (machine_mode mode)
switch (mode)
{
case QImode:
case E_QImode:
return V16QImode;
case HImode:
case E_HImode:
return V8HImode;
case SImode:
case E_SImode:
return V4SImode;
case DImode:
case E_DImode:
return V2DImode;
case SFmode:
case E_SFmode:
return V4SFmode;
case DFmode:
case E_DFmode:
return V2DFmode;
default:
@ -21139,7 +21139,7 @@ mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
t1 = gen_reg_rtx (d->vmode);
switch (d->vmode)
{
case V4HImode:
case E_V4HImode:
emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
if (odd)
@ -21148,7 +21148,7 @@ mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
break;
case V8QImode:
case E_V8QImode:
t2 = gen_reg_rtx (d->vmode);
t3 = gen_reg_rtx (d->vmode);
emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
@ -21481,7 +21481,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
{
switch (imode)
{
case V4SImode:
case E_V4SImode:
if (BYTES_BIG_ENDIAN != high_p)
unpack = gen_msa_ilvl_w;
else
@ -21490,7 +21490,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
cmpFunc = gen_msa_clt_s_w;
break;
case V8HImode:
case E_V8HImode:
if (BYTES_BIG_ENDIAN != high_p)
unpack = gen_msa_ilvl_h;
else
@ -21499,7 +21499,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
cmpFunc = gen_msa_clt_s_h;
break;
case V16QImode:
case E_V16QImode:
if (BYTES_BIG_ENDIAN != high_p)
unpack = gen_msa_ilvl_b;
else
@ -21532,14 +21532,14 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
switch (imode)
{
case V8QImode:
case E_V8QImode:
if (high_p)
unpack = gen_loongson_punpckhbh;
else
unpack = gen_loongson_punpcklbh;
cmpFunc = gen_loongson_pcmpgtb;
break;
case V4HImode:
case E_V4HImode:
if (high_p)
unpack = gen_loongson_punpckhhw;
else
@ -21612,10 +21612,10 @@ mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt)
t1 = gen_reg_rtx (vmode);
switch (vmode)
{
case V8QImode:
case E_V8QImode:
emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
break;
case V4HImode:
case E_V4HImode:
emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
break;
default:
@ -21757,10 +21757,10 @@ mips_expand_vector_init (rtx target, rtx vals)
{
switch (vmode)
{
case V16QImode:
case V8HImode:
case V4SImode:
case V2DImode:
case E_V16QImode:
case E_V8HImode:
case E_V4SImode:
case E_V2DImode:
temp = gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0));
emit_move_insn (target, temp);
return;
@ -21780,18 +21780,18 @@ mips_expand_vector_init (rtx target, rtx vals)
switch (vmode)
{
case V16QImode:
case V8HImode:
case V4SImode:
case V2DImode:
case E_V16QImode:
case E_V8HImode:
case E_V4SImode:
case E_V2DImode:
mips_emit_move (target, gen_rtx_VEC_DUPLICATE (vmode, temp));
break;
case V4SFmode:
case E_V4SFmode:
emit_insn (gen_msa_splati_w_f_scalar (target, temp));
break;
case V2DFmode:
case E_V2DFmode:
emit_insn (gen_msa_splati_d_f_scalar (target, temp));
break;
@ -21814,27 +21814,27 @@ mips_expand_vector_init (rtx target, rtx vals)
emit_move_insn (temp, XVECEXP (vals, 0, i));
switch (vmode)
{
case V16QImode:
case E_V16QImode:
emit_insn (gen_vec_setv16qi (target, temp, GEN_INT (i)));
break;
case V8HImode:
case E_V8HImode:
emit_insn (gen_vec_setv8hi (target, temp, GEN_INT (i)));
break;
case V4SImode:
case E_V4SImode:
emit_insn (gen_vec_setv4si (target, temp, GEN_INT (i)));
break;
case V2DImode:
case E_V2DImode:
emit_insn (gen_vec_setv2di (target, temp, GEN_INT (i)));
break;
case V4SFmode:
case E_V4SFmode:
emit_insn (gen_vec_setv4sf (target, temp, GEN_INT (i)));
break;
case V2DFmode:
case E_V2DFmode:
emit_insn (gen_vec_setv2df (target, temp, GEN_INT (i)));
break;
@ -21897,7 +21897,7 @@ mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
fold = gen_reg_rtx (vmode);
switch (vmode)
{
case V2SFmode:
case E_V2SFmode:
/* Use PUL/PLU to produce { L, H } op { H, L }.
By reversing the pair order, rather than a pure interleave high,
we avoid erroneous exceptional conditions that we might otherwise
@ -21908,12 +21908,12 @@ mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
gcc_assert (ok);
break;
case V2SImode:
case E_V2SImode:
/* Use interleave to produce { H, L } op { H, H }. */
emit_insn (gen_loongson_punpckhwd (fold, last, last));
break;
case V4HImode:
case E_V4HImode:
/* Perform the first reduction with interleave,
and subsequent reductions with shifts. */
emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
@ -21927,7 +21927,7 @@ mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
emit_insn (gen_vec_shr_v4hi (fold, last, x));
break;
case V8QImode:
case E_V8QImode:
emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
next = gen_reg_rtx (vmode);
@ -22008,10 +22008,10 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1)
switch (cmp_mode)
{
case V16QImode:
case V8HImode:
case V4SImode:
case V2DImode:
case E_V16QImode:
case E_V8HImode:
case E_V4SImode:
case E_V2DImode:
switch (cond)
{
case NE:
@ -22039,8 +22039,8 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1)
emit_move_insn (dest, gen_rtx_NOT (GET_MODE (dest), dest));
break;
case V4SFmode:
case V2DFmode:
case E_V4SFmode:
case E_V2DFmode:
switch (cond)
{
case UNORDERED:

4
gcc/config/mips/mips.md
View File

@ -6415,14 +6415,14 @@
switch (GET_MODE (diff_vec))
{
case HImode:
case E_HImode:
output_asm_insn ("sll\t%3,%0,1", operands);
output_asm_insn ("<d>la\t%2,%1", operands);
output_asm_insn ("<d>addu\t%3,%2,%3", operands);
output_asm_insn ("lh\t%3,0(%3)", operands);
break;
case SImode:
case E_SImode:
output_asm_insn ("sll\t%3,%0,2", operands);
output_asm_insn ("<d>la\t%2,%1", operands);
output_asm_insn ("<d>addu\t%3,%2,%3", operands);

24
gcc/config/mn10300/mn10300.c
View File

@ -279,18 +279,18 @@ mn10300_print_operand (FILE *file, rtx x, int code)
switch (GET_MODE (x))
{
case DFmode:
case E_DFmode:
REAL_VALUE_TO_TARGET_DOUBLE
(*CONST_DOUBLE_REAL_VALUE (x), val);
fprintf (file, "0x%lx", val[0]);
break;;
case SFmode:
case E_SFmode:
REAL_VALUE_TO_TARGET_SINGLE
(*CONST_DOUBLE_REAL_VALUE (x), val[0]);
fprintf (file, "0x%lx", val[0]);
break;;
case VOIDmode:
case DImode:
case E_VOIDmode:
case E_DImode:
mn10300_print_operand_address (file,
GEN_INT (CONST_DOUBLE_LOW (x)));
break;
@ -338,15 +338,15 @@ mn10300_print_operand (FILE *file, rtx x, int code)
switch (GET_MODE (x))
{
case DFmode:
case E_DFmode:
REAL_VALUE_TO_TARGET_DOUBLE
(*CONST_DOUBLE_REAL_VALUE (x), val);
fprintf (file, "0x%lx", val[1]);
break;;
case SFmode:
case E_SFmode:
gcc_unreachable ();
case VOIDmode:
case DImode:
case E_VOIDmode:
case E_DImode:
mn10300_print_operand_address (file,
GEN_INT (CONST_DOUBLE_HIGH (x)));
break;
@ -2672,13 +2672,13 @@ cc_flags_for_mode (machine_mode mode)
{
switch (mode)
{
case CCmode:
case E_CCmode:
return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V;
case CCZNCmode:
case E_CCZNCmode:
return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C;
case CCZNmode:
case E_CCZNmode:
return CC_FLAG_Z | CC_FLAG_N;
case CC_FLOATmode:
case E_CC_FLOATmode:
return -1;
default:
gcc_unreachable ();

8
gcc/config/msp430/msp430.c
View File

@ -3547,10 +3547,10 @@ msp430_print_operand (FILE * file, rtx op, int letter)
case 'b':
switch (GET_MODE (op))
{
case QImode: fprintf (file, ".B"); return;
case HImode: fprintf (file, ".W"); return;
case PSImode: fprintf (file, ".A"); return;
case SImode: fprintf (file, ".A"); return;
case E_QImode: fprintf (file, ".B"); return;
case E_HImode: fprintf (file, ".W"); return;
case E_PSImode: fprintf (file, ".A"); return;
case E_SImode: fprintf (file, ".A"); return;
default:
return;
}

16
gcc/config/nds32/nds32-md-auxiliary.c
View File

@ -114,21 +114,21 @@ nds32_mem_format (rtx op)
switch (mode_test)
{
case QImode:
case E_QImode:
/* 333 format. */
if (val >= 0 && val < 8 && regno < 8)
return ADDRESS_LO_REG_IMM3U;
break;
case HImode:
case E_HImode:
/* 333 format. */
if (val >= 0 && val < 16 && (val % 2 == 0) && regno < 8)
return ADDRESS_LO_REG_IMM3U;
break;
case SImode:
case SFmode:
case DFmode:
case E_SImode:
case E_SFmode:
case E_DFmode:
/* fp imply 37 format. */
if ((regno == FP_REGNUM) &&
(val >= 0 && val < 512 && (val % 4 == 0)))
@ -802,13 +802,13 @@ nds32_output_casesi_pc_relative (rtx *operands)
where m is 0, 1, or 2 to load address-diff value from table. */
switch (mode)
{
case QImode:
case E_QImode:
output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands);
break;
case HImode:
case E_HImode:
output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands);
break;
case SImode:
case E_SImode:
output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
break;
default:

6
gcc/config/nds32/nds32.h
View File

@ -897,13 +897,13 @@ enum reg_class
{ \
switch (GET_MODE (body)) \
{ \
case QImode: \
case E_QImode: \
asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
break; \
case HImode: \
case E_HImode: \
asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
break; \
case SImode: \
case E_SImode: \
asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
break; \
default: \

48
gcc/config/nvptx/nvptx.c
View File

@ -220,30 +220,30 @@ nvptx_ptx_type_from_mode (machine_mode mode, bool promote)
{
switch (mode)
{
case BLKmode:
case E_BLKmode:
return ".b8";
case BImode:
case E_BImode:
return ".pred";
case QImode:
case E_QImode:
if (promote)
return ".u32";
else
return ".u8";
case HImode:
case E_HImode:
return ".u16";
case SImode:
case E_SImode:
return ".u32";
case DImode:
case E_DImode:
return ".u64";
case SFmode:
case E_SFmode:
return ".f32";
case DFmode:
case E_DFmode:
return ".f64";
case V2SImode:
case E_V2SImode:
return ".v2.u32";
case V2DImode:
case E_V2DImode:
return ".v2.u64";
default:
@ -1638,10 +1638,10 @@ nvptx_gen_unpack (rtx dst0, rtx dst1, rtx src)
switch (GET_MODE (src))
{
case DImode:
case E_DImode:
res = gen_unpackdisi2 (dst0, dst1, src);
break;
case DFmode:
case E_DFmode:
res = gen_unpackdfsi2 (dst0, dst1, src);
break;
default: gcc_unreachable ();
@ -1659,10 +1659,10 @@ nvptx_gen_pack (rtx dst, rtx src0, rtx src1)
switch (GET_MODE (dst))
{
case DImode:
case E_DImode:
res = gen_packsidi2 (dst, src0, src1);
break;
case DFmode:
case E_DFmode:
res = gen_packsidf2 (dst, src0, src1);
break;
default: gcc_unreachable ();
@ -1680,14 +1680,14 @@ nvptx_gen_shuffle (rtx dst, rtx src, rtx idx, nvptx_shuffle_kind kind)
switch (GET_MODE (dst))
{
case SImode:
case E_SImode:
res = gen_nvptx_shufflesi (dst, src, idx, GEN_INT (kind));
break;
case SFmode:
case E_SFmode:
res = gen_nvptx_shufflesf (dst, src, idx, GEN_INT (kind));
break;
case DImode:
case DFmode:
case E_DImode:
case E_DFmode:
{
rtx tmp0 = gen_reg_rtx (SImode);
rtx tmp1 = gen_reg_rtx (SImode);
@ -1701,7 +1701,7 @@ nvptx_gen_shuffle (rtx dst, rtx src, rtx idx, nvptx_shuffle_kind kind)
end_sequence ();
}
break;
case BImode:
case E_BImode:
{
rtx tmp = gen_reg_rtx (SImode);
@ -1713,8 +1713,8 @@ nvptx_gen_shuffle (rtx dst, rtx src, rtx idx, nvptx_shuffle_kind kind)
end_sequence ();
}
break;
case QImode:
case HImode:
case E_QImode:
case E_HImode:
{
rtx tmp = gen_reg_rtx (SImode);
@ -1776,7 +1776,7 @@ nvptx_gen_wcast (rtx reg, propagate_mask pm, unsigned rep, wcast_data_t *data)
switch (mode)
{
case BImode:
case E_BImode:
{
rtx tmp = gen_reg_rtx (SImode);
@ -5490,9 +5490,9 @@ nvptx_preferred_simd_mode (machine_mode mode)
{
switch (mode)
{
case DImode:
case E_DImode:
return V2DImode;
case SImode:
case E_SImode:
return V2SImode;
default:

12
gcc/config/pa/pa.c
View File

@ -6067,19 +6067,19 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
{
switch (mode)
{
case SImode:
case E_SImode:
sri->icode = CODE_FOR_reload_insi_r1;
break;
case DImode:
case E_DImode:
sri->icode = CODE_FOR_reload_indi_r1;
break;
case SFmode:
case E_SFmode:
sri->icode = CODE_FOR_reload_insf_r1;
break;
case DFmode:
case E_DFmode:
sri->icode = CODE_FOR_reload_indf_r1;
break;
@ -6101,11 +6101,11 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
{
switch (mode)
{
case SImode:
case E_SImode:
sri->icode = CODE_FOR_reload_insi_r1;
break;
case DImode:
case E_DImode:
sri->icode = CODE_FOR_reload_indi_r1;
break;

6
gcc/config/pa/predicates.md
View File

@ -272,9 +272,9 @@
assumed in the instruction encoding. */
switch (mode)
{
case BLKmode:
case QImode:
case HImode:
case E_BLKmode:
case E_QImode:
case E_HImode:
return true;
default:

76
gcc/config/powerpcspe/powerpcspe-c.c
View File

@ -5687,23 +5687,23 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
switch (TYPE_MODE (TREE_TYPE (arg0_type)))
{
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
{
/* For scalar types just use a multiply expression. */
return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
fold_convert (TREE_TYPE (arg0), arg1));
}
case SFmode:
case E_SFmode:
{
/* For floats use the xvmulsp instruction directly. */
tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
return build_call_expr (call, 2, arg0, arg1);
}
case DFmode:
case E_DFmode:
{
/* For doubles use the xvmuldp instruction directly. */
tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
@ -5751,13 +5751,13 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
vec_cmpeq (va, vb)). */
/* Note: vec_nand also works but opt changes vec_nand's
to vec_nor's anyway. */
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case SFmode:
case DFmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
case E_SFmode:
case E_DFmode:
{
/* call = vec_cmpeq (va, vb)
result = vec_nor (call, call). */
@ -5815,7 +5815,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
/* For {un}signed ints,
vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
vec_and (carryv, 0x1)). */
case SImode:
case E_SImode:
{
vec<tree, va_gc> *params = make_tree_vector ();
vec_safe_push (params, arg0);
@ -5835,7 +5835,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
}
/* For {un}signed __int128s use the vaddeuqm instruction
directly. */
case TImode:
case E_TImode:
{
tree adde_bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
return altivec_resolve_overloaded_builtin (loc, adde_bii,
@ -5881,7 +5881,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
vec_or (vec_addc (va, vb),
vec_addc (vec_add (va, vb),
vec_and (carryv, 0x1))). */
case SImode:
case E_SImode:
{
/* Use save_expr to ensure that operands used more than once
that may have side effects (like calls) are only evaluated
@ -5917,7 +5917,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
params);
}
/* For {un}signed __int128s use the vaddecuq instruction. */
case TImode:
case E_TImode:
{
tree VADDECUQ_bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
return altivec_resolve_overloaded_builtin (loc, VADDECUQ_bii,
@ -5969,28 +5969,28 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
unsigned_p = TYPE_UNSIGNED (type);
switch (TYPE_MODE (type))
{
case TImode:
case E_TImode:
type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
size = 1;
break;
case DImode:
case E_DImode:
type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
size = 2;
break;
case SImode:
case E_SImode:
type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
size = 4;
break;
case HImode:
case E_HImode:
type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
size = 8;
break;
case QImode:
case E_QImode:
type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
size = 16;
break;
case SFmode: type = V4SF_type_node; size = 4; break;
case DFmode: type = V2DF_type_node; size = 2; break;
case E_SFmode: type = V4SF_type_node; size = 4; break;
case E_DFmode: type = V2DF_type_node; size = 2; break;
default:
goto bad;
}
@ -6062,33 +6062,33 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
default:
break;
case V1TImode:
case E_V1TImode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
break;
case V2DFmode:
case E_V2DFmode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
break;
case V2DImode:
case E_V2DImode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
break;
case V4SFmode:
case E_V4SFmode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
break;
case V4SImode:
case E_V4SImode:
if (TARGET_DIRECT_MOVE_64BIT)
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
break;
case V8HImode:
case E_V8HImode:
if (TARGET_DIRECT_MOVE_64BIT)
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
break;
case V16QImode:
case E_V16QImode:
if (TARGET_DIRECT_MOVE_64BIT)
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
break;
@ -6104,27 +6104,27 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
default:
break;
case V2DFmode:
case E_V2DFmode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
break;
case V2DImode:
case E_V2DImode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
break;
case V4SFmode:
case E_V4SFmode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
break;
case V4SImode:
case E_V4SImode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
break;
case V8HImode:
case E_V8HImode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
break;
case V16QImode:
case E_V16QImode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
break;
}

466
gcc/config/powerpcspe/powerpcspe.c
View File

File diff suppressed because it is too large Load Diff

46
gcc/config/powerpcspe/predicates.md
View File

@ -650,17 +650,17 @@
switch (mode)
{
case KFmode:
case IFmode:
case TFmode:
case DFmode:
case SFmode:
case E_KFmode:
case E_IFmode:
case E_TFmode:
case E_DFmode:
case E_SFmode:
return 0;
case DImode:
case E_DImode:
return (num_insns_constant (op, DImode) <= 2);
case SImode:
case E_SImode:
return 1;
default:
@ -1932,12 +1932,12 @@
switch (mode)
{
case QImode:
case HImode:
case SImode:
case E_QImode:
case E_HImode:
case E_SImode:
break;
case DImode:
case E_DImode:
if (!TARGET_POWERPC64)
return 0;
break;
@ -1992,20 +1992,20 @@
switch (mode)
{
case QImode:
case HImode:
case SImode:
case E_QImode:
case E_HImode:
case E_SImode:
break;
/* Do not fuse 64-bit DImode in 32-bit since it splits into two
separate instructions. */
case DImode:
case E_DImode:
if (!TARGET_POWERPC64)
return 0;
break;
/* ISA 2.08/power8 only had fusion of GPR loads. */
case SFmode:
case E_SFmode:
if (!TARGET_P9_FUSION)
return 0;
break;
@ -2013,7 +2013,7 @@
/* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit
DFmode in 32-bit if -msoft-float since it splits into two separate
instructions. */
case DFmode:
case E_DFmode:
if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION)
return 0;
break;
@ -2057,15 +2057,15 @@
switch (mode)
{
case QImode:
case HImode:
case SImode:
case SFmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_SFmode:
break;
/* Do not fuse 64-bit DImode in 32-bit since it splits into two
separate instructions. */
case DImode:
case E_DImode:
if (!TARGET_POWERPC64)
return 0;
break;
@ -2073,7 +2073,7 @@
/* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits
into two separate instructions. Do allow fusion if we have hardware
floating point. */
case DFmode:
case E_DFmode:
if (!TARGET_POWERPC64 && !TARGET_DF_FPR)
return 0;
break;

46
gcc/config/rs6000/predicates.md
View File

@ -622,17 +622,17 @@
switch (mode)
{
case KFmode:
case IFmode:
case TFmode:
case DFmode:
case SFmode:
case E_KFmode:
case E_IFmode:
case E_TFmode:
case E_DFmode:
case E_SFmode:
return 0;
case DImode:
case E_DImode:
return (num_insns_constant (op, DImode) <= 2);
case SImode:
case E_SImode:
return 1;
default:
@ -1834,12 +1834,12 @@
switch (mode)
{
case QImode:
case HImode:
case SImode:
case E_QImode:
case E_HImode:
case E_SImode:
break;
case DImode:
case E_DImode:
if (!TARGET_POWERPC64)
return 0;
break;
@ -1894,20 +1894,20 @@
switch (mode)
{
case QImode:
case HImode:
case SImode:
case E_QImode:
case E_HImode:
case E_SImode:
break;
/* Do not fuse 64-bit DImode in 32-bit since it splits into two
separate instructions. */
case DImode:
case E_DImode:
if (!TARGET_POWERPC64)
return 0;
break;
/* ISA 2.08/power8 only had fusion of GPR loads. */
case SFmode:
case E_SFmode:
if (!TARGET_P9_FUSION)
return 0;
break;
@ -1915,7 +1915,7 @@
/* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit
DFmode in 32-bit if -msoft-float since it splits into two separate
instructions. */
case DFmode:
case E_DFmode:
if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION)
return 0;
break;
@ -1959,15 +1959,15 @@
switch (mode)
{
case QImode:
case HImode:
case SImode:
case SFmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_SFmode:
break;
/* Do not fuse 64-bit DImode in 32-bit since it splits into two
separate instructions. */
case DImode:
case E_DImode:
if (!TARGET_POWERPC64)
return 0;
break;
@ -1975,7 +1975,7 @@
/* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits
into two separate instructions. Do allow fusion if we have hardware
floating point. */
case DFmode:
case E_DFmode:
if (!TARGET_POWERPC64 && !TARGET_DF_FPR)
return 0;
break;

76
gcc/config/rs6000/rs6000-c.c
View File

@ -5828,23 +5828,23 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
switch (TYPE_MODE (TREE_TYPE (arg0_type)))
{
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
{
/* For scalar types just use a multiply expression. */
return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
fold_convert (TREE_TYPE (arg0), arg1));
}
case SFmode:
case E_SFmode:
{
/* For floats use the xvmulsp instruction directly. */
tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
return build_call_expr (call, 2, arg0, arg1);
}
case DFmode:
case E_DFmode:
{
/* For doubles use the xvmuldp instruction directly. */
tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
@ -5892,13 +5892,13 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
vec_cmpeq (va, vb)). */
/* Note: vec_nand also works but opt changes vec_nand's
to vec_nor's anyway. */
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case SFmode:
case DFmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
case E_SFmode:
case E_DFmode:
{
/* call = vec_cmpeq (va, vb)
result = vec_nor (call, call). */
@ -5961,7 +5961,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
vec_and (carryv, 1)).
vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb),
vec_and (carryv, 1)). */
case SImode:
case E_SImode:
{
tree add_sub_builtin;
@ -5989,7 +5989,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
}
/* For {un}signed __int128s use the vaddeuqm instruction
directly. */
case TImode:
case E_TImode:
{
tree bii;
@ -6044,7 +6044,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
vec_or (vec_addc (va, vb),
vec_addc (vec_add (va, vb),
vec_and (carryv, 0x1))). */
case SImode:
case E_SImode:
{
/* Use save_expr to ensure that operands used more than once
that may have side effects (like calls) are only evaluated
@ -6095,7 +6095,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
}
/* For {un}signed __int128s use the vaddecuq/vsubbecuq
instructions. */
case TImode:
case E_TImode:
{
tree bii;
@ -6148,28 +6148,28 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
unsigned_p = TYPE_UNSIGNED (type);
switch (TYPE_MODE (type))
{
case TImode:
case E_TImode:
type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
size = 1;
break;
case DImode:
case E_DImode:
type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
size = 2;
break;
case SImode:
case E_SImode:
type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
size = 4;
break;
case HImode:
case E_HImode:
type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
size = 8;
break;
case QImode:
case E_QImode:
type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
size = 16;
break;
case SFmode: type = V4SF_type_node; size = 4; break;
case DFmode: type = V2DF_type_node; size = 2; break;
case E_SFmode: type = V4SF_type_node; size = 4; break;
case E_DFmode: type = V2DF_type_node; size = 2; break;
default:
goto bad;
}
@ -6241,33 +6241,33 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
default:
break;
case V1TImode:
case E_V1TImode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
break;
case V2DFmode:
case E_V2DFmode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
break;
case V2DImode:
case E_V2DImode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
break;
case V4SFmode:
case E_V4SFmode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
break;
case V4SImode:
case E_V4SImode:
if (TARGET_DIRECT_MOVE_64BIT)
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
break;
case V8HImode:
case E_V8HImode:
if (TARGET_DIRECT_MOVE_64BIT)
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
break;
case V16QImode:
case E_V16QImode:
if (TARGET_DIRECT_MOVE_64BIT)
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
break;
@ -6283,27 +6283,27 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
default:
break;
case V2DFmode:
case E_V2DFmode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
break;
case V2DImode:
case E_V2DImode:
call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
break;
case V4SFmode:
case E_V4SFmode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
break;
case V4SImode:
case E_V4SImode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
break;
case V8HImode:
case E_V8HImode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
break;
case V16QImode:
case E_V16QImode:
call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
break;
}

20
gcc/config/rs6000/rs6000-string.c
View File

@ -152,13 +152,13 @@ do_load_for_compare (rtx reg, rtx mem, machine_mode mode)
{
switch (GET_MODE (reg))
{
case DImode:
case E_DImode:
switch (mode)
{
case QImode:
case E_QImode:
emit_insn (gen_zero_extendqidi2 (reg, mem));
break;
case HImode:
case E_HImode:
{
rtx src = mem;
if (!BYTES_BIG_ENDIAN)
@ -169,7 +169,7 @@ do_load_for_compare (rtx reg, rtx mem, machine_mode mode)
emit_insn (gen_zero_extendhidi2 (reg, src));
break;
}
case SImode:
case E_SImode:
{
rtx src = mem;
if (!BYTES_BIG_ENDIAN)
@ -180,7 +180,7 @@ do_load_for_compare (rtx reg, rtx mem, machine_mode mode)
emit_insn (gen_zero_extendsidi2 (reg, src));
}
break;
case DImode:
case E_DImode:
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_bswapdi2 (reg, mem));
else
@ -191,13 +191,13 @@ do_load_for_compare (rtx reg, rtx mem, machine_mode mode)
}
break;
case SImode:
case E_SImode:
switch (mode)
{
case QImode:
case E_QImode:
emit_insn (gen_zero_extendqisi2 (reg, mem));
break;
case HImode:
case E_HImode:
{
rtx src = mem;
if (!BYTES_BIG_ENDIAN)
@ -208,13 +208,13 @@ do_load_for_compare (rtx reg, rtx mem, machine_mode mode)
emit_insn (gen_zero_extendhisi2 (reg, src));
break;
}
case SImode:
case E_SImode:
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_bswapsi2 (reg, mem));
else
emit_insn (gen_movsi (reg, mem));
break;
case DImode:
case E_DImode:
/* DImode is larger than the destination reg so is not expected. */
gcc_unreachable ();
break;

374
gcc/config/rs6000/rs6000.c
View File

@ -2904,13 +2904,13 @@ rs6000_setup_reg_addr_masks (void)
addr_mask |= RELOAD_REG_PRE_MODIFY;
break;
case DImode:
case E_DImode:
if (TARGET_POWERPC64)
addr_mask |= RELOAD_REG_PRE_MODIFY;
break;
case DFmode:
case DDmode:
case E_DFmode:
case E_DDmode:
if (TARGET_DF_INSN)
addr_mask |= RELOAD_REG_PRE_MODIFY;
break;
@ -5533,24 +5533,24 @@ rs6000_preferred_simd_mode (machine_mode mode)
if (TARGET_VSX)
switch (mode)
{
case DFmode:
case E_DFmode:
return V2DFmode;
default:;
}
if (TARGET_ALTIVEC || TARGET_VSX)
switch (mode)
{
case SFmode:
case E_SFmode:
return V4SFmode;
case TImode:
case E_TImode:
return V1TImode;
case DImode:
case E_DImode:
return V2DImode;
case SImode:
case E_SImode:
return V4SImode;
case HImode:
case E_HImode:
return V8HImode;
case QImode:
case E_QImode:
return V16QImode;
default:;
}
@ -6734,13 +6734,13 @@ output_vec_const_move (rtx *operands)
switch (GET_MODE (splat_vec))
{
case V4SImode:
case E_V4SImode:
return "vspltisw %0,%1";
case V8HImode:
case E_V8HImode:
return "vspltish %0,%1";
case V16QImode:
case E_V16QImode:
return "vspltisb %0,%1";
default:
@ -7293,20 +7293,20 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
{
default:
break;
case V1TImode:
case E_V1TImode:
gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
emit_move_insn (target, gen_lowpart (TImode, vec));
break;
case V2DFmode:
case E_V2DFmode:
emit_insn (gen_vsx_extract_v2df (target, vec, elt));
return;
case V2DImode:
case E_V2DImode:
emit_insn (gen_vsx_extract_v2di (target, vec, elt));
return;
case V4SFmode:
case E_V4SFmode:
emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
return;
case V16QImode:
case E_V16QImode:
if (TARGET_DIRECT_MOVE_64BIT)
{
emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
@ -7314,7 +7314,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
}
else
break;
case V8HImode:
case E_V8HImode:
if (TARGET_DIRECT_MOVE_64BIT)
{
emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
@ -7322,7 +7322,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
}
else
break;
case V4SImode:
case E_V4SImode:
if (TARGET_DIRECT_MOVE_64BIT)
{
emit_insn (gen_vsx_extract_v4si (target, vec, elt));
@ -7345,27 +7345,27 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
switch (mode)
{
case V2DFmode:
case E_V2DFmode:
emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
return;
case V2DImode:
case E_V2DImode:
emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
return;
case V4SFmode:
case E_V4SFmode:
emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
return;
case V4SImode:
case E_V4SImode:
emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
return;
case V8HImode:
case E_V8HImode:
emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
return;
case V16QImode:
case E_V16QImode:
emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
return;
@ -7689,15 +7689,15 @@ rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
/* Do the VSLO to get the value into the final location. */
switch (mode)
{
case V2DFmode:
case E_V2DFmode:
emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
return;
case V2DImode:
case E_V2DImode:
emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
return;
case V4SFmode:
case E_V4SFmode:
{
rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
@ -7709,9 +7709,9 @@ rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
return;
}
case V4SImode:
case V8HImode:
case V16QImode:
case E_V4SImode:
case E_V8HImode:
case E_V16QImode:
{
rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
@ -8216,16 +8216,16 @@ reg_offset_addressing_ok_p (machine_mode mode)
{
switch (mode)
{
case V16QImode:
case V8HImode:
case V4SFmode:
case V4SImode:
case V2DFmode:
case V2DImode:
case V1TImode:
case TImode:
case TFmode:
case KFmode:
case E_V16QImode:
case E_V8HImode:
case E_V4SFmode:
case E_V4SImode:
case E_V2DFmode:
case E_V2DImode:
case E_V1TImode:
case E_TImode:
case E_TFmode:
case E_KFmode:
/* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
ISA 3.0 vector d-form addressing mode was added. While TImode is not
a vector mode, if we want to use the VSX registers to move it around,
@ -8236,14 +8236,14 @@ reg_offset_addressing_ok_p (machine_mode mode)
return mode_supports_vsx_dform_quad (mode);
break;
case V2SImode:
case V2SFmode:
case E_V2SImode:
case E_V2SFmode:
/* Paired vector modes. Only reg+reg addressing is valid. */
if (TARGET_PAIRED_FLOAT)
return false;
break;
case SDmode:
case E_SDmode:
/* If we can do direct load/stores of SDmode, restrict it to reg+reg
addressing for the LFIWZX and STFIWX instructions. */
if (TARGET_NO_SDMODE_STACK)
@ -8484,14 +8484,14 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
extra = 0;
switch (mode)
{
case V2SImode:
case V2SFmode:
case E_V2SImode:
case E_V2SFmode:
/* Paired single modes: offset addressing isn't valid. */
return false;
case DFmode:
case DDmode:
case DImode:
case E_DFmode:
case E_DDmode:
case E_DImode:
/* If we are using VSX scalar loads, restrict ourselves to reg+reg
addressing. */
if (VECTOR_MEM_VSX_P (mode))
@ -8505,12 +8505,12 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
return false;
break;
case TFmode:
case IFmode:
case KFmode:
case TDmode:
case TImode:
case PTImode:
case E_TFmode:
case E_IFmode:
case E_KFmode:
case E_TDmode:
case E_TImode:
case E_PTImode:
extra = 8;
if (!worst_case)
break;
@ -8685,12 +8685,12 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
extra = 0;
switch (mode)
{
case TFmode:
case TDmode:
case TImode:
case PTImode:
case IFmode:
case KFmode:
case E_TFmode:
case E_TDmode:
case E_TImode:
case E_PTImode:
case E_IFmode:
case E_KFmode:
/* As in legitimate_offset_address_p we do not assume
worst-case. The mode here is just a hint as to the registers
used. A TImode is usually in gprs, but may actually be in
@ -10040,12 +10040,12 @@ rs6000_emit_set_const (rtx dest, rtx source)
c = INTVAL (source);
switch (mode)
{
case QImode:
case HImode:
case E_QImode:
case E_HImode:
emit_insn (gen_rtx_SET (dest, source));
return true;
case SImode:
case E_SImode:
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
emit_insn (gen_rtx_SET (copy_rtx (temp),
@ -10055,7 +10055,7 @@ rs6000_emit_set_const (rtx dest, rtx source)
GEN_INT (c & 0xffff))));
break;
case DImode:
case E_DImode:
if (!TARGET_POWERPC64)
{
rtx hi, lo;
@ -10211,21 +10211,21 @@ rs6000_const_vec (machine_mode mode)
switch (mode)
{
case V1TImode:
case E_V1TImode:
subparts = 1;
break;
case V2DFmode:
case V2DImode:
case E_V2DFmode:
case E_V2DImode:
subparts = 2;
break;
case V4SFmode:
case V4SImode:
case E_V4SFmode:
case E_V4SImode:
subparts = 4;
break;
case V8HImode:
case E_V8HImode:
subparts = 8;
break;
case V16QImode:
case E_V16QImode:
subparts = 16;
break;
default:
@ -10632,46 +10632,46 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
mode == Pmode. */
switch (mode)
{
case HImode:
case QImode:
case E_HImode:
case E_QImode:
if (CONSTANT_P (operands[1])
&& GET_CODE (operands[1]) != CONST_INT)
operands[1] = force_const_mem (mode, operands[1]);
break;
case TFmode:
case TDmode:
case IFmode:
case KFmode:
case E_TFmode:
case E_TDmode:
case E_IFmode:
case E_KFmode:
if (FLOAT128_2REG_P (mode))
rs6000_eliminate_indexed_memrefs (operands);
/* fall through */
case DFmode:
case DDmode:
case SFmode:
case SDmode:
case E_DFmode:
case E_DDmode:
case E_SFmode:
case E_SDmode:
if (CONSTANT_P (operands[1])
&& ! easy_fp_constant (operands[1], mode))
operands[1] = force_const_mem (mode, operands[1]);
break;
case V16QImode:
case V8HImode:
case V4SFmode:
case V4SImode:
case V2SFmode:
case V2SImode:
case V2DFmode:
case V2DImode:
case V1TImode:
case E_V16QImode:
case E_V8HImode:
case E_V4SFmode:
case E_V4SImode:
case E_V2SFmode:
case E_V2SImode:
case E_V2DFmode:
case E_V2DImode:
case E_V1TImode:
if (CONSTANT_P (operands[1])
&& !easy_vector_constant (operands[1], mode))
operands[1] = force_const_mem (mode, operands[1]);
break;
case SImode:
case DImode:
case E_SImode:
case E_DImode:
/* Use default pattern for address of ELF small data */
if (TARGET_ELF
&& mode == Pmode
@ -10817,12 +10817,12 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
}
break;
case TImode:
case E_TImode:
if (!VECTOR_MEM_VSX_P (TImode))
rs6000_eliminate_indexed_memrefs (operands);
break;
case PTImode:
case E_PTImode:
rs6000_eliminate_indexed_memrefs (operands);
break;
@ -12047,9 +12047,9 @@ rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
#if 0
switch (mode)
{
case SCmode: mode = SFmode; break;
case DCmode: mode = DFmode; break;
case TCmode: mode = TFmode; break;
case E_SCmode: mode = SFmode; break;
case E_DCmode: mode = DFmode; break;
case E_TCmode: mode = TFmode; break;
default: break;
}
#endif
@ -14230,18 +14230,18 @@ swap_selector_for_mode (machine_mode mode)
switch (mode)
{
case V2DFmode:
case V2DImode:
case E_V2DFmode:
case E_V2DImode:
swaparray = swap2;
break;
case V4SFmode:
case V4SImode:
case E_V4SFmode:
case E_V4SImode:
swaparray = swap4;
break;
case V8HImode:
case E_V8HImode:
swaparray = swap8;
break;
case V16QImode:
case E_V16QImode:
swaparray = swap16;
break;
default:
@ -17078,7 +17078,7 @@ paired_init_builtins (void)
switch (insn_data[d->icode].operand[1].mode)
{
case V2SFmode:
case E_V2SFmode:
type = int_ftype_int_v2sf_v2sf;
break;
default:
@ -17509,25 +17509,25 @@ altivec_init_builtins (void)
switch (mode1)
{
case VOIDmode:
case E_VOIDmode:
type = int_ftype_int_opaque_opaque;
break;
case V2DImode:
case E_V2DImode:
type = int_ftype_int_v2di_v2di;
break;
case V4SImode:
case E_V4SImode:
type = int_ftype_int_v4si_v4si;
break;
case V8HImode:
case E_V8HImode:
type = int_ftype_int_v8hi_v8hi;
break;
case V16QImode:
case E_V16QImode:
type = int_ftype_int_v16qi_v16qi;
break;
case V4SFmode:
case E_V4SFmode:
type = int_ftype_int_v4sf_v4sf;
break;
case V2DFmode:
case E_V2DFmode:
type = int_ftype_int_v2df_v2df;
break;
default:
@ -17559,22 +17559,22 @@ altivec_init_builtins (void)
switch (mode0)
{
case V2DImode:
case E_V2DImode:
type = v2di_ftype_v2di;
break;
case V4SImode:
case E_V4SImode:
type = v4si_ftype_v4si;
break;
case V8HImode:
case E_V8HImode:
type = v8hi_ftype_v8hi;
break;
case V16QImode:
case E_V16QImode:
type = v16qi_ftype_v16qi;
break;
case V4SFmode:
case E_V4SFmode:
type = v4sf_ftype_v4sf;
break;
case V2DFmode:
case E_V2DFmode:
type = v2df_ftype_v2df;
break;
default:
@ -22156,26 +22156,26 @@ rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
switch (src_mode)
{
case DFmode:
case E_DFmode:
cvt = sext_optab;
hw_convert = hw_conversions[kf_or_tf].from_df;
break;
case SFmode:
case E_SFmode:
cvt = sext_optab;
hw_convert = hw_conversions[kf_or_tf].from_sf;
break;
case KFmode:
case IFmode:
case TFmode:
case E_KFmode:
case E_IFmode:
case E_TFmode:
if (FLOAT128_IBM_P (src_mode))
cvt = sext_optab;
else
do_move = true;
break;
case SImode:
case E_SImode:
if (unsigned_p)
{
cvt = ufloat_optab;
@ -22188,7 +22188,7 @@ rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
}
break;
case DImode:
case E_DImode:
if (unsigned_p)
{
cvt = ufloat_optab;
@ -22218,26 +22218,26 @@ rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
switch (dest_mode)
{
case DFmode:
case E_DFmode:
cvt = trunc_optab;
hw_convert = hw_conversions[kf_or_tf].to_df;
break;
case SFmode:
case E_SFmode:
cvt = trunc_optab;
hw_convert = hw_conversions[kf_or_tf].to_sf;
break;
case KFmode:
case IFmode:
case TFmode:
case E_KFmode:
case E_IFmode:
case E_TFmode:
if (FLOAT128_IBM_P (dest_mode))
cvt = trunc_optab;
else
do_move = true;
break;
case SImode:
case E_SImode:
if (unsigned_p)
{
cvt = ufix_optab;
@ -22250,7 +22250,7 @@ rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
}
break;
case DImode:
case E_DImode:
if (unsigned_p)
{
cvt = ufix_optab;
@ -23250,13 +23250,13 @@ emit_load_locked (machine_mode mode, rtx reg, rtx mem)
switch (mode)
{
case QImode:
case E_QImode:
fn = gen_load_lockedqi;
break;
case HImode:
case E_HImode:
fn = gen_load_lockedhi;
break;
case SImode:
case E_SImode:
if (GET_MODE (mem) == QImode)
fn = gen_load_lockedqi_si;
else if (GET_MODE (mem) == HImode)
@ -23264,10 +23264,10 @@ emit_load_locked (machine_mode mode, rtx reg, rtx mem)
else
fn = gen_load_lockedsi;
break;
case DImode:
case E_DImode:
fn = gen_load_lockeddi;
break;
case TImode:
case E_TImode:
fn = gen_load_lockedti;
break;
default:
@ -23286,19 +23286,19 @@ emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
switch (mode)
{
case QImode:
case E_QImode:
fn = gen_store_conditionalqi;
break;
case HImode:
case E_HImode:
fn = gen_store_conditionalhi;
break;
case SImode:
case E_SImode:
fn = gen_store_conditionalsi;
break;
case DImode:
case E_DImode:
fn = gen_store_conditionaldi;
break;
case TImode:
case E_TImode:
fn = gen_store_conditionalti;
break;
default:
@ -28839,17 +28839,17 @@ rs6000_output_function_epilogue (FILE *file)
switch (mode)
{
case SFmode:
case SDmode:
case E_SFmode:
case E_SDmode:
bits = 0x2;
break;
case DFmode:
case DDmode:
case TFmode:
case TDmode:
case IFmode:
case KFmode:
case E_DFmode:
case E_DDmode:
case E_TFmode:
case E_TDmode:
case E_IFmode:
case E_KFmode:
bits = 0x3;
break;
@ -32395,28 +32395,28 @@ rs6000_handle_altivec_attribute (tree *node,
unsigned_p = TYPE_UNSIGNED (type);
switch (mode)
{
case TImode:
case E_TImode:
result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
break;
case DImode:
case E_DImode:
result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
break;
case SImode:
case E_SImode:
result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
break;
case HImode:
case E_HImode:
result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
break;
case QImode:
case E_QImode:
result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
break;
case SFmode: result = V4SF_type_node; break;
case DFmode: result = V2DF_type_node; break;
case E_SFmode: result = V4SF_type_node; break;
case E_DFmode: result = V2DF_type_node; break;
/* If the user says 'vector int bool', we may be handed the 'bool'
attribute _before_ the 'vector' attribute, and so select the
proper type in the 'b' case below. */
case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
case V2DImode: case V2DFmode:
case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
case E_V2DImode: case E_V2DFmode:
result = type;
default: break;
}
@ -32424,17 +32424,17 @@ rs6000_handle_altivec_attribute (tree *node,
case 'b':
switch (mode)
{
case DImode: case V2DImode: result = bool_V2DI_type_node; break;
case SImode: case V4SImode: result = bool_V4SI_type_node; break;
case HImode: case V8HImode: result = bool_V8HI_type_node; break;
case QImode: case V16QImode: result = bool_V16QI_type_node;
case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
default: break;
}
break;
case 'p':
switch (mode)
{
case V8HImode: result = pixel_V8HI_type_node;
case E_V8HImode: result = pixel_V8HI_type_node;
default: break;
}
default: break;
@ -35691,10 +35691,10 @@ rs6000_function_value (const_tree valtype,
{
default:
break;
case DImode:
case SCmode:
case DCmode:
case TCmode:
case E_DImode:
case E_SCmode:
case E_DCmode:
case E_TCmode:
int count = GET_MODE_SIZE (mode) / 4;
return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
}
@ -38367,24 +38367,24 @@ emit_fusion_gpr_load (rtx target, rtx mem)
mode = GET_MODE (mem);
switch (mode)
{
case QImode:
case E_QImode:
mode_name = "char";
load_str = "lbz";
break;
case HImode:
case E_HImode:
mode_name = "short";
load_str = "lhz";
break;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
mode_name = (mode == SFmode) ? "float" : "int";
load_str = "lwz";
break;
case DImode:
case DFmode:
case E_DImode:
case E_DFmode:
gcc_assert (TARGET_POWERPC64);
mode_name = (mode == DFmode) ? "double" : "long";
load_str = "ld";
@ -38634,18 +38634,18 @@ emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
{
switch (mode)
{
case QImode:
case E_QImode:
load_string = "lbz";
break;
case HImode:
case E_HImode:
load_string = "lhz";
break;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
load_string = "lwz";
break;
case DImode:
case DFmode:
case E_DImode:
case E_DFmode:
if (!TARGET_POWERPC64)
gcc_unreachable ();
load_string = "ld";
@ -38721,18 +38721,18 @@ emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
{
switch (mode)
{
case QImode:
case E_QImode:
store_string = "stb";
break;
case HImode:
case E_HImode:
store_string = "sth";
break;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
store_string = "stw";
break;
case DImode:
case DFmode:
case E_DImode:
case E_DFmode:
if (!TARGET_POWERPC64)
gcc_unreachable ();
store_string = "std";

24
gcc/config/rx/rx.c
View File

@ -966,25 +966,25 @@ rx_gen_move_template (rtx * operands, bool is_movu)
/* Decide which extension, if any, should be given to the move instruction. */
switch (CONST_INT_P (src) ? GET_MODE (dest) : GET_MODE (src))
{
case QImode:
case E_QImode:
/* The .B extension is not valid when
loading an immediate into a register. */
if (! REG_P (dest) || ! CONST_INT_P (src))
extension = ".B";
break;
case HImode:
case E_HImode:
if (! REG_P (dest) || ! CONST_INT_P (src))
/* The .W extension is not valid when
loading an immediate into a register. */
extension = ".W";
break;
case DFmode:
case DImode:
case SFmode:
case SImode:
case E_DFmode:
case E_DImode:
case E_SFmode:
case E_SImode:
extension = ".L";
break;
case VOIDmode:
case E_VOIDmode:
/* This mode is used by constants. */
break;
default:
@ -3079,15 +3079,15 @@ flags_from_mode (machine_mode mode)
{
switch (mode)
{
case CC_ZSmode:
case E_CC_ZSmode:
return CC_FLAG_S | CC_FLAG_Z;
case CC_ZSOmode:
case E_CC_ZSOmode:
return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
case CC_ZSCmode:
case E_CC_ZSCmode:
return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C;
case CCmode:
case E_CCmode:
return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C;
case CC_Fmode:
case E_CC_Fmode:
return CC_FLAG_FP;
default:
gcc_unreachable ();

28
gcc/config/s390/predicates.md
View File

@ -278,25 +278,25 @@
switch (GET_MODE (XEXP (op, 0)))
{
case CCL1mode:
case E_CCL1mode:
return GET_CODE (op) == LTU;
case CCL2mode:
case E_CCL2mode:
return GET_CODE (op) == LEU;
case CCL3mode:
case E_CCL3mode:
return GET_CODE (op) == GEU;
case CCUmode:
case E_CCUmode:
return GET_CODE (op) == GTU;
case CCURmode:
case E_CCURmode:
return GET_CODE (op) == LTU;
case CCSmode:
case E_CCSmode:
return GET_CODE (op) == UNGT;
case CCSRmode:
case E_CCSRmode:
return GET_CODE (op) == UNLT;
default:
@ -323,25 +323,25 @@
switch (GET_MODE (XEXP (op, 0)))
{
case CCL1mode:
case E_CCL1mode:
return GET_CODE (op) == GEU;
case CCL2mode:
case E_CCL2mode:
return GET_CODE (op) == GTU;
case CCL3mode:
case E_CCL3mode:
return GET_CODE (op) == LTU;
case CCUmode:
case E_CCUmode:
return GET_CODE (op) == LEU;
case CCURmode:
case E_CCURmode:
return GET_CODE (op) == GEU;
case CCSmode:
case E_CCSmode:
return GET_CODE (op) == LE;
case CCSRmode:
case E_CCSRmode:
return GET_CODE (op) == GE;
default:

179
gcc/config/s390/s390.c
View File

@ -1134,11 +1134,20 @@ s390_handle_vectorbool_attribute (tree *node, tree name ATTRIBUTE_UNUSED,
mode = TYPE_MODE (type);
switch (mode)
{
case DImode: case V2DImode: result = s390_builtin_types[BT_BV2DI]; break;
case SImode: case V4SImode: result = s390_builtin_types[BT_BV4SI]; break;
case HImode: case V8HImode: result = s390_builtin_types[BT_BV8HI]; break;
case QImode: case V16QImode: result = s390_builtin_types[BT_BV16QI];
default: break;
case E_DImode: case E_V2DImode:
result = s390_builtin_types[BT_BV2DI];
break;
case E_SImode: case E_V4SImode:
result = s390_builtin_types[BT_BV4SI];
break;
case E_HImode: case E_V8HImode:
result = s390_builtin_types[BT_BV8HI];
break;
case E_QImode: case E_V16QImode:
result = s390_builtin_types[BT_BV16QI];
break;
default:
break;
}
*no_add_attrs = true; /* No need to hang on to the attribute. */
@ -1248,14 +1257,14 @@ s390_vector_mode_supported_p (machine_mode mode)
switch (inner)
{
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case SFmode:
case DFmode:
case TFmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
case E_SFmode:
case E_DFmode:
case E_TFmode:
return true;
default:
return false;
@ -1282,18 +1291,18 @@ s390_cc_modes_compatible (machine_mode m1, machine_mode m2)
switch (m1)
{
case CCZmode:
case E_CCZmode:
if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
|| m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
return m2;
return VOIDmode;
case CCSmode:
case CCUmode:
case CCTmode:
case CCSRmode:
case CCURmode:
case CCZ1mode:
case E_CCSmode:
case E_CCUmode:
case E_CCTmode:
case E_CCSRmode:
case E_CCURmode:
case E_CCZ1mode:
if (m2 == CCZmode)
return m1;
@ -1327,36 +1336,36 @@ s390_match_ccmode_set (rtx set, machine_mode req_mode)
set_mode = GET_MODE (SET_DEST (set));
switch (set_mode)
{
case CCZ1mode:
case CCSmode:
case CCSRmode:
case CCUmode:
case CCURmode:
case CCLmode:
case CCL1mode:
case CCL2mode:
case CCL3mode:
case CCT1mode:
case CCT2mode:
case CCT3mode:
case CCVEQmode:
case CCVIHmode:
case CCVIHUmode:
case CCVFHmode:
case CCVFHEmode:
case E_CCZ1mode:
case E_CCSmode:
case E_CCSRmode:
case E_CCUmode:
case E_CCURmode:
case E_CCLmode:
case E_CCL1mode:
case E_CCL2mode:
case E_CCL3mode:
case E_CCT1mode:
case E_CCT2mode:
case E_CCT3mode:
case E_CCVEQmode:
case E_CCVIHmode:
case E_CCVIHUmode:
case E_CCVFHmode:
case E_CCVFHEmode:
if (req_mode != set_mode)
return 0;
break;
case CCZmode:
case E_CCZmode:
if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
&& req_mode != CCSRmode && req_mode != CCURmode
&& req_mode != CCZ1mode)
return 0;
break;
case CCAPmode:
case CCANmode:
case E_CCAPmode:
case E_CCANmode:
if (req_mode != CCAmode)
return 0;
break;
@ -1675,8 +1684,8 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
enum rtx_code new_code = UNKNOWN;
switch (GET_MODE (XVECEXP (*op0, 0, 0)))
{
case CCZmode:
case CCRAWmode:
case E_CCZmode:
case E_CCRAWmode:
switch (*code)
{
case EQ: new_code = EQ; break;
@ -1792,20 +1801,20 @@ s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
cc = gen_rtx_REG (ccmode, CC_REGNUM);
switch (GET_MODE (mem))
{
case SImode:
case E_SImode:
emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp,
new_rtx, cc));
break;
case DImode:
case E_DImode:
emit_insn (gen_atomic_compare_and_swapdi_internal (old, mem, cmp,
new_rtx, cc));
break;
case TImode:
case E_TImode:
emit_insn (gen_atomic_compare_and_swapti_internal (old, mem, cmp,
new_rtx, cc));
break;
case QImode:
case HImode:
case E_QImode:
case E_HImode:
default:
gcc_unreachable ();
}
@ -1849,8 +1858,8 @@ s390_branch_condition_mask (rtx code)
switch (GET_MODE (XEXP (code, 0)))
{
case CCZmode:
case CCZ1mode:
case E_CCZmode:
case E_CCZ1mode:
switch (GET_CODE (code))
{
case EQ: return CC0;
@ -1859,7 +1868,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCT1mode:
case E_CCT1mode:
switch (GET_CODE (code))
{
case EQ: return CC1;
@ -1868,7 +1877,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCT2mode:
case E_CCT2mode:
switch (GET_CODE (code))
{
case EQ: return CC2;
@ -1877,7 +1886,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCT3mode:
case E_CCT3mode:
switch (GET_CODE (code))
{
case EQ: return CC3;
@ -1886,7 +1895,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCLmode:
case E_CCLmode:
switch (GET_CODE (code))
{
case EQ: return CC0 | CC2;
@ -1895,7 +1904,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCL1mode:
case E_CCL1mode:
switch (GET_CODE (code))
{
case LTU: return CC2 | CC3; /* carry */
@ -1904,7 +1913,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCL2mode:
case E_CCL2mode:
switch (GET_CODE (code))
{
case GTU: return CC0 | CC1; /* borrow */
@ -1913,7 +1922,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCL3mode:
case E_CCL3mode:
switch (GET_CODE (code))
{
case EQ: return CC0 | CC2;
@ -1925,7 +1934,7 @@ s390_branch_condition_mask (rtx code)
default: return -1;
}
case CCUmode:
case E_CCUmode:
switch (GET_CODE (code))
{
case EQ: return CC0;
@ -1938,7 +1947,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCURmode:
case E_CCURmode:
switch (GET_CODE (code))
{
case EQ: return CC0;
@ -1951,7 +1960,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCAPmode:
case E_CCAPmode:
switch (GET_CODE (code))
{
case EQ: return CC0;
@ -1964,7 +1973,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCANmode:
case E_CCANmode:
switch (GET_CODE (code))
{
case EQ: return CC0;
@ -1977,7 +1986,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCSmode:
case E_CCSmode:
switch (GET_CODE (code))
{
case EQ: return CC0;
@ -1998,7 +2007,7 @@ s390_branch_condition_mask (rtx code)
}
break;
case CCSRmode:
case E_CCSRmode:
switch (GET_CODE (code))
{
case EQ: return CC0;
@ -2022,7 +2031,7 @@ s390_branch_condition_mask (rtx code)
/* Vector comparison modes. */
/* CC2 will never be set. It however is part of the negated
masks. */
case CCVIALLmode:
case E_CCVIALLmode:
switch (GET_CODE (code))
{
case EQ:
@ -2037,7 +2046,7 @@ s390_branch_condition_mask (rtx code)
default: return -1;
}
case CCVIANYmode:
case E_CCVIANYmode:
switch (GET_CODE (code))
{
case EQ:
@ -2051,7 +2060,7 @@ s390_branch_condition_mask (rtx code)
case LT: return CC3 | CC2;
default: return -1;
}
case CCVFALLmode:
case E_CCVFALLmode:
switch (GET_CODE (code))
{
case EQ:
@ -2064,7 +2073,7 @@ s390_branch_condition_mask (rtx code)
default: return -1;
}
case CCVFANYmode:
case E_CCVFANYmode:
switch (GET_CODE (code))
{
case EQ:
@ -2077,7 +2086,7 @@ s390_branch_condition_mask (rtx code)
default: return -1;
}
case CCRAWmode:
case E_CCRAWmode:
switch (GET_CODE (code))
{
case EQ:
@ -3510,7 +3519,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
case MULT:
switch (mode)
{
case SImode:
case E_SImode:
{
rtx left = XEXP (x, 0);
rtx right = XEXP (x, 1);
@ -3523,7 +3532,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
*total = s390_cost->ms; /* msr, ms, msy */
break;
}
case DImode:
case E_DImode:
{
rtx left = XEXP (x, 0);
rtx right = XEXP (x, 1);
@ -3554,11 +3563,11 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
}
break;
}
case SFmode:
case DFmode:
case E_SFmode:
case E_DFmode:
*total = s390_cost->mult_df;
break;
case TFmode:
case E_TFmode:
*total = s390_cost->mxbr;
break;
default:
@ -3569,10 +3578,10 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
case FMA:
switch (mode)
{
case DFmode:
case E_DFmode:
*total = s390_cost->madbr;
break;
case SFmode:
case E_SFmode:
*total = s390_cost->maebr;
break;
default:
@ -4292,7 +4301,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
GET_MODE_SIZE (mode))))
{
#define __SECONDARY_RELOAD_CASE(M,m) \
case M##mode: \
case E_##M##mode: \
if (TARGET_64BIT) \
sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
CODE_FOR_reload##m##di_tomem_z10; \
@ -7006,13 +7015,13 @@ s390_expand_cs (machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
{
switch (mode)
{
case TImode:
case DImode:
case SImode:
case E_TImode:
case E_DImode:
case E_SImode:
s390_expand_cs_tdsi (mode, btarget, vtarget, mem, cmp, new_rtx, is_weak);
break;
case HImode:
case QImode:
case E_HImode:
case E_QImode:
s390_expand_cs_hqi (mode, btarget, vtarget, mem, cmp, new_rtx, is_weak);
break;
default:
@ -15490,15 +15499,15 @@ s390_preferred_simd_mode (machine_mode mode)
if (TARGET_VX)
switch (mode)
{
case DFmode:
case E_DFmode:
return V2DFmode;
case DImode:
case E_DImode:
return V2DImode;
case SImode:
case E_SImode:
return V4SImode;
case HImode:
case E_HImode:
return V8HImode;
case QImode:
case E_QImode:
return V16QImode;
default:;
}

6
gcc/config/s390/vx-builtins.md
View File

@ -314,9 +314,9 @@
machine_mode half_mode;
switch (<MODE>mode)
{
case V8HImode: half_mode = V16QImode; break;
case V4SImode: half_mode = V8HImode; break;
case V2DImode: half_mode = V4SImode; break;
case E_V8HImode: half_mode = V16QImode; break;
case E_V4SImode: half_mode = V8HImode; break;
case E_V2DImode: half_mode = V4SImode; break;
default: gcc_unreachable ();
}
s390_expand_vcond (operands[1], operands[1], null_vec,

36
gcc/config/sh/sh.c
View File

@ -1272,11 +1272,11 @@ sh_print_operand (FILE *stream, rtx x, int code)
{
switch (GET_MODE (x))
{
case QImode: fputs (".b", stream); break;
case HImode: fputs (".w", stream); break;
case SImode: fputs (".l", stream); break;
case SFmode: fputs (".s", stream); break;
case DFmode: fputs (".d", stream); break;
case E_QImode: fputs (".b", stream); break;
case E_HImode: fputs (".w", stream); break;
case E_SImode: fputs (".l", stream); break;
case E_SFmode: fputs (".s", stream); break;
case E_DFmode: fputs (".d", stream); break;
default: gcc_unreachable ();
}
}
@ -4622,10 +4622,10 @@ dump_table (rtx_insn *start, rtx_insn *barrier)
switch (p->mode)
{
case HImode:
case E_HImode:
break;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
if (align_insn && !p->part_of_sequence_p)
{
for (lab = p->label; lab; lab = LABEL_REFS (lab))
@ -4651,7 +4651,7 @@ dump_table (rtx_insn *start, rtx_insn *barrier)
need_align = ! need_align;
}
break;
case DFmode:
case E_DFmode:
if (need_align)
{
scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
@ -4659,7 +4659,7 @@ dump_table (rtx_insn *start, rtx_insn *barrier)
need_align = false;
}
/* FALLTHRU */
case DImode:
case E_DImode:
for (lab = p->label; lab; lab = LABEL_REFS (lab))
scan = emit_label_after (lab, scan);
scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
@ -4689,10 +4689,10 @@ dump_table (rtx_insn *start, rtx_insn *barrier)
switch (p->mode)
{
case HImode:
case E_HImode:
break;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
if (need_align)
{
need_align = false;
@ -4704,8 +4704,8 @@ dump_table (rtx_insn *start, rtx_insn *barrier)
scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
scan);
break;
case DFmode:
case DImode:
case E_DFmode:
case E_DImode:
if (need_align)
{
need_align = false;
@ -11239,13 +11239,13 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
&& ! ((fp_zero_operand (x) || fp_one_operand (x)) && mode == SFmode))
switch (mode)
{
case SFmode:
case E_SFmode:
sri->icode = CODE_FOR_reload_insf__frn;
return NO_REGS;
case DFmode:
case E_DFmode:
sri->icode = CODE_FOR_reload_indf__frn;
return NO_REGS;
case SImode:
case E_SImode:
/* ??? If we knew that we are in the appropriate mode -
single precision - we could use a reload pattern directly. */
return FPUL_REGS;

6
gcc/config/sh/sh.h
View File

@ -1793,13 +1793,13 @@ extern bool current_function_interrupt;
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
switch (GET_MODE (BODY)) \
{ \
case SImode: \
case E_SImode: \
asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
case HImode: \
case E_HImode: \
asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
case QImode: \
case E_QImode: \
asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
default: \

12
gcc/config/sh/sh.md
View File

@ -7976,13 +7976,13 @@
switch (GET_MODE (diff_vec))
{
case SImode:
case E_SImode:
return "shll2 %1" "\n"
" mov.l @(r0,%1),%0";
case HImode:
case E_HImode:
return "add %1,%1" "\n"
" mov.w @(r0,%1),%0";
case QImode:
case E_QImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
return "mov.b @(r0,%1),%0" "\n"
" extu.b %0,%0";
@ -8011,17 +8011,17 @@
switch (GET_MODE (diff_vec))
{
case SImode:
case E_SImode:
return "shll2 %1" "\n"
" add r0,%1" "\n"
" mova %O3,r0" "\n"
" mov.l @(r0,%1),%0";
case HImode:
case E_HImode:
return "add %1,%1" "\n"
" add r0,%1" "\n"
" mova %O3,r0" "\n"
" mov.w @(r0,%1),%0";
case QImode:
case E_QImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
return "add r0,%1" "\n"
" mova %O3,r0" "\n"

20
gcc/config/sparc/predicates.md
View File

@ -466,17 +466,17 @@
{
switch (GET_MODE (XEXP (op, 0)))
{
case CCmode:
case CCXmode:
case E_CCmode:
case E_CCXmode:
return true;
case CCNZmode:
case CCXNZmode:
case E_CCNZmode:
case E_CCXNZmode:
return nz_comparison_operator (op, mode);
case CCCmode:
case CCXCmode:
case E_CCCmode:
case E_CCXCmode:
return c_comparison_operator (op, mode);
case CCVmode:
case CCXVmode:
case E_CCVmode:
case E_CCXVmode:
return v_comparison_operator (op, mode);
default:
return false;
@ -489,8 +489,8 @@
{
switch (GET_MODE (XEXP (op, 0)))
{
case CCFPmode:
case CCFPEmode:
case E_CCFPmode:
case E_CCFPEmode:
return true;
default:
return false;

88
gcc/config/sparc/sparc.c
View File

@ -2068,21 +2068,21 @@ sparc_expand_move (machine_mode mode, rtx *operands)
switch (mode)
{
case QImode:
case E_QImode:
/* All QImode constants require only one insn, so proceed. */
break;
case HImode:
case SImode:
case E_HImode:
case E_SImode:
sparc_emit_set_const32 (operands[0], operands[1]);
return true;
case DImode:
case E_DImode:
/* input_operand should have filtered out 32-bit mode. */
sparc_emit_set_const64 (operands[0], operands[1]);
return true;
case TImode:
case E_TImode:
{
rtx high, low;
/* TImode isn't available in 32-bit mode. */
@ -3475,10 +3475,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
case FLOAT_EXTEND:
switch (GET_MODE (operands[1]))
{
case SFmode:
case E_SFmode:
func = "_Qp_stoq";
break;
case DFmode:
case E_DFmode:
func = "_Qp_dtoq";
break;
default:
@ -3489,10 +3489,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
case FLOAT_TRUNCATE:
switch (GET_MODE (operands[0]))
{
case SFmode:
case E_SFmode:
func = "_Qp_qtos";
break;
case DFmode:
case E_DFmode:
func = "_Qp_qtod";
break;
default:
@ -3503,12 +3503,12 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
case FLOAT:
switch (GET_MODE (operands[1]))
{
case SImode:
case E_SImode:
func = "_Qp_itoq";
if (TARGET_ARCH64)
operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
break;
case DImode:
case E_DImode:
func = "_Qp_xtoq";
break;
default:
@ -3519,12 +3519,12 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
case UNSIGNED_FLOAT:
switch (GET_MODE (operands[1]))
{
case SImode:
case E_SImode:
func = "_Qp_uitoq";
if (TARGET_ARCH64)
operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
break;
case DImode:
case E_DImode:
func = "_Qp_uxtoq";
break;
default:
@ -3535,10 +3535,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
case FIX:
switch (GET_MODE (operands[0]))
{
case SImode:
case E_SImode:
func = "_Qp_qtoi";
break;
case DImode:
case E_DImode:
func = "_Qp_qtox";
break;
default:
@ -3549,10 +3549,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
case UNSIGNED_FIX:
switch (GET_MODE (operands[0]))
{
case SImode:
case E_SImode:
func = "_Qp_qtoui";
break;
case DImode:
case E_DImode:
func = "_Qp_qtoux";
break;
default:
@ -7699,11 +7699,11 @@ sparc_preferred_simd_mode (machine_mode mode)
if (TARGET_VIS)
switch (mode)
{
case SImode:
case E_SImode:
return V2SImode;
case HImode:
case E_HImode:
return V4HImode;
case QImode:
case E_QImode:
return V8QImode;
default:;
@ -7973,23 +7973,23 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
switch (mode)
{
case CCmode:
case CCNZmode:
case CCCmode:
case CCVmode:
case E_CCmode:
case E_CCNZmode:
case E_CCCmode:
case E_CCVmode:
labelno = "%%icc, ";
if (v8)
labelno = "";
break;
case CCXmode:
case CCXNZmode:
case CCXCmode:
case CCXVmode:
case E_CCXmode:
case E_CCXNZmode:
case E_CCXCmode:
case E_CCXVmode:
labelno = "%%xcc, ";
gcc_assert (!v8);
break;
case CCFPmode:
case CCFPEmode:
case E_CCFPmode:
case E_CCFPEmode:
{
static char v9_fcc_labelno[] = "%%fccX, ";
/* Set the char indicating the number of the fcc reg to use. */
@ -9047,16 +9047,16 @@ sparc_print_operand (FILE *file, rtx x, int code)
{
switch (GET_MODE (x))
{
case CCmode:
case CCNZmode:
case CCCmode:
case CCVmode:
case E_CCmode:
case E_CCNZmode:
case E_CCCmode:
case E_CCVmode:
s = "%icc";
break;
case CCXmode:
case CCXNZmode:
case CCXCmode:
case CCXVmode:
case E_CCXmode:
case E_CCXNZmode:
case E_CCXCmode:
case E_CCXVmode:
s = "%xcc";
break;
default:
@ -12439,7 +12439,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel)
sel = gen_lowpart (DImode, sel);
switch (vmode)
{
case V2SImode:
case E_V2SImode:
/* inp = xxxxxxxAxxxxxxxB */
t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
NULL_RTX, 1, OPTAB_DIRECT);
@ -12458,7 +12458,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel)
/* sel = { A*4, A*4+1, A*4+2, ... } */
break;
case V4HImode:
case E_V4HImode:
/* inp = xxxAxxxBxxxCxxxD */
t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
NULL_RTX, 1, OPTAB_DIRECT);
@ -12495,7 +12495,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel)
/* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
break;
case V8QImode:
case E_V8QImode:
/* input = xAxBxCxDxExFxGxH */
sel = expand_simple_binop (DImode, AND, sel,
GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32
@ -12793,15 +12793,15 @@ vector_init_bshuffle (rtx target, rtx elt, machine_mode mode,
switch (mode)
{
case V2SImode:
case E_V2SImode:
final_insn = gen_bshufflev2si_vis (target, t1, t1);
bmask = 0x45674567;
break;
case V4HImode:
case E_V4HImode:
final_insn = gen_bshufflev4hi_vis (target, t1, t1);
bmask = 0x67676767;
break;
case V8QImode:
case E_V8QImode:
final_insn = gen_bshufflev8qi_vis (target, t1, t1);
bmask = 0x77777777;
break;

124
gcc/config/spu/spu.c
View File

@ -292,13 +292,13 @@ spu_scalar_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case QImode:
case HImode:
case SImode:
case SFmode:
case DImode:
case TImode:
case DFmode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_SFmode:
case E_DImode:
case E_TImode:
case E_DFmode:
return true;
default:
@ -314,12 +314,12 @@ spu_vector_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case V16QImode:
case V8HImode:
case V4SImode:
case V2DImode:
case V4SFmode:
case V2DFmode:
case E_V16QImode:
case E_V8HImode:
case E_V4SImode:
case E_V2DImode:
case E_V4SFmode:
case E_V2DFmode:
return true;
default:
@ -496,13 +496,13 @@ spu_expand_insv (rtx ops[])
{
switch (dst_mode)
{
case SImode:
case E_SImode:
emit_insn (gen_ashlsi3 (shift_reg, shift_reg, GEN_INT (shift)));
break;
case DImode:
case E_DImode:
emit_insn (gen_ashldi3 (shift_reg, shift_reg, GEN_INT (shift)));
break;
case TImode:
case E_TImode:
emit_insn (gen_ashlti3 (shift_reg, shift_reg, GEN_INT (shift)));
break;
default:
@ -802,50 +802,50 @@ spu_emit_branch_or_set (int is_set, rtx cmp, rtx operands[])
switch (op_mode)
{
case QImode:
case E_QImode:
index = 0;
comp_mode = QImode;
break;
case HImode:
case E_HImode:
index = 1;
comp_mode = HImode;
break;
case SImode:
case E_SImode:
index = 2;
break;
case DImode:
case E_DImode:
index = 3;
break;
case TImode:
case E_TImode:
index = 4;
break;
case SFmode:
case E_SFmode:
index = 5;
break;
case DFmode:
case E_DFmode:
index = 6;
break;
case V16QImode:
case E_V16QImode:
index = 7;
comp_mode = op_mode;
break;
case V8HImode:
case E_V8HImode:
index = 8;
comp_mode = op_mode;
break;
case V4SImode:
case E_V4SImode:
index = 9;
comp_mode = op_mode;
break;
case V4SFmode:
case E_V4SFmode:
index = 10;
comp_mode = V4SImode;
break;
case V2DFmode:
case E_V2DFmode:
index = 11;
comp_mode = V2DImode;
break;
case V2DImode:
case E_V2DImode:
default:
abort ();
}
@ -3710,22 +3710,22 @@ spu_handle_vector_attribute (tree * node, tree name,
unsigned_p = TYPE_UNSIGNED (type);
switch (mode)
{
case DImode:
case E_DImode:
result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
break;
case SImode:
case E_SImode:
result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
break;
case HImode:
case E_HImode:
result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
break;
case QImode:
case E_QImode:
result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
break;
case SFmode:
case E_SFmode:
result = V4SF_type_node;
break;
case DFmode:
case E_DFmode:
result = V2DF_type_node;
break;
default:
@ -5642,24 +5642,24 @@ spu_builtin_splats (rtx ops[])
ops[1] = force_reg (GET_MODE_INNER (mode), ops[1]);
switch (mode)
{
case V2DImode:
case V2DFmode:
case E_V2DImode:
case E_V2DFmode:
shuf =
immed_double_const (0x0001020304050607ll, 0x1011121314151617ll,
TImode);
break;
case V4SImode:
case V4SFmode:
case E_V4SImode:
case E_V4SFmode:
shuf =
immed_double_const (0x0001020300010203ll, 0x0001020300010203ll,
TImode);
break;
case V8HImode:
case E_V8HImode:
shuf =
immed_double_const (0x0203020302030203ll, 0x0203020302030203ll,
TImode);
break;
case V16QImode:
case E_V16QImode:
shuf =
immed_double_const (0x0303030303030303ll, 0x0303030303030303ll,
TImode);
@ -5684,22 +5684,22 @@ spu_builtin_extract (rtx ops[])
{
switch (mode)
{
case V16QImode:
case E_V16QImode:
emit_insn (gen_vec_extractv16qiqi (ops[0], ops[1], ops[2]));
break;
case V8HImode:
case E_V8HImode:
emit_insn (gen_vec_extractv8hihi (ops[0], ops[1], ops[2]));
break;
case V4SFmode:
case E_V4SFmode:
emit_insn (gen_vec_extractv4sfsf (ops[0], ops[1], ops[2]));
break;
case V4SImode:
case E_V4SImode:
emit_insn (gen_vec_extractv4sisi (ops[0], ops[1], ops[2]));
break;
case V2DImode:
case E_V2DImode:
emit_insn (gen_vec_extractv2didi (ops[0], ops[1], ops[2]));
break;
case V2DFmode:
case E_V2DFmode:
emit_insn (gen_vec_extractv2dfdf (ops[0], ops[1], ops[2]));
break;
default:
@ -5714,19 +5714,19 @@ spu_builtin_extract (rtx ops[])
switch (mode)
{
case V16QImode:
case E_V16QImode:
emit_insn (gen_addsi3 (tmp, ops[2], GEN_INT (-3)));
break;
case V8HImode:
case E_V8HImode:
emit_insn (gen_addsi3 (tmp, ops[2], ops[2]));
emit_insn (gen_addsi3 (tmp, tmp, GEN_INT (-2)));
break;
case V4SFmode:
case V4SImode:
case E_V4SFmode:
case E_V4SImode:
emit_insn (gen_ashlsi3 (tmp, ops[2], GEN_INT (2)));
break;
case V2DImode:
case V2DFmode:
case E_V2DImode:
case E_V2DFmode:
emit_insn (gen_ashlsi3 (tmp, ops[2], GEN_INT (3)));
break;
default:
@ -5786,20 +5786,20 @@ spu_builtin_promote (rtx ops[])
offset = gen_reg_rtx (SImode);
switch (mode)
{
case V16QImode:
case E_V16QImode:
emit_insn (gen_subsi3 (offset, GEN_INT (3), ops[2]));
break;
case V8HImode:
case E_V8HImode:
emit_insn (gen_subsi3 (offset, GEN_INT (1), ops[2]));
emit_insn (gen_addsi3 (offset, offset, offset));
break;
case V4SFmode:
case V4SImode:
case E_V4SFmode:
case E_V4SImode:
emit_insn (gen_subsi3 (offset, GEN_INT (0), ops[2]));
emit_insn (gen_ashlsi3 (offset, offset, GEN_INT (2)));
break;
case V2DImode:
case V2DFmode:
case E_V2DImode:
case E_V2DFmode:
emit_insn (gen_ashlsi3 (offset, ops[2], GEN_INT (3)));
break;
default:
@ -5915,19 +5915,19 @@ spu_expand_sign_extend (rtx ops[])
arr[i] = 0x10;
switch (GET_MODE (ops[1]))
{
case HImode:
case E_HImode:
sign = gen_reg_rtx (SImode);
emit_insn (gen_extendhisi2 (sign, ops[1]));
arr[last] = 0x03;
arr[last - 1] = 0x02;
break;
case SImode:
case E_SImode:
sign = gen_reg_rtx (SImode);
emit_insn (gen_ashrsi3 (sign, ops[1], GEN_INT (31)));
for (i = 0; i < 4; i++)
arr[last - i] = 3 - i;
break;
case DImode:
case E_DImode:
sign = gen_reg_rtx (SImode);
c = gen_reg_rtx (SImode);
emit_insn (gen_spu_convert (c, ops[1]));

22
gcc/config/tilegx/tilegx.c
View File

@ -111,15 +111,15 @@ tilegx_scalar_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
case E_TImode:
return true;
case SFmode:
case DFmode:
case E_SFmode:
case E_DFmode:
return true;
default:
@ -1466,16 +1466,16 @@ tilegx_simd_int (rtx num, machine_mode mode)
switch (mode)
{
case QImode:
case E_QImode:
n = 0x0101010101010101LL * (n & 0x000000FF);
break;
case HImode:
case E_HImode:
n = 0x0001000100010001LL * (n & 0x0000FFFF);
break;
case SImode:
case E_SImode:
n = 0x0000000100000001LL * (n & 0xFFFFFFFF);
break;
case DImode:
case E_DImode:
break;
default:
gcc_unreachable ();

20
gcc/config/tilepro/tilepro.c
View File

@ -88,14 +88,14 @@ tilepro_scalar_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case QImode:
case HImode:
case SImode:
case DImode:
case E_QImode:
case E_HImode:
case E_SImode:
case E_DImode:
return true;
case SFmode:
case DFmode:
case E_SFmode:
case E_DFmode:
return true;
default:
@ -1208,15 +1208,15 @@ tilepro_simd_int (rtx num, machine_mode mode)
switch (mode)
{
case QImode:
case E_QImode:
n = 0x01010101 * (n & 0x000000FF);
break;
case HImode:
case E_HImode:
n = 0x00010001 * (n & 0x0000FFFF);
break;
case SImode:
case E_SImode:
break;
case DImode:
case E_DImode:
break;
default:
gcc_unreachable ();

24
gcc/config/v850/v850.c
View File

@ -270,19 +270,19 @@ const_double_split (rtx x, HOST_WIDE_INT * p_high, HOST_WIDE_INT * p_low)
switch (GET_MODE (x))
{
case DFmode:
case E_DFmode:
REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), t);
*p_high = t[1]; /* since v850 is little endian */
*p_low = t[0]; /* high is second word */
return;
case SFmode:
case E_SFmode:
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), *p_high);
*p_low = 0;
return;
case VOIDmode:
case DImode:
case E_VOIDmode:
case E_DImode:
*p_high = CONST_DOUBLE_HIGH (x);
*p_low = CONST_DOUBLE_LOW (x);
return;
@ -594,10 +594,10 @@ v850_print_operand (FILE * file, rtx x, int code)
default:
gcc_unreachable ();
case QImode: fputs (".b", file); break;
case HImode: fputs (".h", file); break;
case SImode: fputs (".w", file); break;
case SFmode: fputs (".w", file); break;
case E_QImode: fputs (".b", file); break;
case E_HImode: fputs (".h", file); break;
case E_SImode: fputs (".w", file); break;
case E_SFmode: fputs (".w", file); break;
}
break;
case '.': /* Register r0. */
@ -1020,7 +1020,7 @@ ep_memory_offset (machine_mode mode, int unsignedp ATTRIBUTE_UNUSED)
switch (mode)
{
case QImode:
case E_QImode:
if (TARGET_SMALL_SLD)
max_offset = (1 << 4);
else if ((TARGET_V850E_UP)
@ -1030,7 +1030,7 @@ ep_memory_offset (machine_mode mode, int unsignedp ATTRIBUTE_UNUSED)
max_offset = (1 << 7);
break;
case HImode:
case E_HImode:
if (TARGET_SMALL_SLD)
max_offset = (1 << 5);
else if ((TARGET_V850E_UP)
@ -1040,8 +1040,8 @@ ep_memory_offset (machine_mode mode, int unsignedp ATTRIBUTE_UNUSED)
max_offset = (1 << 8);
break;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
max_offset = (1 << 8);
break;

30
gcc/config/vax/vax.c
View File

@ -822,18 +822,18 @@ vax_rtx_costs (rtx x, machine_mode mode, int outer_code,
case MULT:
switch (mode)
{
case DFmode:
case E_DFmode:
*total = 16; /* 4 on VAX 9000 */
break;
case SFmode:
case E_SFmode:
*total = 9; /* 4 on VAX 9000, 12 on VAX 2 */
break;
case DImode:
case E_DImode:
*total = 16; /* 6 on VAX 9000, 28 on VAX 2 */
break;
case SImode:
case HImode:
case QImode:
case E_SImode:
case E_HImode:
case E_QImode:
*total = 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
break;
default:
@ -1144,7 +1144,7 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
switch (mode)
{
case DImode:
case E_DImode:
if (operands[1] == const0_rtx)
return "clrq %0";
if (TARGET_QMATH && optimize_size
@ -1257,7 +1257,7 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
}
return "movq %1,%0";
case SImode:
case E_SImode:
if (symbolic_operand (operands[1], SImode))
{
if (push_operand (operands[0], SImode))
@ -1300,7 +1300,7 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
return "pushl %1";
return "movl %1,%0";
case HImode:
case E_HImode:
if (CONST_INT_P (operands[1]))
{
HOST_WIDE_INT i = INTVAL (operands[1]);
@ -1317,7 +1317,7 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
}
return "movw %1,%0";
case QImode:
case E_QImode:
if (CONST_INT_P (operands[1]))
{
HOST_WIDE_INT i = INTVAL (operands[1]);
@ -1352,7 +1352,7 @@ vax_output_int_add (rtx insn, rtx *operands, machine_mode mode)
{
switch (mode)
{
case DImode:
case E_DImode:
{
rtx low[3];
const char *pattern;
@ -1438,7 +1438,7 @@ vax_output_int_add (rtx insn, rtx *operands, machine_mode mode)
return "adwc %2,%0";
}
case SImode:
case E_SImode:
if (rtx_equal_p (operands[0], operands[1]))
{
if (operands[2] == const1_rtx)
@ -1514,7 +1514,7 @@ vax_output_int_add (rtx insn, rtx *operands, machine_mode mode)
return "addl3 %1,%2,%0";
case HImode:
case E_HImode:
if (rtx_equal_p (operands[0], operands[1]))
{
if (operands[2] == const1_rtx)
@ -1533,7 +1533,7 @@ vax_output_int_add (rtx insn, rtx *operands, machine_mode mode)
return "subw3 $%n2,%1,%0";
return "addw3 %1,%2,%0";
case QImode:
case E_QImode:
if (rtx_equal_p (operands[0], operands[1]))
{
if (operands[2] == const1_rtx)
@ -1562,7 +1562,7 @@ vax_output_int_subtract (rtx insn, rtx *operands, machine_mode mode)
{
switch (mode)
{
case DImode:
case E_DImode:
{
rtx low[3];
const char *pattern;

12
gcc/config/visium/predicates.md
View File

@ -153,16 +153,16 @@
{
switch (GET_MODE (XEXP (op, 0)))
{
case CCmode:
case E_CCmode:
return ordered_comparison_operator (op, mode);
case CCNZmode:
case E_CCNZmode:
return visium_nz_comparison_operator (op, mode);
case CCCmode:
case E_CCCmode:
return visium_c_comparison_operator (op, mode);
case CCVmode:
case E_CCVmode:
return visium_v_comparison_operator (op, mode);
case CCFPmode:
case CCFPEmode:
case E_CCFPmode:
case E_CCFPEmode:
return visium_fp_comparison_operator (op, mode);
default:
return false;

24
gcc/config/visium/visium.c
View File

@ -1719,18 +1719,18 @@ rtx_ok_for_offset_p (machine_mode mode, rtx op)
switch (mode)
{
case QImode:
case E_QImode:
return INTVAL (op) <= 31;
case HImode:
case E_HImode:
return (INTVAL (op) % 2) == 0 && INTVAL (op) < 63;
case SImode:
case SFmode:
case E_SImode:
case E_SFmode:
return (INTVAL (op) % 4) == 0 && INTVAL (op) < 127;
case DImode:
case DFmode:
case E_DImode:
case E_DFmode:
return (INTVAL (op) % 4) == 0 && INTVAL (op) < 123;
default:
@ -3323,18 +3323,18 @@ visium_print_operand_address (FILE *file, machine_mode mode, rtx addr)
HOST_WIDE_INT val = INTVAL (y);
switch (mode)
{
case SImode:
case DImode:
case SFmode:
case DFmode:
case E_SImode:
case E_DImode:
case E_SFmode:
case E_DFmode:
val >>= 2;
break;
case HImode:
case E_HImode:
val >>= 1;
break;
case QImode:
case E_QImode:
default:
break;
}

6
gcc/config/visium/visium.h
View File

@ -1528,13 +1528,13 @@ do \
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
switch (GET_MODE (BODY)) \
{ \
case SImode: \
case E_SImode: \
asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
case HImode: \
case E_HImode: \
asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
case QImode: \
case E_QImode: \
asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
default: \

30
gcc/config/xtensa/xtensa.c
View File

@ -591,7 +591,7 @@ xtensa_mem_offset (unsigned v, machine_mode mode)
{
switch (mode)
{
case BLKmode:
case E_BLKmode:
/* Handle the worst case for block moves. See xtensa_expand_block_move
where we emit an optimized block move operation if the block can be
moved in < "move_ratio" pieces. The worst case is when the block is
@ -600,13 +600,13 @@ xtensa_mem_offset (unsigned v, machine_mode mode)
return (xtensa_uimm8 (v)
&& xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
case QImode:
case E_QImode:
return xtensa_uimm8 (v);
case HImode:
case E_HImode:
return xtensa_uimm8x2 (v);
case DFmode:
case E_DFmode:
return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
default:
@ -802,16 +802,16 @@ xtensa_expand_conditional_branch (rtx *operands, machine_mode mode)
switch (mode)
{
case DFmode:
case E_DFmode:
default:
fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
case SImode:
case E_SImode:
invert = FALSE;
cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
break;
case SFmode:
case E_SFmode:
if (!TARGET_HARD_FLOAT)
fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
cmp0, cmp1));
@ -1161,8 +1161,8 @@ xtensa_copy_incoming_a7 (rtx opnd)
switch (mode)
{
case DFmode:
case DImode:
case E_DFmode:
case E_DImode:
/* Copy the value out of A7 here but keep the first word in A6 until
after the set_frame_ptr insn. Otherwise, the register allocator
may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
@ -1170,16 +1170,16 @@ xtensa_copy_incoming_a7 (rtx opnd)
emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
gen_raw_REG (SImode, A7_REG)));
break;
case SFmode:
case E_SFmode:
emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
break;
case SImode:
case E_SImode:
emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
break;
case HImode:
case E_HImode:
emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
break;
case QImode:
case E_QImode:
emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
break;
default:
@ -2581,7 +2581,7 @@ xtensa_output_literal (FILE *file, rtx x, machine_mode mode, int labelno)
switch (mode)
{
case SFmode:
case E_SFmode:
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x),
value_long[0]);
if (HOST_BITS_PER_LONG > 32)
@ -2589,7 +2589,7 @@ xtensa_output_literal (FILE *file, rtx x, machine_mode mode, int labelno)
fprintf (file, "0x%08lx\n", value_long[0]);
break;
case DFmode:
case E_DFmode:
REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x),
value_long);
if (HOST_BITS_PER_LONG > 32)

6
gcc/dfp.c
View File

@ -720,13 +720,13 @@ decimal_real_maxval (REAL_VALUE_TYPE *r, int sign, machine_mode mode)
switch (mode)
{
case SDmode:
case E_SDmode:
max = "9.999999E96";
break;
case DDmode:
case E_DDmode:
max = "9.999999999999999E384";
break;
case TDmode:
case E_TDmode:
max = "9.999999999999999999999999999999999E6144";
break;
default:

7
gcc/objc/ChangeLog
View File

@ -1,3 +1,10 @@
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* objc-encoding.c (encode_gnu_bitfield): Prefix mode names with E_ in
case statements.
2017-08-09 Marek Polacek <polacek@redhat.com>
PR c/81417

16
gcc/objc/objc-encoding.c
View File

@ -756,11 +756,11 @@ encode_gnu_bitfield (int position, tree type, int size)
{
switch (TYPE_MODE (type))
{
case QImode:
case E_QImode:
charType = 'C'; break;
case HImode:
case E_HImode:
charType = 'S'; break;
case SImode:
case E_SImode:
{
if (type == long_unsigned_type_node)
charType = 'L';
@ -768,7 +768,7 @@ encode_gnu_bitfield (int position, tree type, int size)
charType = 'I';
break;
}
case DImode:
case E_DImode:
charType = 'Q'; break;
default:
gcc_unreachable ();
@ -779,11 +779,11 @@ encode_gnu_bitfield (int position, tree type, int size)
{
switch (TYPE_MODE (type))
{
case QImode:
case E_QImode:
charType = 'c'; break;
case HImode:
case E_HImode:
charType = 's'; break;
case SImode:
case E_SImode:
{
if (type == long_integer_type_node)
charType = 'l';
@ -791,7 +791,7 @@ encode_gnu_bitfield (int position, tree type, int size)
charType = 'i';
break;
}
case DImode:
case E_DImode:
charType = 'q'; break;
default:
gcc_unreachable ();

8
gcc/targhooks.c
View File

@ -448,16 +448,16 @@ default_libgcc_floating_mode_supported_p (machine_mode mode)
switch (mode)
{
#ifdef HAVE_SFmode
case SFmode:
case E_SFmode:
#endif
#ifdef HAVE_DFmode
case DFmode:
case E_DFmode:
#endif
#ifdef HAVE_XFmode
case XFmode:
case E_XFmode:
#endif
#ifdef HAVE_TFmode
case TFmode:
case E_TFmode:
#endif
return true;

7
libobjc/ChangeLog
View File

@ -1,3 +1,10 @@
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* encoding.c (_darwin_rs6000_special_round_type_align): Prefix mode
names with E_ in case statements.
2017-02-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/79256

2
libobjc/encoding.c
View File

@ -162,7 +162,7 @@ _darwin_rs6000_special_round_type_align (const char *struc, int comp, int spec)
case UNION_TYPE:
return MAX (MAX (comp, spec), objc_alignof_type (_stp) * __CHAR_BIT__);
break;
case DFmode:
case E_DFmode:
case _C_LNG_LNG:
case _C_ULNG_LNG:
return MAX (MAX (comp, spec), 64);