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mips.md (UNSPEC_COMPARE_AND_SWAP_12): New unspec_volitile.
gcc/ 2008-04-23 David Daney <ddaney@avtrex.com> * config/mips/mips.md (UNSPEC_COMPARE_AND_SWAP_12): New unspec_volitile. (UNSPEC_SYNC_OLD_OP, UNSPEC_SYNC_NEW_OP, UNSPEC_SYNC_EXCHANGE, UNSPEC_MEMORY_BARRIER, UNSPEC_SET_GOT_VERSION, UNSPEC_UPDATE_GOT_VERSION): Renumber. (sync_compare_and_swap<mode>): New expand for QI and HI modes. (compare_and_swap_12): New insn. * config/mips/mips-protos.h (mips_expand_compare_and_swap_12): Declare. * config/mips/mips.c (mips_force_binary): New function. (mips_emit_int_order_test, mips_expand_synci_loop): Use it. (mips_expand_compare_and_swap_12): New function. * config/mips/mips.h (MIPS_COMPARE_AND_SWAP_12): New macro. gcc/testsuite/ * gcc.target/mips/gcc-have-sync-compare-and-swap-1.c: Expect __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 and __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 to be defined. * gcc.target/mips/gcc-have-sync-compare-and-swap-2.c: Likewise. From-SVN: r134695
This commit is contained in:
Richard Sandiford
parent
a93a597ae7
commit
49bce30a21
@ -1,3 +1,18 @@
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2008-04-26 David Daney <ddaney@avtrex.com>
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* config/mips/mips.md (UNSPEC_COMPARE_AND_SWAP_12): New
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unspec_volitile.
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(UNSPEC_SYNC_OLD_OP, UNSPEC_SYNC_NEW_OP, UNSPEC_SYNC_EXCHANGE,
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UNSPEC_MEMORY_BARRIER, UNSPEC_SET_GOT_VERSION,
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UNSPEC_UPDATE_GOT_VERSION): Renumber.
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(sync_compare_and_swap<mode>): New expand for QI and HI modes.
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(compare_and_swap_12): New insn.
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* config/mips/mips-protos.h (mips_expand_compare_and_swap_12): Declare.
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* config/mips/mips.c (mips_force_binary): New function.
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(mips_emit_int_order_test, mips_expand_synci_loop): Use it.
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(mips_expand_compare_and_swap_12): New function.
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* config/mips/mips.h (MIPS_COMPARE_AND_SWAP_12): New macro.
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2008-04-25 Jan Hubicka <jh@suse.cz>
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PR testsuite/35843
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@ -292,5 +292,6 @@ extern bool mips_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
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extern const char *mips16e_output_save_restore (rtx, HOST_WIDE_INT);
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extern bool mips16e_save_restore_pattern_p (rtx, HOST_WIDE_INT,
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struct mips16e_save_restore_info *);
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extern void mips_expand_compare_and_swap_12 (rtx, rtx, rtx, rtx);
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#endif /* ! GCC_MIPS_PROTOS_H */
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@ -1,6 +1,6 @@
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/* Subroutines used for MIPS code generation.
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Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
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1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
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1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by A. Lichnewsky, lich@inria.inria.fr.
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Changes by Michael Meissner, meissner@osf.org.
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@ -2121,6 +2121,19 @@ mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
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gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
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}
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/* Compute (CODE OP0 OP1) and store the result in a new register
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of mode MODE. Return that new register. */
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static rtx
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mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
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{
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rtx reg;
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reg = gen_reg_rtx (mode);
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mips_emit_binary (code, reg, op0, op1);
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return reg;
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}
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/* Copy VALUE to a register and return that register. If new pseudos
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are allowed, copy it into a new register, otherwise use DEST. */
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@ -3741,8 +3754,10 @@ mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
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}
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else if (invert_ptr == 0)
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{
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rtx inv_target = gen_reg_rtx (GET_MODE (target));
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mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
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rtx inv_target;
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inv_target = mips_force_binary (GET_MODE (target),
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inv_code, cmp0, cmp1);
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mips_emit_binary (XOR, target, inv_target, const1_rtx);
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}
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else
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@ -5850,8 +5865,7 @@ mips_expand_synci_loop (rtx begin, rtx end)
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emit_insn (gen_synci (begin));
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cmp = gen_reg_rtx (Pmode);
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mips_emit_binary (GTU, cmp, begin, end);
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cmp = mips_force_binary (Pmode, GTU, begin, end);
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mips_emit_binary (PLUS, begin, begin, inc);
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@ -5859,6 +5873,68 @@ mips_expand_synci_loop (rtx begin, rtx end)
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emit_jump_insn (gen_condjump (cmp_result, label));
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}
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/* Expand a QI or HI mode compare_and_swap. The operands are the same
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as for the generator function. */
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void
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mips_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
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{
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rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
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rtx mask, inverted_mask, oldvalsi, old_shifted, newvalsi, new_shifted, res;
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/* Compute the address of the containing SImode value. */
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orig_addr = force_reg (Pmode, XEXP (mem, 0));
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memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
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force_reg (Pmode, GEN_INT (-4)));
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/* Create a memory reference for it. */
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memsi = gen_rtx_MEM (SImode, memsi_addr);
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set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
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MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
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/* Work out the byte offset of the QImode or HImode value,
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counting from the least significant byte. */
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shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
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if (TARGET_BIG_ENDIAN)
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mips_emit_binary (XOR, shift, shift,
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GEN_INT (GET_MODE (mem) == QImode ? 3 : 2));
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/* Multiply by eight to convert the shift value from bytes to bits. */
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mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
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/* Make the final shift an SImode value, so that it can be used in
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SImode operations. */
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shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
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/* Set MASK to an inclusive mask of the QImode or HImode value. */
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unshifted_mask = GEN_INT (GET_MODE_MASK (GET_MODE (mem)));
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unshifted_mask = force_reg (SImode, unshifted_mask);
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mask = mips_force_binary (SImode, ASHIFT, unshifted_mask, shiftsi);
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/* Compute the equivalent exclusive mask. */
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inverted_mask = gen_reg_rtx (SImode);
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emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
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gen_rtx_NOT (SImode, mask)));
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/* Shift the old value into place. */
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oldvalsi = force_reg (SImode, gen_lowpart (SImode, oldval));
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old_shifted = mips_force_binary (SImode, ASHIFT, oldvalsi, shiftsi);
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/* Do the same for the new value. */
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newvalsi = force_reg (SImode, gen_lowpart (SImode, newval));
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new_shifted = mips_force_binary (SImode, ASHIFT, newvalsi, shiftsi);
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/* Do the SImode atomic access. */
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res = gen_reg_rtx (SImode);
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emit_insn (gen_compare_and_swap_12 (res, memsi, mask, inverted_mask,
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old_shifted, new_shifted));
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/* Shift and convert the result. */
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mips_emit_binary (AND, res, res, mask);
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mips_emit_binary (LSHIFTRT, res, res, shiftsi);
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mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
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}
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/* Return true if it is possible to use left/right accesses for a
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bitfield of WIDTH bits starting BITPOS bits into *OP. When
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returning true, update *OP, *LEFT and *RIGHT as follows:
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@ -2904,6 +2904,30 @@ while (0)
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"\tnop\n" \
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"2:\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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- Given that %2 contains a bit mask and %3 the inverted mask and
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that %4 and %5 have already been ANDed with $2.
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- Compares the bits in memory reference %1 selected by mask %2 to
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register %4 and, if they are equal, changes the selected bits
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in memory to %5.
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- Sets register %0 to the old value of memory reference %1.
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*/
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#define MIPS_COMPARE_AND_SWAP_12 \
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"%(%<%[%|sync\n" \
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"1:\tll\t%0,%1\n" \
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"\tand\t%@,%0,%2\n" \
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"\tbne\t%@,%4,2f\n" \
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"\tand\t%@,%0,%3\n" \
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"\tor\t%@,%@,%5\n" \
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"\tsc\t%@,%1\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)\n" \
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"2:\n"
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/* Return an asm string that atomically:
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- Sets memory reference %0 to %0 INSN %1.
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@ -54,12 +54,13 @@
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(UNSPEC_SYNCI 35)
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(UNSPEC_SYNC 36)
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(UNSPEC_COMPARE_AND_SWAP 37)
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(UNSPEC_SYNC_OLD_OP 38)
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(UNSPEC_SYNC_NEW_OP 39)
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(UNSPEC_SYNC_EXCHANGE 40)
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(UNSPEC_MEMORY_BARRIER 41)
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(UNSPEC_SET_GOT_VERSION 42)
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(UNSPEC_UPDATE_GOT_VERSION 43)
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(UNSPEC_COMPARE_AND_SWAP_12 38)
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(UNSPEC_SYNC_OLD_OP 39)
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(UNSPEC_SYNC_NEW_OP 40)
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(UNSPEC_SYNC_EXCHANGE 41)
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(UNSPEC_MEMORY_BARRIER 42)
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(UNSPEC_SET_GOT_VERSION 43)
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(UNSPEC_UPDATE_GOT_VERSION 44)
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(UNSPEC_ADDRESS_FIRST 100)
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@ -4447,6 +4448,34 @@
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}
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[(set_attr "length" "32")])
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(define_expand "sync_compare_and_swap<mode>"
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[(match_operand:SHORT 0 "register_operand")
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(match_operand:SHORT 1 "memory_operand")
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(match_operand:SHORT 2 "general_operand")
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(match_operand:SHORT 3 "general_operand")]
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"GENERATE_LL_SC"
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{
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mips_expand_compare_and_swap_12 (operands[0], operands[1],
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operands[2], operands[3]);
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DONE;
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})
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;; Helper insn for mips_expand_compare_and_swap_12.
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(define_insn "compare_and_swap_12"
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[(set (match_operand:SI 0 "register_operand" "=&d")
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(match_operand:SI 1 "memory_operand" "+R"))
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(set (match_dup 1)
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(unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
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(match_operand:SI 3 "register_operand" "d")
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(match_operand:SI 4 "register_operand" "d")
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(match_operand:SI 5 "register_operand" "d")]
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UNSPEC_COMPARE_AND_SWAP_12))]
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"GENERATE_LL_SC"
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{
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return MIPS_COMPARE_AND_SWAP_12;
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}
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[(set_attr "length" "40")])
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(define_insn "sync_add<mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+R,R")
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(unspec_volatile:GPR
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@ -1,3 +1,10 @@
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2008-04-26 Richard Sandiford <rsandifo@nildram.co.uk>
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* gcc.target/mips/gcc-have-sync-compare-and-swap-1.c: Expect
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__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 and
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__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 to be defined.
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* gcc.target/mips/gcc-have-sync-compare-and-swap-2.c: Likewise.
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2008-04-25 Tobias Burnus <burnus@net-b.de>
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* gfortran/array_constructor_23.f: Change REAL(10) into kind > 8.
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@ -1,11 +1,11 @@
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/* { dg-do preprocess } */
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/* { dg-mips-options "-mips2" } */
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
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#if defined (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1) == defined (__mips16)
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#error nonono
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#endif
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
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#if defined (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) == defined (__mips16)
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#error nonono
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#endif
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@ -1,11 +1,11 @@
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/* { dg-do preprocess } */
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/* { dg-mips-options "-mgp64" } */
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
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#if defined (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1) == defined (__mips16)
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#error nonono
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#endif
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
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#if defined (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) == defined (__mips16)
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#error nonono
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#endif
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