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[RISC-V][PR target/116590] Avoid emitting multiple instructions from fmacc patterns
So much like my patch from last week, this removes alternatives that create multiple instructions that we really should have never needed. In this case it fixes one of two bugs in pr116590. In particular we don't want vmvNr instructions for thead-vector. Those instructions were emitted as part of those two instruction sequences. I've tested this in my tester and assuming the pre-commit tester is happy, I'll push it to the trunk. PR target/116590 gcc * config/riscv/vector.md (pred_mul_<optab>mode_undef): Drop unnecessary alternatives. (pred_<madd_msub><mode>): Likewise. (pred_<macc_msac><mode>): Likewise. (pred_<madd_msub><mode>_scalar): Likewise. (pred_<macc_msac><mode>_scalar): Likewise. (pred_mul_neg_<optab><mode>_undef): Likewise. (pred_<nmsub_nmadd><mode>): Likewise. (pred_<nmsac_nmacc><mode>): Likewise. (pred_<nmsub_nmadd><mode>_scalar): Likewise. (pred_<nmsac_nmacc><mode>_scalar): Likewise. gcc/testsuite * gcc.target/riscv/pr116590.c: New test.
This commit is contained in:
Jeff Law
parent
fbca864a7b
commit
41fb3a5669
@ -6393,62 +6393,58 @@
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})
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(define_insn "*pred_mul_<optab><mode>_undef"
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd, vr, vr")
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(if_then_else:V_VLSF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
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||||
(match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
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||||
(match_operand 7 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 10 "const_int_operand" " i, i, i, i, i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
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(match_operand 6 "vector_length_operand" " rK,rK, rK, rK")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(match_operand 10 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)
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(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
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(plus_minus:V_VLSF
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(mult:V_VLSF
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(match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
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(match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))
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(match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
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(match_operand:V_VLSF 3 "register_operand" " 0,vr, 0, vr")
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(match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr"))
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(match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, 0"))
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(match_operand:V_VLSF 2 "vector_undef_operand")))]
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"TARGET_VECTOR"
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"@
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vf<madd_msub>.vv\t%0,%4,%5%p1
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vf<macc_msac>.vv\t%0,%3,%4%p1
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vmv%m3r.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1
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vf<madd_msub>.vv\t%0,%4,%5%p1
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vf<macc_msac>.vv\t%0,%3,%4%p1
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vmv%m3r.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1"
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vf<macc_msac>.vv\t%0,%3,%4%p1"
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[(set_attr "type" "vfmuladd")
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(set_attr "mode" "<MODE>")
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(set (attr "frm_mode")
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(symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
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(define_insn "*pred_<madd_msub><mode>"
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
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(if_then_else:V_VLSF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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(match_operand 9 "const_int_operand" " i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)
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(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
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(plus_minus:V_VLSF
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(mult:V_VLSF
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(match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
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(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
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(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
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(match_operand:V_VLSF 2 "register_operand" " 0, 0")
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(match_operand:V_VLSF 3 "register_operand" " vr, vr"))
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(match_operand:V_VLSF 4 "register_operand" " vr, vr"))
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(match_dup 2)))]
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"TARGET_VECTOR"
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"@
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vf<madd_msub>.vv\t%0,%3,%4%p1
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vmv%m2r.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
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vf<madd_msub>.vv\t%0,%3,%4%p1
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vmv%m2r.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1"
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vf<madd_msub>.vv\t%0,%3,%4%p1"
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[(set_attr "type" "vfmuladd")
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(set_attr "mode" "<MODE>")
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(set_attr "merge_op_idx" "2")
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@ -6460,30 +6456,28 @@
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(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
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(define_insn "*pred_<macc_msac><mode>"
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
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(if_then_else:V_VLSF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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(match_operand 9 "const_int_operand" " i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)
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(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
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(plus_minus:V_VLSF
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(mult:V_VLSF
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(match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
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(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
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(match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
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(match_operand:V_VLSF 2 "register_operand" " vr, vr")
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(match_operand:V_VLSF 3 "register_operand" " vr, vr"))
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(match_operand:V_VLSF 4 "register_operand" " 0, 0"))
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(match_dup 4)))]
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"TARGET_VECTOR"
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"@
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vf<macc_msac>.vv\t%0,%2,%3%p1
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vmv%m4r.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
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vf<macc_msac>.vv\t%0,%2,%3%p1
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vmv%m4r.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1"
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vf<macc_msac>.vv\t%0,%2,%3%p1"
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[(set_attr "type" "vfmuladd")
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(set_attr "mode" "<MODE>")
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(set_attr "merge_op_idx" "4")
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@ -6518,31 +6512,29 @@
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{})
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(define_insn "*pred_<madd_msub><mode>_scalar"
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
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(if_then_else:V_VLSF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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(match_operand 9 "const_int_operand" " i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)
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(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
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(plus_minus:V_VLSF
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(mult:V_VLSF
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(vec_duplicate:V_VLSF
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(match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
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(match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr"))
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(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
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(match_operand:<VEL> 2 "register_operand" " f, f"))
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(match_operand:V_VLSF 3 "register_operand" " 0, 0"))
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(match_operand:V_VLSF 4 "register_operand" " vr, vr"))
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(match_dup 3)))]
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"TARGET_VECTOR"
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"@
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vf<madd_msub>.vf\t%0,%2,%4%p1
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vmv%m3r.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
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vf<madd_msub>.vf\t%0,%2,%4%p1
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vmv%m3r.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1"
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vf<madd_msub>.vf\t%0,%2,%4%p1"
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[(set_attr "type" "vfmuladd")
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(set_attr "mode" "<MODE>")
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(set_attr "merge_op_idx" "3")
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@ -6554,31 +6546,29 @@
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(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
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(define_insn "*pred_<macc_msac><mode>_scalar"
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
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(if_then_else:V_VLSF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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(match_operand 9 "const_int_operand" " i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)
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(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
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(plus_minus:V_VLSF
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(mult:V_VLSF
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(vec_duplicate:V_VLSF
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(match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
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(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
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(match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
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(match_operand:<VEL> 2 "register_operand" " f, f"))
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(match_operand:V_VLSF 3 "register_operand" "vr, vr"))
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(match_operand:V_VLSF 4 "register_operand" " 0, 0"))
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(match_dup 4)))]
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"TARGET_VECTOR"
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"@
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vf<macc_msac>.vf\t%0,%2,%3%p1
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vmv%m4r.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
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vf<macc_msac>.vf\t%0,%2,%3%p1
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vmv%m4r.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1"
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vf<macc_msac>.vf\t%0,%2,%3%p1"
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[(set_attr "type" "vfmuladd")
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(set_attr "mode" "<MODE>")
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(set_attr "merge_op_idx" "4")
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@ -6615,64 +6605,60 @@
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})
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(define_insn "*pred_mul_neg_<optab><mode>_undef"
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,vr, vr")
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(if_then_else:V_VLSF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
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(match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
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(match_operand 7 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 10 "const_int_operand" " i, i, i, i, i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
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(match_operand 6 "vector_length_operand" " rK,rK, rK, rK")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(match_operand 10 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)
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(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
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(plus_minus:V_VLSF
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(neg:V_VLSF
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(mult:V_VLSF
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(match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
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(match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr")))
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(match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
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(match_operand:V_VLSF 3 "register_operand" " 0,vr, 0, vr")
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(match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr")))
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(match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, 0"))
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(match_operand:V_VLSF 2 "vector_undef_operand")))]
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"TARGET_VECTOR"
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"@
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vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
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vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
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vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
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vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
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vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
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vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1"
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vf<nmsac_nmacc>.vv\t%0,%3,%4%p1"
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[(set_attr "type" "vfmuladd")
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(set_attr "mode" "<MODE>")
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(set (attr "frm_mode")
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(symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
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(define_insn "*pred_<nmsub_nmadd><mode>"
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
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(if_then_else:V_VLSF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i, i, i")
|
||||
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
|
||||
(match_operand 5 "vector_length_operand" " rK, rK")
|
||||
(match_operand 6 "const_int_operand" " i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i")
|
||||
(reg:SI VL_REGNUM)
|
||||
(reg:SI VTYPE_REGNUM)
|
||||
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
|
||||
(plus_minus:V_VLSF
|
||||
(neg:V_VLSF
|
||||
(mult:V_VLSF
|
||||
(match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
|
||||
(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
|
||||
(match_operand:V_VLSF 2 "register_operand" " 0, 0")
|
||||
(match_operand:V_VLSF 3 "register_operand" " vr, vr")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " vr, vr"))
|
||||
(match_dup 2)))]
|
||||
"TARGET_VECTOR"
|
||||
"@
|
||||
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
|
||||
vmv%m2r.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
|
||||
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
|
||||
vmv%m2r.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
|
||||
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
|
||||
[(set_attr "type" "vfmuladd")
|
||||
(set_attr "mode" "<MODE>")
|
||||
(set_attr "merge_op_idx" "2")
|
||||
@ -6684,31 +6670,29 @@
|
||||
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
|
||||
|
||||
(define_insn "*pred_<nmsac_nmacc><mode>"
|
||||
[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
|
||||
[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
|
||||
(if_then_else:V_VLSF
|
||||
(unspec:<VM>
|
||||
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
|
||||
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
|
||||
(match_operand 6 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i, i, i")
|
||||
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
|
||||
(match_operand 5 "vector_length_operand" " rK, rK")
|
||||
(match_operand 6 "const_int_operand" " i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i")
|
||||
(reg:SI VL_REGNUM)
|
||||
(reg:SI VTYPE_REGNUM)
|
||||
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
|
||||
(plus_minus:V_VLSF
|
||||
(neg:V_VLSF
|
||||
(mult:V_VLSF
|
||||
(match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
|
||||
(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
|
||||
(match_operand:V_VLSF 2 "register_operand" " vr, vr")
|
||||
(match_operand:V_VLSF 3 "register_operand" " vr, vr")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " 0, 0"))
|
||||
(match_dup 4)))]
|
||||
"TARGET_VECTOR"
|
||||
"@
|
||||
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
|
||||
vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
|
||||
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
|
||||
vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
|
||||
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
|
||||
[(set_attr "type" "vfmuladd")
|
||||
(set_attr "mode" "<MODE>")
|
||||
(set_attr "merge_op_idx" "4")
|
||||
@ -6744,15 +6728,15 @@
|
||||
{})
|
||||
|
||||
(define_insn "*pred_<nmsub_nmadd><mode>_scalar"
|
||||
[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
|
||||
[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
|
||||
(if_then_else:V_VLSF
|
||||
(unspec:<VM>
|
||||
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
|
||||
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
|
||||
(match_operand 6 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i, i, i")
|
||||
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
|
||||
(match_operand 5 "vector_length_operand" " rK, rK")
|
||||
(match_operand 6 "const_int_operand" " i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i")
|
||||
(reg:SI VL_REGNUM)
|
||||
(reg:SI VTYPE_REGNUM)
|
||||
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
|
||||
@ -6760,16 +6744,14 @@
|
||||
(neg:V_VLSF
|
||||
(mult:V_VLSF
|
||||
(vec_duplicate:V_VLSF
|
||||
(match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
|
||||
(match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
|
||||
(match_operand:<VEL> 2 "register_operand" " f, f"))
|
||||
(match_operand:V_VLSF 3 "register_operand" " 0, 0")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " vr, vr"))
|
||||
(match_dup 3)))]
|
||||
"TARGET_VECTOR"
|
||||
"@
|
||||
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
|
||||
vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
|
||||
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
|
||||
vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
|
||||
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
|
||||
[(set_attr "type" "vfmuladd")
|
||||
(set_attr "mode" "<MODE>")
|
||||
(set_attr "merge_op_idx" "3")
|
||||
@ -6781,15 +6763,15 @@
|
||||
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
|
||||
|
||||
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
|
||||
[(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
|
||||
[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
|
||||
(if_then_else:V_VLSF
|
||||
(unspec:<VM>
|
||||
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
|
||||
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
|
||||
(match_operand 6 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i, i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i, i, i")
|
||||
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
|
||||
(match_operand 5 "vector_length_operand" " rK, rK")
|
||||
(match_operand 6 "const_int_operand" " i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i")
|
||||
(reg:SI VL_REGNUM)
|
||||
(reg:SI VTYPE_REGNUM)
|
||||
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
|
||||
@ -6797,16 +6779,14 @@
|
||||
(neg:V_VLSF
|
||||
(mult:V_VLSF
|
||||
(vec_duplicate:V_VLSF
|
||||
(match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
|
||||
(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
|
||||
(match_operand:<VEL> 2 "register_operand" " f, f"))
|
||||
(match_operand:V_VLSF 3 "register_operand" " vr, vr")))
|
||||
(match_operand:V_VLSF 4 "register_operand" " 0, 0"))
|
||||
(match_dup 4)))]
|
||||
"TARGET_VECTOR"
|
||||
"@
|
||||
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
|
||||
vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
|
||||
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
|
||||
vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
|
||||
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
|
||||
[(set_attr "type" "vfmuladd")
|
||||
(set_attr "mode" "<MODE>")
|
||||
(set_attr "merge_op_idx" "4")
|
||||
|
||||
54
gcc/testsuite/gcc.target/riscv/pr116590.c
Normal file
54
gcc/testsuite/gcc.target/riscv/pr116590.c
Normal file
@ -0,0 +1,54 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d" } */
|
||||
typedef long unsigned int size_t;
|
||||
#pragma riscv intrinsic "vector"
|
||||
|
||||
|
||||
void vmv8r()
|
||||
{
|
||||
float x[32];
|
||||
|
||||
size_t vl = __riscv_vsetvl_e32m8(32);
|
||||
vfloat32m8_t _p = __riscv_vle32_v_f32m8(x, vl);
|
||||
|
||||
_p = __riscv_vfmacc_vf_f32m8(__riscv_vfmv_v_f_f32m8(0.5f, vl), 1.442, _p, vl);
|
||||
|
||||
__riscv_vse32_v_f32m8(x, _p, vl);
|
||||
}
|
||||
|
||||
void gen_vmv8r(float* ptr, int n)
|
||||
{
|
||||
while (n > 0)
|
||||
{
|
||||
size_t vl = __riscv_vsetvl_e32m8(n);
|
||||
|
||||
vfloat32m8_t _p = __riscv_vle32_v_f32m8(ptr, vl);
|
||||
|
||||
_p = __riscv_vfmacc_vf_f32m8(__riscv_vfmv_v_f_f32m8(0.5f, vl), 1.4f, _p, vl);
|
||||
|
||||
__riscv_vse32_v_f32m8(ptr, _p, vl);
|
||||
|
||||
ptr += vl;
|
||||
n -= vl;
|
||||
}
|
||||
}
|
||||
|
||||
void no_vmv8r(float* ptr, int n)
|
||||
{
|
||||
size_t vl0 = __riscv_vsetvl_e32m8(n);
|
||||
vfloat32m8_t _a = __riscv_vfmv_v_f_f32m8(0.5f, vl0);
|
||||
|
||||
while (n > 0)
|
||||
{
|
||||
size_t vl = __riscv_vsetvl_e32m8(n);
|
||||
|
||||
vfloat32m8_t _p = __riscv_vle32_v_f32m8(ptr, vl);
|
||||
|
||||
_p = __riscv_vfmacc_vf_f32m8(_a, 1.4f, _p, vl);
|
||||
|
||||
__riscv_vse32_v_f32m8(ptr, _p, vl);
|
||||
|
||||
ptr += vl;
|
||||
n -= vl;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user