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ifcvt.c: Fix comment typos.
* ifcvt.c: Fix comment typos. * lcm.c: Likewise. * libgcc2.c: Likewise. * local-alloc.c: Likewise. * loop.c: Likewise. * predict.c: Likewise. * ra-build.c: Likewise. * ra.c: Likewise. * ra-colorize.c: Likewise. * ra.h: Likewise. * ra-rewrite.c: Likewise. * regmove.c: Likewise. * reload.h: Likewise. * rtlanal.c: Likewise. * toplev.c: Likewise. * tree.h: Likewise. * unwind-dw2-fde-glibc.c: Likewise. * vmsdbgout.c: Likewise. From-SVN: r61421
This commit is contained in:
parent
fd2190ca49
commit
3d042e770b
@ -1,3 +1,24 @@
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2003-01-16 Kazu Hirata <kazu@cs.umass.edu>
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* ifcvt.c: Fix comment typos.
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* lcm.c: Likewise.
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* libgcc2.c: Likewise.
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* local-alloc.c: Likewise.
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* loop.c: Likewise.
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* predict.c: Likewise.
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* ra-build.c: Likewise.
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* ra.c: Likewise.
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* ra-colorize.c: Likewise.
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* ra.h: Likewise.
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* ra-rewrite.c: Likewise.
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* regmove.c: Likewise.
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* reload.h: Likewise.
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* rtlanal.c: Likewise.
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* toplev.c: Likewise.
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* tree.h: Likewise.
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* unwind-dw2-fde-glibc.c: Likewise.
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* vmsdbgout.c: Likewise.
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2003-01-16 Richard Henderson <rth@redhat.com>
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* dwarf2out.c (struct file_table): Remove.
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@ -2282,7 +2282,7 @@ find_if_block (ce_info)
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int max_insns = MAX_CONDITIONAL_EXECUTE;
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int n_insns;
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/* Determine if the preceeding block is an && or || block. */
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/* Determine if the preceding block is an && or || block. */
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if ((n_insns = block_jumps_and_fallthru_p (bb, else_bb)) >= 0)
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{
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ce_info->and_and_p = TRUE;
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@ -2877,7 +2877,7 @@ dead_or_predicable (test_bb, merge_bb, other_bb, new_dest, reversep)
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if (HAVE_conditional_execution)
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{
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/* In the conditional execution case, we have things easy. We know
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the condition is reversable. We don't have to check life info,
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the condition is reversible. We don't have to check life info,
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becase we're going to conditionally execute the code anyway.
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All that's left is making sure the insns involved can actually
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be predicated. */
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@ -307,7 +307,7 @@ compute_laterin (edge_list, earliest, antloc, later, laterin)
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qin = worklist;
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/* Note that we do not use the last allocated element for our queue,
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as EXIT_BLOCK is never inserted into it. In fact the above allocation
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of n_basic_blocks + 1 elements is not encessary. */
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of n_basic_blocks + 1 elements is not necessary. */
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qend = &worklist[n_basic_blocks];
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qlen = n_basic_blocks;
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@ -849,9 +849,9 @@ pre_edge_rev_lcm (file, n_exprs, transp, st_avloc, st_antloc, kill,
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The LCM algorithm is then run over the flow graph to determine where to
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place the sets to the highest-priority value in respect of first the first
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insn in any one block. Any adjustments required to the transparancy
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insn in any one block. Any adjustments required to the transparency
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vectors are made, then the next iteration starts for the next-lower
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priority mode, till for each entity all modes are exhasted.
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priority mode, till for each entity all modes are exhausted.
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More details are located in the code for optimize_mode_switching(). */
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@ -234,7 +234,7 @@ __mulvdi3 (DWtype u, DWtype v)
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#endif
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/* Unless shift functions are defined whith full ANSI prototypes,
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/* Unless shift functions are defined with full ANSI prototypes,
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parameter b will be promoted to int if word_type is smaller than an int. */
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#ifdef L_lshrdi3
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DWtype
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@ -1347,7 +1347,7 @@ gcov_exit (void)
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#if defined (TARGET_HAS_F_SETLKW)
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/* After a fork, another process might try to read and/or write
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the same file simultanously. So if we can, lock the file to
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the same file simultaneously. So if we can, lock the file to
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avoid race conditions. */
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while (fcntl (fileno (da_file), F_SETLKW, &s_flock)
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&& errno == EINTR)
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@ -1179,7 +1179,7 @@ update_equiv_regs ()
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}
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/* Mark REG as having no known equivalence.
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Some instructions might have been proceessed before and furnished
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Some instructions might have been processed before and furnished
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with REG_EQUIV notes for this register; these notes will have to be
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removed.
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STORE is the piece of RTL that does the non-constant / conflicting
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@ -1327,7 +1327,7 @@ block_alloc (b)
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must match operand zero. In that case, skip any
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operand that doesn't list operand 0 since we know that
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the operand always conflicts with operand 0. We
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ignore commutatity in this case to keep things simple. */
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ignore commutativity in this case to keep things simple. */
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if (n_matching_alts == recog_data.n_alternatives
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&& 0 == requires_inout (recog_data.constraints[i]))
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continue;
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22
gcc/loop.c
22
gcc/loop.c
@ -82,7 +82,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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#define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
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/* Parameterize some prefetch heuristics so they can be turned on and off
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easily for performance testing on new architecures. These can be
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easily for performance testing on new architectures. These can be
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defined in target-dependent files. */
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/* Prefetch is worthwhile only when loads/stores are dense. */
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@ -793,7 +793,7 @@ scan_loop (loop, flags)
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}
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}
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/* For parallels, add any possible uses to the depencies, as
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/* For parallels, add any possible uses to the dependencies, as
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we can't move the insn without resolving them first. */
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if (GET_CODE (PATTERN (p)) == PARALLEL)
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{
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@ -3620,7 +3620,7 @@ check_store (x, pat, data)
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/* Like rtx_equal_p, but attempts to swap commutative operands. This is
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important to get some addresses combined. Later more sophisticated
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transformations can be added when necesary.
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transformations can be added when necessary.
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??? Same trick with swapping operand is done at several other places.
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It can be nice to develop some common way to handle this. */
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@ -5537,7 +5537,7 @@ valid_initial_value_p (x, insn, call_seen, loop_start)
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as a possible giv. INSN is the insn whose pattern X comes from.
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NOT_EVERY_ITERATION is 1 if the insn might not be executed during
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every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
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more thanonce in each loop iteration. */
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more than once in each loop iteration. */
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static void
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find_mem_givs (loop, x, insn, not_every_iteration, maybe_multiple)
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@ -5742,7 +5742,7 @@ record_giv (loop, v, insn, src_reg, dest_reg, mult_val, add_val, ext_val,
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rtx set = single_set (insn);
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rtx temp;
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/* Attempt to prove constantness of the values. Don't let simplity_rtx
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/* Attempt to prove constantness of the values. Don't let simplify_rtx
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undo the MULT canonicalization that we performed earlier. */
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temp = simplify_rtx (add_val);
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if (temp
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@ -6686,7 +6686,7 @@ simplify_giv_expr (loop, x, ext_val, benefit)
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arg1)),
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ext_val, benefit);
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}
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/* Porpagate the MULT expressions to the intermost nodes. */
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/* Propagate the MULT expressions to the intermost nodes. */
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else if (GET_CODE (arg0) == PLUS)
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{
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/* (invar_0 + invar_1) * invar_2. Distribute. */
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@ -7372,7 +7372,7 @@ check_ext_dependent_givs (bl, loop_info)
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constants in order to be certain of no overflow. */
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/* ??? An unknown iteration count with an increment of +-1
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combined with friendly exit tests of against an invariant
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value is also ameanable to optimization. Not implemented. */
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value is also amenable to optimization. Not implemented. */
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if (loop_info->n_iterations > 0
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&& bl->initial_value
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&& GET_CODE (bl->initial_value) == CONST_INT
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@ -7394,7 +7394,7 @@ check_ext_dependent_givs (bl, loop_info)
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neg_incr = 1, abs_incr = -abs_incr;
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total_incr = abs_incr * loop_info->n_iterations;
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/* Check for host arithmatic overflow. */
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/* Check for host arithmetic overflow. */
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if (total_incr / loop_info->n_iterations == abs_incr)
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{
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unsigned HOST_WIDE_INT u_max;
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@ -7407,7 +7407,7 @@ check_ext_dependent_givs (bl, loop_info)
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/* Check zero extension of biv ok. */
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if (start_val >= 0
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/* Check for host arithmatic overflow. */
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/* Check for host arithmetic overflow. */
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&& (neg_incr
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? u_end_val < u_start_val
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: u_end_val > u_start_val)
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@ -7425,7 +7425,7 @@ check_ext_dependent_givs (bl, loop_info)
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keep this fact in mind -- myself included on occasion.
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So leave alone with the signed overflow optimizations. */
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if (start_val >= -s_max - 1
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/* Check for host arithmatic overflow. */
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/* Check for host arithmetic overflow. */
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&& (neg_incr
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? s_end_val < start_val
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: s_end_val > start_val)
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@ -10541,7 +10541,7 @@ loop_insn_sink (loop, pattern)
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}
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/* bl->final_value can be eighter general_operand or PLUS of general_operand
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and constant. Emit sequence of intructions to load it into REG */
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and constant. Emit sequence of instructions to load it into REG. */
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static rtx
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gen_load_of_final_value (reg, final_value)
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rtx reg, final_value;
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@ -570,7 +570,7 @@ estimate_probability (loops_info)
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if (FLOAT_MODE_P (GET_MODE (XEXP (cond, 0))))
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;
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/* Comparisons with 0 are often used for booleans and there is
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nothing usefull to predict about them. */
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nothing useful to predict about them. */
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else if (XEXP (cond, 1) == const0_rtx
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|| XEXP (cond, 0) == const0_rtx)
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;
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@ -586,7 +586,7 @@ estimate_probability (loops_info)
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if (FLOAT_MODE_P (GET_MODE (XEXP (cond, 0))))
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;
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/* Comparisons with 0 are often used for booleans and there is
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nothing usefull to predict about them. */
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nothing useful to predict about them. */
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else if (XEXP (cond, 1) == const0_rtx
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|| XEXP (cond, 0) == const0_rtx)
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;
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oldwebs can't have their references changed. The
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incremental machinery barfs on that. */
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|| (!rtx_unstable_p (src) && !contains_pseudo (src))
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/* Additionally also memrefs to stack-slots are usefull, when
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/* Additionally also memrefs to stack-slots are useful, when
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we created them ourself. They might not have set their
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unchanging flag set, but nevertheless they are stable across
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the livetime in question. */
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@ -1511,7 +1511,7 @@ colorize_one_web (web, hard)
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struct web *aw = alias (w);
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/* If we are a spill-temp, we also look at webs coalesced
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to precolored ones. Otherwise we only look at webs which
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themself were colored, or coalesced to one. */
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themselves were colored, or coalesced to one. */
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if (aw->type == PRECOLORED && w != aw && web->spill_temp
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&& flag_ra_optimistic_coalescing)
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{
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sbitmap_zero (already_webs);
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/* We need to recheck all uses of all webs involved in spilling (and the
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uses added by spill insns, but those are not analyzed yet).
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Those are the spilled webs themself, webs coalesced to spilled ones,
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Those are the spilled webs themselves, webs coalesced to spilled ones,
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and webs conflicting with any of them. */
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for (pass = 0; pass < 2; pass++)
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for (d = (pass == 0) ? WEBS(SPILLED) : WEBS(COALESCED); d; d = d->next)
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4
gcc/ra.c
4
gcc/ra.c
@ -681,7 +681,7 @@ reg_alloc ()
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/* Setup debugging levels. */
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switch (0)
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{
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/* Some usefull presets of the debug level, I often use. */
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/* Some useful presets of the debug level, I often use. */
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case 0: debug_new_regalloc = DUMP_EVER; break;
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case 1: debug_new_regalloc = DUMP_COSTS; break;
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case 2: debug_new_regalloc = DUMP_IGRAPH_M; break;
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@ -807,7 +807,7 @@ reg_alloc ()
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/* Those new pseudos need to have their REFS count set. */
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reg_scan_update (get_insns (), NULL, max_regno);
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max_regno = max_reg_num ();
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/* And they need usefull classes too. */
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/* And they need useful classes too. */
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regclass (get_insns (), max_reg_num (), rtl_dump_file);
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rtl_dump_file = ra_dump_file;
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2
gcc/ra.h
2
gcc/ra.h
@ -258,7 +258,7 @@ struct web
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/* Number of usable colors in usable_regs. */
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int num_freedom;
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/* After successfull coloring the graph each web gets a new reg rtx,
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/* After successful coloring the graph each web gets a new reg rtx,
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with which the original uses and defs are replaced. This is it. */
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rtx reg_rtx;
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@ -647,7 +647,7 @@ optimize_reg_copy_2 (insn, dest, src)
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}
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/* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST.
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Look if SRC dies there, and if it is only set once, by loading
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it from memory. If so, try to encorporate the zero/sign extension
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it from memory. If so, try to incorporate the zero/sign extension
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into the memory read, change SRC to the mode of DEST, and alter
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the remaining accesses to use the appropriate SUBREG. This allows
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SRC and DEST to be tied later. */
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/* IN_RTX is the value loaded by a reload that we now decided to inherit,
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or a subpart of it. If we have any replacements registered for IN_RTX,
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chancel the reloads that were supposed to load them.
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Return nonzero if we chanceled any reloads. */
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cancel the reloads that were supposed to load them.
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Return nonzero if we canceled any reloads. */
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extern int remove_address_replacements PARAMS ((rtx in_rtx));
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/* Like rtx_equal_p except that it allows a REG and a SUBREG to match
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@ -3420,7 +3420,7 @@ hoist_test_store (x, val, live)
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/* Pseudo registers can be allways replaced by another pseudo to avoid
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the side effect, for hard register we must ensure that they are dead.
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Eventually we may want to add code to try turn pseudos to hards, but it
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is unlikely usefull. */
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is unlikely useful. */
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if (REGNO (x) < FIRST_PSEUDO_REGISTER)
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{
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@ -3150,7 +3150,7 @@ rest_of_compilation (decl)
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= combine_instructions (insns, max_reg_num ());
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/* Combining insns may have turned an indirect jump into a
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direct jump. Rebuid the JUMP_LABEL fields of jumping
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direct jump. Rebuild the JUMP_LABEL fields of jumping
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instructions. */
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if (rebuild_jump_labels_after_combine)
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{
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@ -682,7 +682,7 @@ extern void tree_vec_elt_check_failed PARAMS ((int, int, const char *,
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bounded pointer. It is insufficient to determine the boundedness
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of an expression EXP with BOUNDED_POINTER_TYPE_P (TREE_TYPE (EXP)),
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since we allow pointer to be temporarily cast to integer for
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rounding up to an alignment boudary in a way that preserves the
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rounding up to an alignment boundary in a way that preserves the
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pointer's bounds.
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In an IDENTIFIER_NODE, nonzero means that the name is prefixed with
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@ -155,7 +155,7 @@ _Unwind_IteratePhdrCallback (struct dl_phdr_info *info, size_t size, void *ptr)
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data->dbase = NULL;
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if (p_dynamic)
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{
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/* For dynamicly linked executables and shared libraries,
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/* For dynamically linked executables and shared libraries,
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DT_PLTGOT is the gp value for that object. */
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ElfW(Dyn) *dyn = (ElfW(Dyn) *) (p_dynamic->p_vaddr + load_base);
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for (; dyn->d_tag != DT_NULL ; dyn++)
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@ -352,7 +352,7 @@ static char text_end_label[MAX_ARTIFICIAL_LABEL_BYTES];
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#endif
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/* This is similar to the default ASM_OUTPUT_ASCII, except that no trailing
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newline is produced. When flag_verbose_asm is asserted, we add commnetary
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newline is produced. When flag_verbose_asm is asserted, we add commentary
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at the end of the line, so we must avoid output of a newline here. */
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#ifndef ASM_OUTPUT_DEBUG_STRING
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#define ASM_OUTPUT_DEBUG_STRING(FILE,P) \
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