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sparc.c (sparc_emit_set_symbolic_const64): If we are given conflicting registers...

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* config/sparc/sparc.c (sparc_emit_set_symbolic_const64): If
we are given conflicting registers, switch to the other one we
had allocated for us.
* config/sparc/sparc.md (reload_indi, reload_outdi): Pass op[2]
as TImode so we know when the "other" register is available.

From-SVN: r49412
This commit is contained in:
DJ Delorie 2002-02-01 16:54:39 -05:00 committed by DJ Delorie
parent 1c24f830c5
commit 3968de80f8
3 changed files with 37 additions and 15 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2002-02-01 DJ Delorie <dj@redhat.com>
* config/sparc/sparc.c (sparc_emit_set_symbolic_const64): If
we are given conflicting registers, switch to the other one we
had allocated for us.
* config/sparc/sparc.md (reload_indi, reload_outdi): Pass op[2]
as TImode so we know when the "other" register is available.
2002-02-01 David O'Brien <obrien@FreeBSD.org>
* config/sparc/sol2-sld-64.h: Include sparc/biarch64.h rather than

38
gcc/config/sparc/sparc.c
View File

@ -1366,6 +1366,14 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
rtx op1;
rtx temp1;
{
rtx ti_temp1 = 0;
if (temp1 && GET_MODE (temp1) == TImode)
{
ti_temp1 = temp1;
temp1 = gen_rtx_REG (DImode, REGNO (temp1));
}
switch (sparc_cmodel)
{
case CM_MEDLOW:
@ -1419,12 +1427,16 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
sllx %temp3, 32, %temp5
or %temp4, %temp5, %reg */
/* Getting this right wrt. reloading is really tricky.
We _MUST_ have a separate temporary at this point,
if we don't barf immediately instead of generating
incorrect code. */
/* It is possible that one of the registers we got for operands[2]
might coincide with that of operands[0] (which is why we made
it TImode). Pick the other one to use as our scratch. */
if (rtx_equal_p (temp1, op0))
abort ();
{
if (ti_temp1)
temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
else
abort();
}
emit_insn (gen_sethh (op0, op1));
emit_insn (gen_setlm (temp1, op1));
@ -1462,12 +1474,16 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
}
else
{
/* Getting this right wrt. reloading is really tricky.
We _MUST_ have a separate temporary at this point,
so we barf immediately instead of generating
incorrect code. */
if (temp1 == op0)
abort ();
/* It is possible that one of the registers we got for operands[2]
might coincide with that of operands[0] (which is why we made
it TImode). Pick the other one to use as our scratch. */
if (rtx_equal_p (temp1, op0))
{
if (ti_temp1)
temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
else
abort();
}
emit_insn (gen_embmedany_textuhi (op0, op1));
emit_insn (gen_embmedany_texthi (temp1, op1));

6
gcc/config/sparc/sparc.md
View File

@ -2734,8 +2734,7 @@
&& ! flag_pic"
"
{
sparc_emit_set_symbolic_const64 (operands[0], operands[1],
gen_rtx_REG (DImode, REGNO (operands[2])));
sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
DONE;
}")
@ -2748,8 +2747,7 @@
&& ! flag_pic"
"
{
sparc_emit_set_symbolic_const64 (operands[0], operands[1],
gen_rtx_REG (DImode, REGNO (operands[2])));
sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
DONE;
}")