mirrors/gcc
1
0
Fork 0
mirror of https://gcc.gnu.org/git/gcc.git synced 2024-11-24 03:14:08 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

RISC-V: Fix sync.md and riscv.cc whitespace errors

Browse Source 
This patch fixes whitespace errors introduced with
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html

2023-04-26 Patrick O'Neill <patrick@rivosinc.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc: Fix whitespace.
	* config/riscv/sync.md: Fix whitespace.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
This commit is contained in:
Patrick O'Neill 2023-04-26 14:13:19 -07:00
parent 9b40ca2569
commit 2a26872984
2 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/config/riscv/riscv.cc
View File

@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask,
emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask,
gen_lowpart (QImode, *shift)));
emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask));
emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask));
}
/* Leftshift a subword within an SImode register. */
@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift,
emit_move_insn (value_reg, simplify_gen_subreg (SImode, value,
mode, 0));
emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
gen_lowpart (QImode, shift)));
emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
gen_lowpart (QImode, shift)));
}
/* Initialize the GCC target structure. */

16
gcc/config/riscv/sync.md
View File

@ -128,10 +128,10 @@
{
/* We have no QImode/HImode atomics, so form a mask, then use
subword_atomic_fetch_strong_nand to implement a LR/SC version of the
operation. */
operation. */
/* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
is disabled */
is disabled. */
rtx old = gen_reg_rtx (SImode);
rtx mem = operands[1];
@ -193,10 +193,10 @@
{
/* We have no QImode/HImode atomics, so form a mask, then use
subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
operation. */
operation. */
/* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
is disabled */
is disabled. */
rtx old = gen_reg_rtx (SImode);
rtx mem = operands[1];
@ -367,7 +367,7 @@
{
rtx difference = gen_rtx_MINUS (SImode, val, exp);
compare = gen_reg_rtx (SImode);
emit_move_insn (compare, difference);
emit_move_insn (compare, difference);
}
if (word_mode != SImode)
@ -393,10 +393,10 @@
{
/* We have no QImode/HImode atomics, so form a mask, then use
subword_atomic_cas_strong<mode> to implement a LR/SC version of the
operation. */
operation. */
/* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
is disabled */
is disabled. */
rtx old = gen_reg_rtx (SImode);
rtx mem = operands[1];
@ -461,7 +461,7 @@
"TARGET_ATOMIC"
{
/* We have no QImode atomics, so use the address LSBs to form a mask,
then use an aligned SImode atomic. */
then use an aligned SImode atomic. */
rtx result = operands[0];
rtx mem = operands[1];
rtx model = operands[2];