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arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo hard-register and also updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives accordingly. This patch also adds support to emit ".pacspval" directive when "pac ip, lr, sp" instruction in generated in the assembly. RA_AUTH_CODE register number is 107 and it's dwarf register number is 143. Applying this patch on top of PACBTI series posted here https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599658.html and when compiling the following test.c with "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard fasynchronous-unwind-tables -g -O0 -S" command line options, the assembly output after this patch looks like below: $cat test.c void fun1(int a); void fun(int a,...) { fun1(a); } int main() { fun (10); return 0; } $ arm-none-eabi-gcc -march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard -fasynchronous-unwind-tables -g -O0 -S test.s Assembly output: ... fun: ... .pacspval pac ip, lr, sp .cfi_register 143, 12 push {r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -24 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... main: ... .pacspval pac ip, lr, sp .cfi_register 143, 12 push {r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... gcc/ChangeLog: 2023-01-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/aout.h (ra_auth_code): Add entry in enum. * config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE register to dwarf frame expression. (arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register. (arm_expand_prologue): Update frame related information and reg notes for pac/pacbit insn. (arm_regno_class): Check for pac pseudo reigster. (arm_dbx_register_number): Assign ra_auth_code register number in dwarf. (arm_init_machine_status): Set pacspval_needed to zero. (arm_debugger_regno): Check for PAC register. (arm_unwind_emit_sequence): Print .save directive with ra_auth_code register. (arm_unwind_emit_set): Add entry for IP_REGNUM in switch case. (arm_unwind_emit): Update REG_CFA_REGISTER case._ * config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify. (DWARF_PAC_REGNUM): Define. (IS_PAC_REGNUM): Likewise. (enum reg_class): Add PAC_REG entry. (machine_function): Add pacbti_needed state to structure. * config/arm/arm.md (RA_AUTH_CODE): Define. gcc/testsuite/ChangeLog: 2023-01-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * g++.target/arm/pac-1.C: New test. * gcc.target/arm/pac-15.c: Likewise.
This commit is contained in:
Srinath Parvathaneni
parent
3a0dd2cc28
commit
273874e925
@ -74,7 +74,8 @@
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"wr8", "wr9", "wr10", "wr11", \
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"wr12", "wr13", "wr14", "wr15", \
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"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
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"cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
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"cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0", \
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"ra_auth_code" \
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}
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#endif
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@ -22272,7 +22272,33 @@ emit_multi_reg_push (unsigned long mask, unsigned long dwarf_regs_mask)
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{
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if (mask & (1 << i))
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{
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reg = gen_rtx_REG (SImode, i);
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/* NOTE: Dwarf code emitter handle reg-reg copies correctly and in the
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following example reg-reg copy of SP to IP register is handled
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through .cfi_def_cfa_register directive and the .cfi_offset
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directive for IP register is skipped by dwarf code emitter.
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Example:
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mov ip, sp
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.cfi_def_cfa_register 12
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push {fp, ip, lr, pc}
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.cfi_offset 11, -16
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.cfi_offset 13, -12
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.cfi_offset 14, -8
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Where as Arm-specific .save directive handling is different to that
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of dwarf code emitter and it doesn't consider reg-reg copies while
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updating the register list. When PACBTI is enabled we manually
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updated the .save directive register list to use "ra_auth_code"
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(pseduo register 143) instead of IP register as shown in following
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pseduo code.
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Example:
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pacbti ip, lr, sp
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.cfi_register 143, 12
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push {r3, r7, ip, lr}
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.save {r3, r7, ra_auth_code, lr}
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*/
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rtx dwarf_reg = reg = gen_rtx_REG (SImode, i);
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if (arm_current_function_pac_enabled_p () && i == IP_REGNUM)
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dwarf_reg = gen_rtx_REG (SImode, RA_AUTH_CODE);
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XVECEXP (par, 0, 0)
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= gen_rtx_SET (gen_frame_mem
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@ -22290,7 +22316,7 @@ emit_multi_reg_push (unsigned long mask, unsigned long dwarf_regs_mask)
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if (dwarf_regs_mask & (1 << i))
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{
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tmp = gen_rtx_SET (gen_frame_mem (SImode, stack_pointer_rtx),
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reg);
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dwarf_reg);
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RTX_FRAME_RELATED_P (tmp) = 1;
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XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
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}
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@ -22303,7 +22329,9 @@ emit_multi_reg_push (unsigned long mask, unsigned long dwarf_regs_mask)
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{
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if (mask & (1 << i))
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{
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reg = gen_rtx_REG (SImode, i);
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rtx dwarf_reg = reg = gen_rtx_REG (SImode, i);
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if (arm_current_function_pac_enabled_p () && i == IP_REGNUM)
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dwarf_reg = gen_rtx_REG (SImode, RA_AUTH_CODE);
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XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
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@ -22314,7 +22342,7 @@ emit_multi_reg_push (unsigned long mask, unsigned long dwarf_regs_mask)
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(SImode,
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plus_constant (Pmode, stack_pointer_rtx,
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4 * j)),
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reg);
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dwarf_reg);
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RTX_FRAME_RELATED_P (tmp) = 1;
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XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
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}
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@ -22399,7 +22427,9 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
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for (j = 0, i = 0; j < num_regs; i++)
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if (saved_regs_mask & (1 << i))
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{
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reg = gen_rtx_REG (SImode, i);
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rtx dwarf_reg = reg = gen_rtx_REG (SImode, i);
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if (arm_current_function_pac_enabled_p () && i == IP_REGNUM)
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dwarf_reg = gen_rtx_REG (SImode, RA_AUTH_CODE);
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if ((num_regs == 1) && emit_update && !return_in_pc)
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{
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/* Emit single load with writeback. */
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@ -22407,7 +22437,8 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
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gen_rtx_POST_INC (Pmode,
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stack_pointer_rtx));
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tmp = emit_insn (gen_rtx_SET (reg, tmp));
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REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
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REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, dwarf_reg,
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dwarf);
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return;
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}
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@ -22421,7 +22452,7 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
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/* We need to maintain a sequence for DWARF info too. As dwarf info
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should not have PC, skip PC. */
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if (i != PC_REGNUM)
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dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
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dwarf = alloc_reg_note (REG_CFA_RESTORE, dwarf_reg, dwarf);
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j++;
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}
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@ -23603,6 +23634,8 @@ arm_expand_prologue (void)
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-fp_offset));
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RTX_FRAME_RELATED_P (insn) = 1;
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add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
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if (arm_current_function_pac_enabled_p ())
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cfun->machine->pacspval_needed = 1;
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}
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else
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{
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@ -23638,6 +23671,8 @@ arm_expand_prologue (void)
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RTX_FRAME_RELATED_P (insn) = 1;
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fp_offset = args_to_push;
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args_to_push = 0;
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if (arm_current_function_pac_enabled_p ())
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cfun->machine->pacspval_needed = 1;
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}
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}
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@ -23647,9 +23682,13 @@ arm_expand_prologue (void)
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one will be added before the push of the clobbered IP (if
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necessary) by the bti pass. */
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if (aarch_bti_enabled () && !clobber_ip)
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emit_insn (gen_pacbti_nop ());
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insn = emit_insn (gen_pacbti_nop ());
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else
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emit_insn (gen_pac_nop ());
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insn = emit_insn (gen_pac_nop ());
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rtx dwarf = gen_rtx_SET (ip_rtx, gen_rtx_REG (SImode, RA_AUTH_CODE));
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RTX_FRAME_RELATED_P (insn) = 1;
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add_reg_note (insn, REG_CFA_REGISTER, dwarf);
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}
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if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
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@ -25731,6 +25770,9 @@ arm_regno_class (int regno)
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if (IS_VPR_REGNUM (regno))
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return VPR_REG;
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if (IS_PAC_REGNUM (regno))
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return PAC_REG;
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if (TARGET_THUMB1)
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{
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if (regno == STACK_POINTER_REGNUM)
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@ -26891,6 +26933,7 @@ arm_init_machine_status (void)
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machine->func_type = ARM_FT_UNKNOWN;
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#endif
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machine->static_chain_stack_bytes = -1;
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machine->pacspval_needed = 0;
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return machine;
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}
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@ -29700,6 +29743,9 @@ arm_debugger_regno (unsigned int regno)
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if (IS_IWMMXT_REGNUM (regno))
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return 112 + regno - FIRST_IWMMXT_REGNUM;
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if (IS_PAC_REGNUM (regno))
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return DWARF_PAC_REGNUM;
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return DWARF_FRAME_REGISTERS;
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}
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@ -29793,7 +29839,7 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p)
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gcc_assert (nregs);
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reg = REGNO (SET_SRC (XVECEXP (p, 0, 1)));
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if (reg < 16)
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if (reg < 16 || IS_PAC_REGNUM (reg))
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{
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/* For -Os dummy registers can be pushed at the beginning to
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avoid separate stack pointer adjustment. */
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@ -29850,6 +29896,8 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p)
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double precision register names. */
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if (IS_VFP_REGNUM (reg))
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asm_fprintf (out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
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else if (IS_PAC_REGNUM (reg))
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asm_fprintf (asm_out_file, "ra_auth_code");
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else
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asm_fprintf (out_file, "%r", reg);
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@ -29944,7 +29992,7 @@ arm_unwind_emit_set (FILE * out_file, rtx p)
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/* Move from sp to reg. */
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asm_fprintf (out_file, "\t.movsp %r\n", REGNO (e0));
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}
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else if (GET_CODE (e1) == PLUS
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else if (GET_CODE (e1) == PLUS
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&& REG_P (XEXP (e1, 0))
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&& REGNO (XEXP (e1, 0)) == SP_REGNUM
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&& CONST_INT_P (XEXP (e1, 1)))
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@ -29953,6 +30001,11 @@ arm_unwind_emit_set (FILE * out_file, rtx p)
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asm_fprintf (out_file, "\t.movsp %r, #%d\n",
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REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
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}
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else if (REGNO (e0) == IP_REGNUM && arm_current_function_pac_enabled_p ())
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{
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if (cfun->machine->pacspval_needed)
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asm_fprintf (out_file, "\t.pacspval\n");
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}
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else
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abort ();
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break;
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@ -30007,10 +30060,15 @@ arm_unwind_emit (FILE * out_file, rtx_insn *insn)
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src = SET_SRC (pat);
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dest = SET_DEST (pat);
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gcc_assert (src == stack_pointer_rtx);
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gcc_assert (src == stack_pointer_rtx
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|| IS_PAC_REGNUM (REGNO (src)));
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reg = REGNO (dest);
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asm_fprintf (out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
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reg + 0x90, reg);
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if (IS_PAC_REGNUM (REGNO (src)))
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arm_unwind_emit_set (out_file, PATTERN (insn));
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else
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asm_fprintf (out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
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reg + 0x90, reg);
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}
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handled_one = true;
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break;
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@ -816,7 +816,8 @@ extern const int arm_arch_cde_coproc_bits[];
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s16-s31 S VFP variable (aka d8-d15).
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vfpcc Not a real register. Represents the VFP condition
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code flags.
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vpr Used to represent MVE VPR predication. */
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vpr Used to represent MVE VPR predication.
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ra_auth_code Pseudo register to save PAC. */
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/* The stack backtrace structure is as follows:
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fp points to here: | save code pointer | [fp]
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@ -857,7 +858,7 @@ extern const int arm_arch_cde_coproc_bits[];
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1,1,1,1,1,1,1,1, \
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1,1,1,1, \
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/* Specials. */ \
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1,1,1,1,1,1,1 \
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1,1,1,1,1,1,1,1 \
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}
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/* 1 for registers not available across function calls.
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@ -887,7 +888,7 @@ extern const int arm_arch_cde_coproc_bits[];
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1,1,1,1,1,1,1,1, \
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1,1,1,1, \
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/* Specials. */ \
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1,1,1,1,1,1,1 \
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1,1,1,1,1,1,1,1 \
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}
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#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
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@ -1063,10 +1064,12 @@ extern const int arm_arch_cde_coproc_bits[];
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&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
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/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
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+ 1 APSRQ + 1 APSRGE + 1 VPR. */
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+ 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
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/* Intel Wireless MMX Technology registers add 16 + 4 more. */
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/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
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#define FIRST_PSEUDO_REGISTER 107
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#define FIRST_PSEUDO_REGISTER 108
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#define DWARF_PAC_REGNUM 143
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#define DEBUGGER_REGNO(REGNO) arm_debugger_regno (REGNO)
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@ -1253,12 +1256,15 @@ extern int arm_regs_in_sequence[];
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CC_REGNUM, VFPCC_REGNUM, \
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FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
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SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
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APSRGE_REGNUM, VPR_REGNUM \
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APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \
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}
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#define IS_VPR_REGNUM(REGNUM) \
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((REGNUM) == VPR_REGNUM)
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#define IS_PAC_REGNUM(REGNUM) \
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((REGNUM) == RA_AUTH_CODE)
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/* Use different register alloc ordering for Thumb. */
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#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
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@ -1297,6 +1303,7 @@ enum reg_class
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SFP_REG,
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AFP_REG,
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VPR_REG,
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PAC_REG,
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GENERAL_AND_VPR_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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@ -1327,6 +1334,7 @@ enum reg_class
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"SFP_REG", \
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"AFP_REG", \
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"VPR_REG", \
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"PAC_REG", \
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"GENERAL_AND_VPR_REGS", \
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"ALL_REGS" \
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}
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@ -1356,6 +1364,7 @@ enum reg_class
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \
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{ 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \
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{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \
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}
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@ -1621,6 +1630,9 @@ typedef struct GTY(()) machine_function
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/* The number of bytes used to store the static chain register on the
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stack, above the stack frame. */
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int static_chain_stack_bytes;
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/* Set to 1 when pointer authentication operation uses value of SP other
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than the incoming stack pointer value. */
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int pacspval_needed;
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}
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machine_function;
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#endif
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@ -42,6 +42,7 @@
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(APSRQ_REGNUM 104) ; Q bit pseudo register
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(APSRGE_REGNUM 105) ; GE bits pseudo register
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(VPR_REGNUM 106) ; Vector Predication Register - MVE register.
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(RA_AUTH_CODE 107) ; Pseudo register to save PAC.
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]
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)
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;; 3rd operand to select_dominance_cc_mode
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35
gcc/testsuite/g++.target/arm/pac-1.C
Normal file
35
gcc/testsuite/g++.target/arm/pac-1.C
Normal file
@ -0,0 +1,35 @@
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/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE pseudo hard-register. */
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/* { dg-do compile } */
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/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */
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/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard -g -O0" } */
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__attribute__((noinline)) void
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fn1 (int a, int b, int c)
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{
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if (a != b + c)
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__builtin_abort ();
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else
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throw b+c;
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}
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int main ()
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{
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int a = 120;
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try
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{
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fn1 (a, 40, 80);
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}
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||||
catch (int x)
|
||||
{
|
||||
if (x != a)
|
||||
__builtin_abort ();
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "pac ip, lr, sp" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\.cfi_register 143, 12" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\.save {r7, ra_auth_code, lr}" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "\.cfi_offset 143, -8" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\.save {r4, r7, ra_auth_code, lr}" 1 } } */
|
||||
32
gcc/testsuite/gcc.target/arm/pac-15.c
Normal file
32
gcc/testsuite/gcc.target/arm/pac-15.c
Normal file
@ -0,0 +1,32 @@
|
||||
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE pseudo hard-register. */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target mbranch_protection_ok } */
|
||||
/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */
|
||||
/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard -fasynchronous-unwind-tables -g -O0" } */
|
||||
|
||||
#include "stdio.h"
|
||||
|
||||
__attribute__((noinline)) int
|
||||
fn1 (int a)
|
||||
{
|
||||
const char *fmt = "branch-protection";
|
||||
int fun1(int x,const char *fmt,int c,int d)
|
||||
{
|
||||
printf("string = %s\n",fmt);
|
||||
return x+c+d;
|
||||
}
|
||||
return fun1(a,fmt,10,10);
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
return fn1 (40);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\.pacspval" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "pac ip, lr, sp" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "\.cfi_register 143, 12" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "\.save {r7, ra_auth_code, lr}" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\.cfi_offset 143, -8" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\.save {r3, r7, ra_auth_code, lr}" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "\.cfi_offset 143, -12" 1 } } */
|
||||
Loading…
Reference in New Issue
Block a user