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rs6000: Add veqv support to *eqv<mode>3_internal1

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When making patch to replace TARGET_P8_VECTOR, I noticed
for *eqv<BOOL_128:mode>3_internal1 unlike the other logical
operations, we only exploited the vsx version.  I think it
is an oversight, this patch is to consider veqv as well.

gcc/ChangeLog:

	* config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate
	insn veqv if TARGET_ALTIVEC and operands are altivec_register_operand.
This commit is contained in:
Kewen Lin 2024-11-21 07:41:33 +00:00 committed by Kewen Lin
parent 0719ade048
commit 2441dc2495
1 changed files with 4 additions and 1 deletions
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gcc/config/rs6000/rs6000.md
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@ -7557,9 +7557,12 @@
(match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
"TARGET_P8_VECTOR"
{
if (vsx_register_operand (operands[0], <MODE>mode))
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
return "xxleqv %x0,%x1,%x2";
if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
return "veqv %0,%1,%2";
return "#";
}
"TARGET_P8_VECTOR && reload_completed