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hppa: Revise TImode aritmetic patterns to support arith11_operands
2024-11-25 John David Anglin <danglin@gcc.gnu.org> gcc/ChangeLog: PR target/117645 * config/pa/pa.md (addti3): Revise pattern to support arith11_operands. Use "R" operand prefix to print least significant register of TImode register pair. (addvti3, subti3, subvti3): Likewise. (negti2, negvti2): Use "R" operand prefix.
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John David Anglin
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4b09e2c67e
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22b13b1d4e
@ -5481,18 +5481,20 @@
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(define_insn "addti3"
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[(set (match_operand:TI 0 "register_operand" "=r")
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(plus:TI (match_operand:TI 1 "register_operand" "r")
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(match_operand:TI 2 "register_operand" "r")))]
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(plus:TI (match_operand:TI 1 "register_operand" "%r")
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(match_operand:TI 2 "arith11_operand" "rI")))]
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"TARGET_64BIT"
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"*
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{
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operands[3] = gen_lowpart (DImode, operands[0]);
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operands[4] = gen_lowpart (DImode, operands[1]);
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operands[5] = gen_lowpart (DImode, operands[2]);
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operands[0] = gen_highpart (DImode, operands[0]);
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operands[1] = gen_highpart (DImode, operands[1]);
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operands[2] = gen_highpart (DImode, operands[2]);
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return \"add %4,%5,%3\;add,dc %1,%2,%0\";
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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if (INTVAL (operands[2]) >= 0)
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return \"addi %2,%R1,%R0\;add,dc %1,%%r0,%0\";
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else
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return \"addi %2,%R1,%R0\;sub,db %1,%%r0,%0\";
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}
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else
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return \"add %R2,%R1,%R0\;add,dc %2,%1,%0\";
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}"
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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@ -5500,7 +5502,7 @@
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(define_insn "addvti3"
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[(set (match_operand:TI 0 "register_operand" "=r")
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(plus:TI (match_operand:TI 1 "register_operand" "r")
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(match_operand:TI 2 "register_operand" "r")))
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(match_operand:TI 2 "arith11_operand" "rI")))
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(trap_if (ne (plus:OI (sign_extend:OI (match_dup 1))
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(sign_extend:OI (match_dup 2)))
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(sign_extend:OI (plus:TI (match_dup 1)
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@ -5509,39 +5511,49 @@
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"TARGET_64BIT"
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"*
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{
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operands[3] = gen_lowpart (DImode, operands[0]);
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operands[4] = gen_lowpart (DImode, operands[1]);
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operands[5] = gen_lowpart (DImode, operands[2]);
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operands[0] = gen_highpart (DImode, operands[0]);
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operands[1] = gen_highpart (DImode, operands[1]);
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operands[2] = gen_highpart (DImode, operands[2]);
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return \"add %4,%5,%3\;add,dc,tsv %1,%2,%0\";
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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if (INTVAL (operands[2]) >= 0)
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return \"addi %2,%R1,%R0\;add,dc,tsv %1,%%r0,%0\";
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else
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return \"addi %2,%R1,%R0\;sub,db,tsv %1,%%r0,%0\";
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}
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else
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return \"add %R2,%R1,%R0\;add,dc,tsv %2,%1,%0\";
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}"
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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(define_insn "subti3"
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[(set (match_operand:TI 0 "register_operand" "=r")
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(minus:TI (match_operand:TI 1 "register_operand" "r")
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(match_operand:TI 2 "register_operand" "r")))]
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[(set (match_operand:TI 0 "register_operand" "=r,&r")
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(minus:TI (match_operand:TI 1 "arith11_operand" "r,I")
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(match_operand:TI 2 "reg_or_0_operand" "rM,rM")))]
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"TARGET_64BIT"
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"*
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{
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operands[3] = gen_lowpart (DImode, operands[0]);
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operands[4] = gen_lowpart (DImode, operands[1]);
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operands[5] = gen_lowpart (DImode, operands[2]);
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operands[0] = gen_highpart (DImode, operands[0]);
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operands[1] = gen_highpart (DImode, operands[1]);
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operands[2] = gen_highpart (DImode, operands[2]);
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return \"sub %4,%5,%3\;sub,db %1,%2,%0\";
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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if (INTVAL (operands[1]) >= 0)
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return \"subi %1,%R2,%R0\;sub,db %%r0,%2,%0\";
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else
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return \"ldi -1,%0\;subi %1,%R2,%R0\;sub,db %0,%2,%0\";
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}
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else
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return \"sub %R1,%R2,%R0\;sub,db %1,%2,%0\";
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}"
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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(set (attr "length")
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(if_then_else (eq_attr "alternative" "0")
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(const_int 8)
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(if_then_else (ge (symbol_ref "INTVAL (operands[1])")
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(const_int 0))
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(const_int 8)
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(const_int 12))))])
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(define_insn "subvti3"
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[(set (match_operand:TI 0 "register_operand" "=r")
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(minus:TI (match_operand:TI 1 "register_operand" "r")
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(match_operand:TI 2 "register_operand" "r")))
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[(set (match_operand:TI 0 "register_operand" "=r,&r")
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(minus:TI (match_operand:TI 1 "arith11_operand" "r,I")
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(match_operand:TI 2 "reg_or_0_operand" "rM,rM")))
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(trap_if (ne (minus:OI (sign_extend:OI (match_dup 1))
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(sign_extend:OI (match_dup 2)))
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(sign_extend:OI (minus:TI (match_dup 1)
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@ -5550,16 +5562,24 @@
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"TARGET_64BIT"
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"*
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{
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operands[3] = gen_lowpart (DImode, operands[0]);
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operands[4] = gen_lowpart (DImode, operands[1]);
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operands[5] = gen_lowpart (DImode, operands[2]);
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operands[0] = gen_highpart (DImode, operands[0]);
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operands[1] = gen_highpart (DImode, operands[1]);
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operands[2] = gen_highpart (DImode, operands[2]);
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return \"sub %4,%5,%3\;sub,db,tsv %1,%2,%0\";
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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if (INTVAL (operands[1]) >= 0)
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return \"subi %1,%R2,%R0\;sub,db,tsv %%r0,%2,%0\";
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else
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return \"ldi -1,%0\;subi %1,%R2,%R0\;sub,db,tsv %0,%2,%0\";
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}
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else
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return \"sub %R1,%R2,%R0\;sub,db,tsv %1,%2,%0\";
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}"
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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[(set_attr "type" "multi,multi")
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(set (attr "length")
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(if_then_else (eq_attr "alternative" "0")
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(const_int 8)
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(if_then_else (ge (symbol_ref "INTVAL (operands[1])")
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(const_int 0))
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(const_int 8)
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(const_int 12))))])
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;; Trap instructions.
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@ -6098,14 +6118,7 @@
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[(set (match_operand:TI 0 "register_operand" "=r")
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(neg:TI (match_operand:TI 1 "register_operand" "r")))]
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"TARGET_64BIT"
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"*
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{
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operands[2] = gen_lowpart (DImode, operands[0]);
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operands[3] = gen_lowpart (DImode, operands[1]);
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operands[0] = gen_highpart (DImode, operands[0]);
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operands[1] = gen_highpart (DImode, operands[1]);
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return \"sub %%r0,%3,%2\;sub,db %%r0,%1,%0\";
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}"
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"sub %%r0,%R1,%R0\;sub,db %%r0,%1,%0"
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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@ -6147,14 +6160,7 @@
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(sign_extend:OI (neg:TI (match_dup 1))))
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(const_int 0))]
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"TARGET_64BIT"
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"*
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{
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operands[2] = gen_lowpart (DImode, operands[0]);
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operands[3] = gen_lowpart (DImode, operands[1]);
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operands[0] = gen_highpart (DImode, operands[0]);
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operands[1] = gen_highpart (DImode, operands[1]);
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return \"sub %%r0,%3,%2\;sub,db,tsv %%r0,%1,%0\";
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}"
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"sub %%r0,%R1,%R0\;sub,db,tsv %%r0,%1,%0"
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[(set_attr "type" "multi")
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(set_attr "length" "8")])
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