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AVX-512. Add convert ps2pd and ps2dq.
gcc/ * config/i386/sse.md (define_insn "<fixsuffix>fix_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>"): New. (define_insn "<fixsuffix>fix_truncv2sfv2di2<mask_name>"): Ditto. (define_insn "ufix_trunc<mode><sseintvecmodelower>2<mask_name>"): Ditto. (define_insn "sse2_cvtss2sd<round_saeonly_name>"): Change "nonimmediate_operand" to "<round_saeonly_nimm_predicate>". (define_insn "avx_cvtpd2ps256<mask_name>"): Add masking. (define_expand "sse2_cvtpd2ps_mask): New. (define_insn "*sse2_cvtpd2ps<mask_name>"): Add masking. (define_insn "sse2_cvtps2pd<mask_name>"): Add masking. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r215586
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
42815c486a
commit
1bdf255a6b
@ -1,3 +1,25 @@
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2014-09-25 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/i386/sse.md
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(define_insn
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"<fixsuffix>fix_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>"):
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New.
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(define_insn "<fixsuffix>fix_truncv2sfv2di2<mask_name>"): Ditto.
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(define_insn "ufix_trunc<mode><sseintvecmodelower>2<mask_name>"): Ditto.
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(define_insn "sse2_cvtss2sd<round_saeonly_name>"): Change
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"nonimmediate_operand" to "<round_saeonly_nimm_predicate>".
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(define_insn "avx_cvtpd2ps256<mask_name>"): Add masking.
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(define_expand "sse2_cvtpd2ps_mask): New.
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(define_insn "*sse2_cvtpd2ps<mask_name>"): Add masking.
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(define_insn "sse2_cvtps2pd<mask_name>"): Add masking.
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2014-09-25 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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@ -4659,6 +4659,38 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseintvecmode2>")])
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(define_insn "<fixsuffix>fix_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>"
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[(set (match_operand:<sselongvecmode> 0 "register_operand" "=v")
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(any_fix:<sselongvecmode>
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(match_operand:VF1_128_256VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
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"TARGET_AVX512DQ && <round_saeonly_modev8sf_condition>"
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"vcvttps2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseintvecmode3>")])
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(define_insn "<fixsuffix>fix_truncv2sfv2di2<mask_name>"
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[(set (match_operand:V2DI 0 "register_operand" "=v")
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(any_fix:V2DI
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(vec_select:V2SF
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(match_operand:V4SF 1 "nonimmediate_operand" "vm")
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(parallel [(const_int 0) (const_int 1)]))))]
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"TARGET_AVX512DQ && TARGET_AVX512VL"
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"vcvttps2<fixsuffix>qq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "TI")])
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(define_insn "ufix_trunc<mode><sseintvecmodelower>2<mask_name>"
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[(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
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(unsigned_fix:<sseintvecmode>
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(match_operand:VF1_128_256VL 1 "nonimmediate_operand" "vm")))]
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"TARGET_AVX512VL"
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"vcvttps2udq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseintvecmode2>")])
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(define_expand "avx_cvttpd2dq256_2"
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[(set (match_operand:V8SI 0 "register_operand")
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(vec_concat:V8SI
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@ -4713,7 +4745,7 @@
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(vec_merge:V2DF
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(float_extend:V2DF
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(vec_select:V2SF
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(match_operand:V4SF 2 "nonimmediate_operand" "x,m,<round_saeonly_constraint>")
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(match_operand:V4SF 2 "<round_saeonly_nimm_predicate>" "x,m,<round_saeonly_constraint>")
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(parallel [(const_int 0) (const_int 1)])))
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(match_operand:V2DF 1 "register_operand" "0,0,v")
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(const_int 1)))]
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@ -4741,14 +4773,14 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "V8SF")])
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(define_insn "avx_cvtpd2ps256"
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(define_insn "avx_cvtpd2ps256<mask_name>"
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[(set (match_operand:V4SF 0 "register_operand" "=v")
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(float_truncate:V4SF
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(match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
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"TARGET_AVX"
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"vcvtpd2ps{y}\t{%1, %0|%0, %1}"
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(match_operand:V4DF 1 "nonimmediate_operand" "vm")))]
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"TARGET_AVX && <mask_avx512vl_condition>"
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"vcvtpd2ps{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "vex")
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(set_attr "prefix" "maybe_evex")
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(set_attr "btver2_decode" "vector")
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(set_attr "mode" "V4SF")])
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@ -4761,16 +4793,28 @@
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"TARGET_SSE2"
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"operands[2] = CONST0_RTX (V2SFmode);")
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(define_insn "*sse2_cvtpd2ps"
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(define_expand "sse2_cvtpd2ps_mask"
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[(set (match_operand:V4SF 0 "register_operand")
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(vec_merge:V4SF
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(vec_concat:V4SF
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(float_truncate:V2SF
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(match_operand:V2DF 1 "nonimmediate_operand"))
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(match_dup 4))
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(match_operand:V4SF 2 "register_operand")
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(match_operand:QI 3 "register_operand")))]
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"TARGET_SSE2"
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"operands[4] = CONST0_RTX (V2SFmode);")
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(define_insn "*sse2_cvtpd2ps<mask_name>"
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[(set (match_operand:V4SF 0 "register_operand" "=v")
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(vec_concat:V4SF
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(float_truncate:V2SF
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(match_operand:V2DF 1 "nonimmediate_operand" "xm"))
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(match_operand:V2DF 1 "nonimmediate_operand" "vm"))
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(match_operand:V2SF 2 "const0_operand")))]
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"TARGET_SSE2"
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"TARGET_SSE2 && <mask_avx512vl_condition>"
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{
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if (TARGET_AVX)
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return "vcvtpd2ps{x}\t{%1, %0|%0, %1}";
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return "vcvtpd2ps{x}\t{%1, %0<mask_operand3>|%0<mask_operand3>, %1}";
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else
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return "cvtpd2ps\t{%1, %0|%0, %1}";
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}
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@ -4824,14 +4868,14 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "V8DF")])
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(define_insn "sse2_cvtps2pd"
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(define_insn "sse2_cvtps2pd<mask_name>"
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[(set (match_operand:V2DF 0 "register_operand" "=v")
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(float_extend:V2DF
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(vec_select:V2SF
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(match_operand:V4SF 1 "nonimmediate_operand" "xm")
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(match_operand:V4SF 1 "nonimmediate_operand" "vm")
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(parallel [(const_int 0) (const_int 1)]))))]
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"TARGET_SSE2"
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"%vcvtps2pd\t{%1, %0|%0, %q1}"
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"TARGET_SSE2 && <mask_avx512vl_condition>"
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"%vcvtps2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
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[(set_attr "type" "ssecvt")
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(set_attr "amdfam10_decode" "direct")
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(set_attr "athlon_decode" "double")
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