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arc: Update doloop_end patterns
ARC processor can use LP instruction to implement zero overlay loops. The current inplementation doesn't handle the unlikely situation when the loop iterator is located in memory. Refurbish the loop_end insn pattern into a define_insn_and_split pattern. gcc/ 2021-07-09 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (loop_end): Change it to define_insn_and_split. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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@ -4962,7 +4962,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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(define_expand "doloop_end"
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[(parallel [(set (pc)
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(if_then_else
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(ne (match_operand 0 "" "")
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(ne (match_operand 0 "nonimmediate_operand")
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(const_int 1))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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@ -4988,44 +4988,38 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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;; if by any chance the lp_count is not used, then use an 'r'
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;; register, instead of going to memory.
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(define_insn "loop_end"
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;; split pattern for the very slim chance when the loop register is
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;; memory.
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(define_insn_and_split "loop_end"
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[(set (pc)
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(if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,m")
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(if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,!m")
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(const_int 1))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_operand:SI 0 "nonimmediate_operand" "=r,m")
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(plus (match_dup 2) (const_int -1)))
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(unspec [(const_int 0)] UNSPEC_ARC_LP)
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(clobber (match_scratch:SI 3 "=X,&r"))]
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""
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"; ZOL_END, begins @%l1"
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[(set_attr "length" "0")
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(set_attr "predicable" "no")
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(set_attr "type" "loop_end")])
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;; split pattern for the very slim chance when the loop register is
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;; memory.
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(define_split
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[(set (pc)
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(if_then_else (ne (match_operand:SI 0 "memory_operand")
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(const_int 1))
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(label_ref (match_operand 1 ""))
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(pc)))
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(set (match_dup 0) (plus (match_dup 0) (const_int -1)))
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(unspec [(const_int 0)] UNSPEC_ARC_LP)
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(clobber (match_scratch:SI 2))]
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"memory_operand (operands[0], SImode)"
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(clobber (match_scratch:SI 2 "=X,&r"))]
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""
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"@
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; ZOL_END, begins @%l1
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#"
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"reload_completed && memory_operand (operands[0], Pmode)"
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[(set (match_dup 2) (match_dup 0))
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(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
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(parallel
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[(set (reg:CC_ZN CC_REG)
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(compare:CC_ZN (plus:SI (match_dup 2) (const_int -1))
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(const_int 0)))
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(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))])
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(set (match_dup 0) (match_dup 2))
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(set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))
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(set (pc)
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(if_then_else (ne (reg:CC CC_REG)
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(if_then_else (ne (reg:CC_ZN CC_REG)
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(const_int 0))
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(label_ref (match_dup 1))
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(pc)))]
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"")
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""
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[(set_attr "length" "0,24")
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(set_attr "predicable" "no")
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(set_attr "type" "loop_end")])
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(define_insn "loop_fail"
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[(set (reg:SI LP_COUNT)
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