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target.h (htm_available): Determine vendor from __get_cpuid_max return.
* config/x86/target.h (htm_available): Determine vendor from __get_cpuid_max return. Use signature_INTEL_ebx. Cleanup. From-SVN: r244644
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@ -1,3 +1,8 @@
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2017-01-19 Uros Bizjak <ubizjak@gmail.com>
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* config/x86/target.h (htm_available): Determine vendor from
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__get_cpuid_max return. Use signature_INTEL_ebx. Cleanup.
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2017-01-18 Torvald Riegel <triegel@redhat.com>
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* config/x86/target.h (htm_available): Add check for some processors
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@ -75,31 +75,32 @@ static inline bool
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htm_available ()
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{
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const unsigned cpuid_rtm = bit_RTM;
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if (__get_cpuid_max (0, NULL) >= 7)
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unsigned vendor;
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if (__get_cpuid_max (0, &vendor) >= 7)
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{
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unsigned a, b, c, d;
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/* TSX is broken on some processors. This can be fixed by microcode,
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unsigned family;
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__cpuid (1, a, b, c, d);
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family = (a >> 8) & 0x0f;
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/* TSX is broken on some processors. TSX can be disabled by microcode,
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but we cannot reliably detect whether the microcode has been
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updated. Therefore, do not report availability of TSX on these
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processors. We use the same approach here as in glibc (see
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https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html). */
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__cpuid (0, a, b, c, d);
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if (b == 0x756e6547 && c == 0x6c65746e && d == 0x49656e69)
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if (vendor == signature_INTEL_ebx && family == 0x06)
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{
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__cpuid (1, a, b, c, d);
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if (((a >> 8) & 0x0f) == 0x06) // Family.
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{
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unsigned model = ((a >> 4) & 0x0f) // Model.
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+ ((a >> 12) & 0xf0); // Extended model.
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unsigned stepping = a & 0x0f;
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if ((model == 0x3c)
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|| (model == 0x45)
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|| (model == 0x46)
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/* Xeon E7 v3 has correct TSX if stepping >= 4. */
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|| ((model == 0x3f) && (stepping < 4)))
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return false;
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}
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unsigned model = ((a >> 4) & 0x0f) + ((a >> 12) & 0xf0);
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unsigned stepping = a & 0x0f;
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if (model == 0x3c
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/* Xeon E7 v3 has correct TSX if stepping >= 4. */
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|| (model == 0x3f && stepping < 4)
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|| model == 0x45
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|| model == 0x46)
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return false;
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}
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__cpuid_count (7, 0, a, b, c, d);
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if (b & cpuid_rtm)
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return true;
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