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ia64.h (enum reg_class): Remove FR_INT_REGS, FR_FP_REGS, GR_AND_FR_INT_REGS, GR_AND_FR_FP_REGS.
* config/ia64/ia64.h (enum reg_class): Remove FR_INT_REGS, FR_FP_REGS,
GR_AND_FR_INT_REGS, GR_AND_FR_FP_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(FR_FP_REGNO_P, FR_INT_REGNO_P): Remove.
(HARD_REGNO_MODE_OK): Remove references to them.
(REGNO_REG_CLASS): Likewise.
(REG_CLASS_FROM_LETTER): Likewise.
(CLASS_MAX_NREGS): Likewise.
(REGISTER_MOVE_COST): Likewise.
* config/ia64/ia64.c (ia64_secondary_reload_class): Likewise.
* config/ia64/ia64.md (*): Replace "e" constraints with "f".
(movqi_internal): Special case moves from zero.
(movhi_internal, movsi_internal): Likewise.
(movdi_internal): Likewise. Fill out "f" constraints.
(movsf_internal): Fill out "r" constraints.
(movdf_internal): Likewise.
From-SVN: r34530
This commit is contained in:
Richard Henderson
Richard Henderson
parent
ef3843807e
commit
13da91fd23
@ -1,3 +1,23 @@
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2000-06-13 Richard Henderson <rth@cygnus.com>
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* config/ia64/ia64.h (enum reg_class): Remove FR_INT_REGS, FR_FP_REGS,
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GR_AND_FR_INT_REGS, GR_AND_FR_FP_REGS.
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(REG_CLASS_NAMES): Likewise.
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(REG_CLASS_CONTENTS): Likewise.
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(FR_FP_REGNO_P, FR_INT_REGNO_P): Remove.
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(HARD_REGNO_MODE_OK): Remove references to them.
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(REGNO_REG_CLASS): Likewise.
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(REG_CLASS_FROM_LETTER): Likewise.
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(CLASS_MAX_NREGS): Likewise.
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(REGISTER_MOVE_COST): Likewise.
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* config/ia64/ia64.c (ia64_secondary_reload_class): Likewise.
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* config/ia64/ia64.md (*): Replace "e" constraints with "f".
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(movqi_internal): Special case moves from zero.
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(movhi_internal, movsi_internal): Likewise.
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(movdi_internal): Likewise. Fill out "f" constraints.
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(movsf_internal): Fill out "r" constraints.
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(movdf_internal): Likewise.
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2000-06-13 Richard Henderson <rth@cygnus.com>
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* flow.c (insn_dead_p): Keep sets to PIC_OFFSET_TABLE_REGNUM
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@ -1969,7 +1969,7 @@ ia64_secondary_reload_class (class, mode, x)
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because paradoxical subregs are not accepted by register_operand when
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INSN_SCHEDULING is defined. Or alternatively, stop the paradoxical subreg
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stupidity in the *_operand functions in recog.c. */
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if ((class == FR_REGS || class == FR_INT_REGS || class == FR_FP_REGS)
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if (class == FR_REGS
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&& GET_CODE (x) == MEM
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&& (GET_MODE (x) == SImode || GET_MODE (x) == HImode
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|| GET_MODE (x) == QImode))
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@ -1978,15 +1978,7 @@ ia64_secondary_reload_class (class, mode, x)
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/* This can happen because of the ior/and/etc patterns that accept FP
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registers as operands. If the third operand is a constant, then it
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needs to be reloaded into a FP register. */
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if ((class == FR_REGS || class == FR_INT_REGS || class == FR_FP_REGS)
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&& GET_CODE (x) == CONST_INT)
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return GR_REGS;
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/* Moving a integer from an FP register to memory requires a general register
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as an intermediary. This is not necessary if we are moving a DImode
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subreg of a DFmode value from an FP register to memory, since stfd will
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do the right thing in this case. */
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if (class == FR_INT_REGS && GET_CODE (x) == MEM && GET_MODE (x) == DImode)
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if (class == FR_REGS && GET_CODE (x) == CONST_INT)
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return GR_REGS;
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/* ??? This happens if we cse/gcse a CCmode value across a call, and the
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@ -545,10 +545,6 @@ while (0)
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/* Ranges for the various kinds of registers. */
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#define ADDL_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 3)
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#define GR_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 127)
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#define FR_FP_REGNO_P(REGNO) \
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(((REGNO) >= 128 && (REGNO) <= 143) || ((REGNO) >= 152 && (REGNO) <= 223))
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#define FR_INT_REGNO_P(REGNO) \
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(((REGNO) >= 144 && (REGNO) <= 151) || ((REGNO) >= 224 && (REGNO) <= 255))
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#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
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#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
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#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
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@ -816,10 +812,7 @@ while (0)
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that one). */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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(FR_FP_REGNO_P (REGNO) ? ! INTEGRAL_MODE_P (MODE) \
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: FR_INT_REGNO_P (REGNO) ? ! FLOAT_MODE_P (MODE) \
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: PR_REGNO_P (REGNO) ? (MODE) == CCmode \
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: 1)
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(PR_REGNO_P (REGNO) ? (MODE) == CCmode : 1)
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/* A C expression that is nonzero if it is desirable to choose register
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allocation so as to avoid move instructions between a value of mode MODE1
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@ -861,11 +854,6 @@ while (0)
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register class, followed by one more enumeral value, `LIM_REG_CLASSES',
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which is not a register class but rather tells how many classes there
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are. */
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/* ??? FP registers hold INT and FP values in different representations, so
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we can't just use a subreg to convert between the two. We get around this
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problem by segmenting the FP register set into two parts. One part (FR_INT)
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only holds integer values, and one part (FR_FP) only hold FP values. Thus
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we always know which representation is being used. */
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/* ??? When compiling without optimization, it is possible for the only use of
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a pseudo to be a parameter load from the stack with a REG_EQUIV note.
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Regclass handles this case specially and does not assign any costs to the
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@ -879,11 +867,7 @@ enum reg_class
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BR_REGS,
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ADDL_REGS,
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GR_REGS,
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FR_INT_REGS,
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FR_FP_REGS,
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FR_REGS,
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GR_AND_FR_INT_REGS,
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GR_AND_FR_FP_REGS,
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GR_AND_FR_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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@ -897,9 +881,8 @@ enum reg_class
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/* An initializer containing the names of the register classes as C string
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constants. These names are used in writing some of the debugging dumps. */
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", "FR_INT_REGS", \
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"FR_FP_REGS", "FR_REGS", "GR_AND_FR_INT_REGS", "GR_AND_FR_FP_REGS", \
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"GR_AND_FR_REGS", "ALL_REGS" }
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{ "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", \
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"FR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
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/* An initializer containing the contents of the register classes, as integers
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which are bit masks. The Nth integer specifies the contents of class N.
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@ -927,26 +910,10 @@ enum reg_class
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x300 }, \
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/* FR_INT_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00FF0000, 0x00000000, 0x00000000, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x000 }, \
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/* FR_FP_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0xFF00FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, \
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0x00000000, 0x00000000, 0x000 }, \
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/* FR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x000 }, \
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/* GR_AND_FR_INT_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00FF0000, 0x00000000, 0x00000000, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x300 }, \
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/* GR_AND_FR_FP_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0xFF00FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, \
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0x00000000, 0x00000000, 0x300 }, \
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/* GR_AND_FR_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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@ -966,8 +933,7 @@ enum reg_class
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#define REGNO_REG_CLASS(REGNO) \
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(ADDL_REGNO_P (REGNO) ? ADDL_REGS \
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: GENERAL_REGNO_P (REGNO) ? GR_REGS \
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: FR_FP_REGNO_P (REGNO) ? FR_FP_REGS \
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: FR_INT_REGNO_P (REGNO) ? FR_INT_REGS \
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: FR_REGNO_P (REGNO) ? FR_REGS \
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: PR_REGNO_P (REGNO) ? PR_REGS \
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: BR_REGNO_P (REGNO) ? BR_REGS \
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: NO_REGS)
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@ -990,8 +956,7 @@ enum reg_class
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will not be passed to this macro; you do not need to handle it. */
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#define REG_CLASS_FROM_LETTER(CHAR) \
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((CHAR) == 'f' ? FR_FP_REGS \
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: (CHAR) == 'e' ? FR_INT_REGS \
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((CHAR) == 'f' ? FR_REGS \
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: (CHAR) == 'a' ? ADDL_REGS \
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: (CHAR) == 'b' ? BR_REGS \
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: (CHAR) == 'c' ? PR_REGS \
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@ -1041,9 +1006,8 @@ enum reg_class
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This is closely related to the macro `HARD_REGNO_NREGS'. */
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((MODE) == CCmode && (CLASS) == PR_REGS ? 2 \
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: (((CLASS) == FR_REGS || (CLASS) == FR_FP_REGS \
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|| (CLASS) == FR_INT_REGS) && (MODE) == XFmode) ? 1 \
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((MODE) == CCmode && (CLASS) == PR_REGS ? 2 \
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: ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
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: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* If defined, gives a class of registers that cannot be used as the
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@ -1160,6 +1124,7 @@ enum reg_class
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or a `MEM' representing a location in the stack. This enables DWARF2
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unwind info for C++ EH. */
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#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
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/* ??? This is not defined because of three problems.
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1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
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The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
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@ -1925,8 +1890,6 @@ do { \
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((FROM) == BR_REGS && (TO) == BR_REGS ? 8 \
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: (((FROM) == BR_REGS && (TO) != GENERAL_REGS) \
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|| ((TO) == BR_REGS && (FROM) != GENERAL_REGS)) ? 6 \
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: (((FROM) == FR_FP_REGS && (TO) == FR_INT_REGS) \
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|| ((FROM) == FR_INT_REGS && (TO) == FR_FP_REGS)) ? 4 \
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: 2)
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/* A C expression for the cost of moving data of mode M between a register and
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@ -177,18 +177,19 @@
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}")
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(define_insn "*movqi_internal"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,r,*e")
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(match_operand:QI 1 "move_operand" "r,J,m,r,*e,r"))]
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
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(match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
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"! memory_operand (operands[0], QImode)
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|| ! memory_operand (operands[1], QImode)"
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"@
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mov %0 = %1
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mov %0 = %r1
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addl %0 = %1, r0
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ld1%O1 %0 = %1%P1
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st1%Q0 %0 = %1%P0
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st1%Q0 %0 = %r1%P0
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getf.sig %0 = %1
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setf.sig %0 = %1"
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[(set_attr "type" "A,A,M,M,M,M")])
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setf.sig %0 = %r1
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mov %0 = %1"
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[(set_attr "type" "A,A,M,M,M,M,F")])
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(define_expand "movhi"
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[(set (match_operand:HI 0 "general_operand" "")
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@ -203,18 +204,19 @@
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}")
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(define_insn "*movhi_internal"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r,*e")
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(match_operand:HI 1 "move_operand" "r,J,m,r,*e,r"))]
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
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(match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
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"! memory_operand (operands[0], HImode)
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|| !memory_operand (operands[1], HImode)"
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"@
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mov %0 = %1
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mov %0 = %r1
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addl %0 = %1, r0
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ld2%O1 %0 = %1%P1
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st2%Q0 %0 = %1%P0
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st2%Q0 %0 = %r1%P0
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getf.sig %0 = %1
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setf.sig %0 = %1"
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[(set_attr "type" "A,A,M,M,M,M")])
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setf.sig %0 = %r1
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mov %0 = %1"
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[(set_attr "type" "A,A,M,M,M,M,F")])
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(define_expand "movsi"
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[(set (match_operand:SI 0 "general_operand" "")
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@ -229,22 +231,20 @@
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}")
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(define_insn "*movsi_internal"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,r,*e,*e,r,*f")
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(match_operand:SI 1 "move_operand" "r,J,i,m,r,*e,r,*e,*f,r"))]
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f")
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(match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f"))]
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"! memory_operand (operands[0], SImode)
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|| ! memory_operand (operands[1], SImode)"
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"@
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mov %0 = %1
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mov %0 = %r1
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addl %0 = %1, r0
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movl %0 = %1
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ld4%O1 %0 = %1%P1
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st4%Q0 %0 = %1%P0
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st4%Q0 %0 = %r1%P0
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getf.sig %0 = %1
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setf.sig %0 = %1
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mov %0 = %1
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getf.s %0 = %1
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setf.s %0 = %1"
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[(set_attr "type" "A,A,L,M,M,M,M,F,M,M")])
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setf.sig %0 = %r1
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mov %0 = %1"
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[(set_attr "type" "A,A,L,M,M,M,M,F")])
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(define_expand "movdi"
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[(set (match_operand:DI 0 "general_operand" "")
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@ -287,25 +287,24 @@
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operands[1] = copy_to_mode_reg (DImode, operands[1]);
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}")
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;; ??? Emit stf8 for m/*e constraint.
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(define_insn "*movdi_internal"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,r,*e,*e,r,*f,r,*b")
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(match_operand:DI 1 "move_operand" "r,J,i,m,r,*e,r,*e,*f,r,*b,r"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f,*f, m, r,*b")
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(match_operand:DI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f, m,*f,*b,rO"))]
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"! memory_operand (operands[0], DImode)
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|| ! memory_operand (operands[1], DImode)"
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"@
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mov %0 = %1
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mov %0 = %r1
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addl %0 = %1, r0
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movl %0 = %1
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ld8%O1 %0 = %1%P1
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st8%Q0 %0 = %1%P0
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st8%Q0 %0 = %r1%P0
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getf.sig %0 = %1
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setf.sig %0 = %1
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setf.sig %0 = %r1
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mov %0 = %1
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getf.d %0 = %1
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setf.d %0 = %1
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ldf8%O1 %0 = %1%P1
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stf8%Q0 %0 = %1%P0
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mov %0 = %1
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mov %0 = %1"
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mov %0 = %r1"
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[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I")])
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(define_expand "load_fptr"
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@ -392,12 +391,9 @@
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operands[1] = copy_to_mode_reg (SFmode, operands[1]);
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}")
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;; ??? The r/m alternative is apparently needed because of paradoxical subregs,
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;; so it may no longer be necessary after scheduling is enabled.
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(define_insn "*movsf_internal"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,*r,f,*r,*r")
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(match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r,m"))]
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
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(match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
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"! memory_operand (operands[0], SFmode)
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|| ! memory_operand (operands[1], SFmode)"
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"@
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@ -407,8 +403,9 @@
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getf.s %0 = %F1
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setf.s %0 = %1
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mov %0 = %1
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ld4%O1 %0 = %1"
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[(set_attr "type" "F,M,M,M,M,A,M")])
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ld4%O1 %0 = %1%P1
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st4%Q0 %0 = %1%P0"
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[(set_attr "type" "F,M,M,M,M,A,M,M")])
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(define_expand "movdf"
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[(set (match_operand:DF 0 "general_operand" "")
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||||
@ -422,11 +419,9 @@
|
||||
operands[1] = copy_to_mode_reg (DFmode, operands[1]);
|
||||
}")
|
||||
|
||||
;; ??? movsf has a r/m alternative, movdf doesn't.
|
||||
|
||||
(define_insn "*movdf_internal"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,*r,f,*r")
|
||||
(match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r"))]
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
|
||||
(match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
|
||||
"! memory_operand (operands[0], DFmode)
|
||||
|| ! memory_operand (operands[1], DFmode)"
|
||||
"@
|
||||
@ -435,8 +430,10 @@
|
||||
stfd %0 = %F1%P0
|
||||
getf.d %0 = %F1
|
||||
setf.d %0 = %1
|
||||
mov %0 = %1"
|
||||
[(set_attr "type" "F,M,M,M,M,A")])
|
||||
mov %0 = %1
|
||||
ld8%O1 %0 = %1%P1
|
||||
st8%Q0 %0 = %1%P0"
|
||||
[(set_attr "type" "F,M,M,M,M,A,M,M")])
|
||||
|
||||
(define_expand "movxf"
|
||||
[(set (match_operand:XF 0 "general_operand" "")
|
||||
@ -451,8 +448,8 @@
|
||||
}")
|
||||
|
||||
(define_insn "*movxf_internal"
|
||||
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,m")
|
||||
(match_operand:XF 1 "general_operand" "fG,m,fG"))]
|
||||
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f, m")
|
||||
(match_operand:XF 1 "general_operand" "fG,m,fG"))]
|
||||
"! memory_operand (operands[0], XFmode)
|
||||
|| ! memory_operand (operands[1], XFmode)"
|
||||
"@
|
||||
@ -485,8 +482,8 @@
|
||||
[(set_attr "type" "I")])
|
||||
|
||||
(define_insn "extendsidi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*e")
|
||||
(sign_extend:DI (match_operand:SI 1 "register_operand" "r,*e")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*f")
|
||||
(sign_extend:DI (match_operand:SI 1 "register_operand" "r,*f")))]
|
||||
""
|
||||
"@
|
||||
sxt4 %0 = %1
|
||||
@ -514,8 +511,8 @@
|
||||
[(set_attr "type" "I,M")])
|
||||
|
||||
(define_insn "zero_extendsidi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,r,*e")
|
||||
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*e")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,r,*f")
|
||||
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
|
||||
""
|
||||
"@
|
||||
zxt4 %0 = %1
|
||||
@ -565,20 +562,20 @@
|
||||
|
||||
(define_insn "floatdixf2"
|
||||
[(set (match_operand:XF 0 "register_operand" "=f")
|
||||
(float:XF (match_operand:DI 1 "register_operand" "e")))]
|
||||
(float:XF (match_operand:DI 1 "register_operand" "f")))]
|
||||
""
|
||||
"fcvt.xf %0 = %1"
|
||||
[(set_attr "type" "F")])
|
||||
|
||||
(define_insn "fix_truncsfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(fix:DI (match_operand:SF 1 "register_operand" "f")))]
|
||||
""
|
||||
"fcvt.fx.trunc %0 = %1%B0"
|
||||
[(set_attr "type" "F")])
|
||||
|
||||
(define_insn "fix_truncdfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(fix:DI (match_operand:DF 1 "register_operand" "f")))]
|
||||
""
|
||||
"fcvt.fx.trunc %0 = %1%B0"
|
||||
@ -588,27 +585,27 @@
|
||||
|
||||
(define_insn "floatunsdisf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(unsigned_float:SF (match_operand:DI 1 "register_operand" "e")))]
|
||||
(unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
|
||||
""
|
||||
"fcvt.xuf.s %0 = %1%B0"
|
||||
[(set_attr "type" "F")])
|
||||
|
||||
(define_insn "floatunsdidf2"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(unsigned_float:DF (match_operand:DI 1 "register_operand" "e")))]
|
||||
(unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
|
||||
""
|
||||
"fcvt.xuf.d %0 = %1%B0"
|
||||
[(set_attr "type" "F")])
|
||||
|
||||
(define_insn "fixuns_truncsfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
|
||||
""
|
||||
"fcvt.fxu.trunc %0 = %1%B0"
|
||||
[(set_attr "type" "F")])
|
||||
|
||||
(define_insn "fixuns_truncdfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
|
||||
""
|
||||
"fcvt.fxu.trunc %0 = %1%B0"
|
||||
@ -920,9 +917,9 @@
|
||||
;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
|
||||
|
||||
(define_insn "*mulsi3_internal"
|
||||
[(set (match_operand:SI 0 "register_operand" "=e")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "e")
|
||||
(match_operand:SI 2 "nonmemory_operand" "e")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=f")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "f")
|
||||
(match_operand:SI 2 "nonmemory_operand" "f")))]
|
||||
""
|
||||
"xma.l %0 = %1, %2, f0%B0"
|
||||
[(set_attr "type" "F")])
|
||||
@ -1065,9 +1062,9 @@
|
||||
[(set_attr "type" "A")])
|
||||
|
||||
(define_insn "muldi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
(mult:DI (match_operand:DI 1 "register_operand" "e")
|
||||
(match_operand:DI 2 "register_operand" "e")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(mult:DI (match_operand:DI 1 "register_operand" "f")
|
||||
(match_operand:DI 2 "register_operand" "f")))]
|
||||
""
|
||||
"xma.l %0 = %1, %2, f0%B0"
|
||||
[(set_attr "type" "F")])
|
||||
@ -1084,10 +1081,10 @@
|
||||
;; ??? Maybe we should change how adds are canonicalized.
|
||||
|
||||
(define_insn "*madddi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "e")
|
||||
(match_operand:DI 2 "register_operand" "e"))
|
||||
(match_operand:DI 3 "register_operand" "e")))
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
|
||||
(match_operand:DI 2 "register_operand" "f"))
|
||||
(match_operand:DI 3 "register_operand" "f")))
|
||||
(clobber (match_scratch:DI 4 "=X"))]
|
||||
""
|
||||
"xma.l %0 = %1, %2, %3%B0"
|
||||
@ -1103,11 +1100,11 @@
|
||||
|
||||
(define_insn "*madddi3_elim"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&r")
|
||||
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "e")
|
||||
(match_operand:DI 2 "register_operand" "e"))
|
||||
(match_operand:DI 3 "register_operand" "e"))
|
||||
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
|
||||
(match_operand:DI 2 "register_operand" "f"))
|
||||
(match_operand:DI 3 "register_operand" "f"))
|
||||
(match_operand:DI 4 "nonmemory_operand" "rI")))
|
||||
(clobber (match_scratch:DI 5 "=e"))]
|
||||
(clobber (match_scratch:DI 5 "=f"))]
|
||||
"reload_in_progress"
|
||||
"#"
|
||||
[(set_attr "type" "unknown")])
|
||||
@ -1136,22 +1133,22 @@
|
||||
;; to generate them.
|
||||
|
||||
(define_insn "smuldi3_highpart"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "e"))
|
||||
(sign_extend:TI (match_operand:DI 2 "register_operand" "e")))
|
||||
(mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "f"))
|
||||
(sign_extend:TI (match_operand:DI 2 "register_operand" "f")))
|
||||
(const_int 64))))]
|
||||
""
|
||||
"xma.h %0 = %1, %2, f0%B0"
|
||||
[(set_attr "type" "F")])
|
||||
|
||||
(define_insn "umuldi3_highpart"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
[(set (match_operand:DI 0 "register_operand" "=f")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "e"))
|
||||
(zero_extend:TI (match_operand:DI 2 "register_operand" "e")))
|
||||
(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "f"))
|
||||
(zero_extend:TI (match_operand:DI 2 "register_operand" "f")))
|
||||
(const_int 64))))]
|
||||
""
|
||||
"xma.hu %0 = %1, %2, f0%B0"
|
||||
@ -1735,9 +1732,9 @@
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
(define_insn "anddi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*e")
|
||||
(and:DI (match_operand:DI 1 "register_operand" "%r,*e")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*f")
|
||||
(and:DI (match_operand:DI 1 "register_operand" "%r,*f")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
|
||||
""
|
||||
"@
|
||||
and %0 = %2, %1
|
||||
@ -1745,9 +1742,9 @@
|
||||
[(set_attr "type" "A,F")])
|
||||
|
||||
(define_insn "*andnot"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*e")
|
||||
(and:DI (not:DI (match_operand:DI 1 "register_operand" "r,*e"))
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*f")
|
||||
(and:DI (not:DI (match_operand:DI 1 "register_operand" "r,*f"))
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
|
||||
""
|
||||
"@
|
||||
andcm %0 = %2, %1
|
||||
@ -1755,9 +1752,9 @@
|
||||
[(set_attr "type" "A,F")])
|
||||
|
||||
(define_insn "iordi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*e")
|
||||
(ior:DI (match_operand:DI 1 "register_operand" "%r,*e")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*f")
|
||||
(ior:DI (match_operand:DI 1 "register_operand" "%r,*f")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
|
||||
""
|
||||
"@
|
||||
or %0 = %2, %1
|
||||
@ -1765,9 +1762,9 @@
|
||||
[(set_attr "type" "A,F")])
|
||||
|
||||
(define_insn "xordi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*e")
|
||||
(xor:DI (match_operand:DI 1 "register_operand" "%r,*e")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,*f")
|
||||
(xor:DI (match_operand:DI 1 "register_operand" "%r,*f")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
|
||||
""
|
||||
"@
|
||||
xor %0 = %2, %1
|
||||
@ -3000,7 +2997,7 @@
|
||||
(return)
|
||||
(pc)))]
|
||||
"ia64_direct_return ()"
|
||||
"(%%J0) br.ret%+.many rp"
|
||||
"(%J0) br.ret%+.many rp"
|
||||
[(set_attr "type" "B")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
@ -3012,7 +3009,7 @@
|
||||
(pc)
|
||||
(return)))]
|
||||
"ia64_direct_return ()"
|
||||
"(%%j0) br.ret%+.many rp"
|
||||
"(%j0) br.ret%+.many rp"
|
||||
[(set_attr "type" "B")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
@ -3132,13 +3129,13 @@
|
||||
|
||||
(define_insn "fr_spill"
|
||||
[(set (match_operand:XF 0 "memory_operand" "=m")
|
||||
(unspec:XF [(match_operand:XF 1 "register_operand" "f*e")] 3))]
|
||||
(unspec:XF [(match_operand:XF 1 "register_operand" "f")] 3))]
|
||||
""
|
||||
"stf.spill %0 = %1%P0"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "fr_restore"
|
||||
[(set (match_operand:XF 0 "register_operand" "=f*e")
|
||||
[(set (match_operand:XF 0 "register_operand" "=f")
|
||||
(unspec:XF [(match_operand:XF 1 "memory_operand" "m")] 4))]
|
||||
""
|
||||
"ldf.fill %0 = %1%P1"
|
||||
@ -3196,28 +3193,14 @@
|
||||
[(unspec_volatile [(const_int 0)] 5)
|
||||
(use (match_operand:DI 0 "register_operand" "r"))]
|
||||
""
|
||||
"flushrs\; \
|
||||
mov r19=ar.rsc\; \
|
||||
;;\; \
|
||||
and r19=0x1c,r19\; \
|
||||
;;\; \
|
||||
mov ar.rsc=r19\; \
|
||||
;;\; \
|
||||
mov ar.bspstore=%0\; \
|
||||
;;\; \
|
||||
or r19=0x3,r19\; \
|
||||
;;\; \
|
||||
loadrs\; \
|
||||
invala\; \
|
||||
;;\; \
|
||||
mov ar.rsc=r19\;"
|
||||
"flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
|
||||
[(set_attr "type" "unknown")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "flushrs"
|
||||
[(unspec [(const_int 0)] 21)]
|
||||
""
|
||||
";; \; flushrs"
|
||||
";;\;flushrs"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
Loading…
Reference in New Issue
Block a user