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re PR target/6526 ([SH4] sdivsi3_i4 can clobber xd0/xd2)
PR target/6526 * config/sh/lib1funcs.S (sdivsi3_i4, udivsi3_i4): Do not change bits other than FPSCR.PR and FPSCR.SZ. Add SH4A implementation. PR target/6526 * gcc.target/sh/pr6526.c: New. From-SVN: r199873
This commit is contained in:
Oleg Endo
parent
3e56ed50d7
commit
0d00888247
@ -1,3 +1,8 @@
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2013-06-09 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/6526
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* gcc.target/sh/pr6526.c: New.
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2013-06-09 Jakub Jelinek <jakub@redhat.com>
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PR target/57568
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64
gcc/testsuite/gcc.target/sh/pr6526.c
Normal file
64
gcc/testsuite/gcc.target/sh/pr6526.c
Normal file
@ -0,0 +1,64 @@
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/* Check that the XF registers are not clobbered by an integer division
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that is done using double precision FPU division. */
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/* { dg-do run { target "sh*-*-*" } } */
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/* { dg-options "-O1 -mdiv=call-fp" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4*-single" "-m4*-single-only" } } */
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#include <assert.h>
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#include <stdlib.h>
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extern void __set_fpscr (int);
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void
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write_xf0 (float* f)
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{
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__asm__ __volatile__ ("frchg; fmov.s @%0,fr0; frchg" : : "r" (f) : "memory");
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}
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void
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read_xf0 (float* f)
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{
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__asm__ __volatile__ ("frchg; fmov.s fr0,@%0; frchg" : : "r" (f) : "memory");
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}
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int __attribute__ ((noinline))
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test_00 (int a, int b)
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{
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return a / b;
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}
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unsigned int __attribute__ ((noinline))
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test_01 (unsigned a, unsigned b)
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{
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return a / b;
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}
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int __attribute__ ((noinline))
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test_02 (int x)
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{
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return x & 0;
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}
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int
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main (void)
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{
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float test_value;
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int r = 0;
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/* Set FPSCR.FR to 1. */
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__set_fpscr (0x200000);
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test_value = 123;
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write_xf0 (&test_value);
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r += test_00 (40, 4);
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read_xf0 (&test_value);
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assert (test_value == 123);
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test_value = 321;
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write_xf0 (&test_value);
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r += test_01 (50, 5);
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read_xf0 (&test_value);
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assert (test_value == 321);
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return test_02 (r);
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}
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@ -1,3 +1,9 @@
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2013-06-09 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/6526
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* config/sh/lib1funcs.S (sdivsi3_i4, udivsi3_i4): Do not change bits
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other than FPSCR.PR and FPSCR.SZ. Add SH4A implementation.
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2013-06-08 Walter Lee <walt@tilera.com>
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* config/tilepro/atomic.h: Don't include stdint.h or features.h.
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@ -1003,11 +1003,17 @@ hiset: sts macl,r0 ! r0 = bb*dd
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ENDFUNC(GLOBAL(mulsi3))
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#endif
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#endif /* ! __SH5__ */
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/*------------------------------------------------------------------------------
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32 bit signed integer division that uses FPU double precision division. */
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#ifdef L_sdivsi3_i4
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.title "SH DIVIDE"
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!! 4 byte integer Divide code for the Renesas SH
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#if defined (__SH4__) || defined (__SH2A__)
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!! args in r4 and r5, result in fpul, clobber dr0, dr2
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/* This variant is used when FPSCR.PR = 1 (double precision) is the default
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setting.
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Args in r4 and r5, result in fpul, clobber dr0, dr2. */
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.global GLOBAL(sdivsi3_i4)
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HIDDEN_FUNC(GLOBAL(sdivsi3_i4))
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@ -1021,8 +1027,13 @@ GLOBAL(sdivsi3_i4):
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ftrc dr0,fpul
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ENDFUNC(GLOBAL(sdivsi3_i4))
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#elif defined (__SH2A_SINGLE__) || defined (__SH2A_SINGLE_ONLY__) || defined(__SH4_SINGLE__) || defined(__SH4_SINGLE_ONLY__) || (defined (__SH5__) && ! defined __SH4_NOFPU__)
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!! args in r4 and r5, result in fpul, clobber r2, dr0, dr2
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/* This variant is used when FPSCR.PR = 0 (sigle precision) is the default
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setting.
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Args in r4 and r5, result in fpul, clobber r2, dr0, dr2.
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For this to work, we must temporarily switch the FPU do double precision,
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but we better do not touch FPSCR.FR. See PR 6526. */
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#if ! __SH5__ || __SH5__ == 32
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#if __SH5__
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@ -1031,24 +1042,43 @@ GLOBAL(sdivsi3_i4):
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.global GLOBAL(sdivsi3_i4)
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HIDDEN_FUNC(GLOBAL(sdivsi3_i4))
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GLOBAL(sdivsi3_i4):
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sts.l fpscr,@-r15
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mov #8,r2
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swap.w r2,r2
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lds r2,fpscr
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lds r4,fpul
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float fpul,dr0
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lds r5,fpul
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float fpul,dr2
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fdiv dr2,dr0
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ftrc dr0,fpul
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#ifndef __SH4A__
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mov.l r3,@-r15
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sts fpscr,r2
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mov #8,r3
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swap.w r3,r3 // r3 = 1 << 19 (FPSCR.PR bit)
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or r2,r3
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lds r3,fpscr // Set FPSCR.PR = 1.
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lds r4,fpul
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float fpul,dr0
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lds r5,fpul
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float fpul,dr2
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fdiv dr2,dr0
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ftrc dr0,fpul
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lds r2,fpscr
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rts
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lds.l @r15+,fpscr
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mov.l @r15+,r3
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#else
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/* On SH4A we can use the fpchg instruction to flip the FPSCR.PR bit. */
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fpchg
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lds r4,fpul
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float fpul,dr0
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lds r5,fpul
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float fpul,dr2
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fdiv dr2,dr0
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ftrc dr0,fpul
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rts
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fpchg
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#endif /* __SH4A__ */
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ENDFUNC(GLOBAL(sdivsi3_i4))
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#endif /* ! __SH5__ || __SH5__ == 32 */
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#endif /* ! __SH4__ || __SH2A__ */
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#endif
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#endif /* L_sdivsi3_i4 */
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//------------------------------------------------------------------------------
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#ifdef L_sdivsi3
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/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
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sh2e/sh3e code. */
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@ -1367,54 +1397,60 @@ div0: rts
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mov #0,r0
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ENDFUNC(GLOBAL(sdivsi3))
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#endif /* ! __SHMEDIA__ */
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#endif
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#ifdef L_udivsi3_i4
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#endif /* ! __SHMEDIA__ */
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#endif /* L_sdivsi3 */
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/*------------------------------------------------------------------------------
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32 bit unsigned integer division that uses FPU double precision division. */
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#ifdef L_udivsi3_i4
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.title "SH DIVIDE"
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!! 4 byte integer Divide code for the Renesas SH
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#if defined (__SH4__) || defined (__SH2A__)
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!! args in r4 and r5, result in fpul, clobber r0, r1, r4, r5, dr0, dr2, dr4,
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!! and t bit
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/* This variant is used when FPSCR.PR = 1 (double precision) is the default
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setting.
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Args in r4 and r5, result in fpul,
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clobber r0, r1, r4, r5, dr0, dr2, dr4, and t bit */
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.global GLOBAL(udivsi3_i4)
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HIDDEN_FUNC(GLOBAL(udivsi3_i4))
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GLOBAL(udivsi3_i4):
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mov #1,r1
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cmp/hi r1,r5
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bf trivial
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rotr r1
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xor r1,r4
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lds r4,fpul
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mova L1,r0
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mov #1,r1
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cmp/hi r1,r5
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bf/s trivial
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rotr r1
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xor r1,r4
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lds r4,fpul
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mova L1,r0
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#ifdef FMOVD_WORKS
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fmov.d @r0+,dr4
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fmov.d @r0+,dr4
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#else
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fmov.s @r0+,DR40
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fmov.s @r0,DR41
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fmov.s @r0+,DR40
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fmov.s @r0,DR41
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#endif
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float fpul,dr0
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xor r1,r5
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lds r5,fpul
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float fpul,dr2
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fadd dr4,dr0
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fadd dr4,dr2
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fdiv dr2,dr0
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float fpul,dr0
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xor r1,r5
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lds r5,fpul
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float fpul,dr2
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fadd dr4,dr0
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fadd dr4,dr2
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fdiv dr2,dr0
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rts
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ftrc dr0,fpul
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ftrc dr0,fpul
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trivial:
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rts
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lds r4,fpul
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lds r4,fpul
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.align 2
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#ifdef FMOVD_WORKS
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.align 3 ! make double below 8 byte aligned.
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.align 3 // Make the double below 8 byte aligned.
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#endif
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L1:
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.double 2147483648
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ENDFUNC(GLOBAL(udivsi3_i4))
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#elif defined (__SH5__) && ! defined (__SH4_NOFPU__) && ! defined (__SH2A_NOFPU__)
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#if ! __SH5__ || __SH5__ == 32
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!! args in r4 and r5, result in fpul, clobber r20, r21, dr0, fr33
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@ -1436,57 +1472,106 @@ GLOBAL(udivsi3_i4):
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ENDFUNC(GLOBAL(udivsi3_i4))
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#endif /* ! __SH5__ || __SH5__ == 32 */
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#elif defined (__SH2A_SINGLE__) || defined (__SH2A_SINGLE_ONLY__) || defined(__SH4_SINGLE__) || defined(__SH4_SINGLE_ONLY__)
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!! args in r4 and r5, result in fpul, clobber r0, r1, r4, r5, dr0, dr2, dr4
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/* This variant is used when FPSCR.PR = 0 (sigle precision) is the default
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setting.
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Args in r4 and r5, result in fpul,
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clobber r0, r1, r4, r5, dr0, dr2, dr4.
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For this to work, we must temporarily switch the FPU do double precision,
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but we better do not touch FPSCR.FR. See PR 6526. */
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.global GLOBAL(udivsi3_i4)
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HIDDEN_FUNC(GLOBAL(udivsi3_i4))
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GLOBAL(udivsi3_i4):
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mov #1,r1
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cmp/hi r1,r5
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bf trivial
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sts.l fpscr,@-r15
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mova L1,r0
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lds.l @r0+,fpscr
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rotr r1
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xor r1,r4
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lds r4,fpul
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#ifndef __SH4A__
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mov #1,r1
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cmp/hi r1,r5
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bf/s trivial
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rotr r1 // r1 = 1 << 31
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sts.l fpscr,@-r15
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xor r1,r4
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mov.l @(0,r15),r0
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xor r1,r5
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mov.l L2,r1
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lds r4,fpul
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or r0,r1
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mova L1,r0
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lds r1,fpscr
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#ifdef FMOVD_WORKS
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fmov.d @r0+,dr4
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fmov.d @r0+,dr4
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#else
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fmov.s @r0+,DR40
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fmov.s @r0,DR41
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fmov.s @r0+,DR40
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fmov.s @r0,DR41
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#endif
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float fpul,dr0
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xor r1,r5
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lds r5,fpul
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float fpul,dr2
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fadd dr4,dr0
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fadd dr4,dr2
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fdiv dr2,dr0
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ftrc dr0,fpul
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float fpul,dr0
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lds r5,fpul
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float fpul,dr2
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fadd dr4,dr0
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fadd dr4,dr2
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fdiv dr2,dr0
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ftrc dr0,fpul
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rts
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lds.l @r15+,fpscr
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lds.l @r15+,fpscr
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#ifdef FMOVD_WORKS
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.align 3 ! make double below 8 byte aligned.
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.align 3 // Make the double below 8 byte aligned.
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#endif
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trivial:
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rts
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lds r4,fpul
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lds r4,fpul
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.align 2
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L2:
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#ifdef FMOVD_WORKS
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.long 0x180000 // FPSCR.PR = 1, FPSCR.SZ = 1
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#else
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.long 0x80000 // FPSCR.PR = 1
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#endif
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L1:
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.double 2147483648
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#else
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/* On SH4A we can use the fpchg instruction to flip the FPSCR.PR bit.
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Although on SH4A fmovd usually works, it would require either additional
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two fschg instructions or an FPSCR push + pop. It's not worth the effort
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for loading only one double constant. */
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mov #1,r1
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cmp/hi r1,r5
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bf/s trivial
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rotr r1 // r1 = 1 << 31
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fpchg
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mova L1,r0
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xor r1,r4
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fmov.s @r0+,DR40
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lds r4,fpul
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fmov.s @r0,DR41
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xor r1,r5
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float fpul,dr0
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lds r5,fpul
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float fpul,dr2
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fadd dr4,dr0
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fadd dr4,dr2
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fdiv dr2,dr0
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ftrc dr0,fpul
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rts
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fpchg
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trivial:
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rts
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lds r4,fpul
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.align 2
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L1:
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#ifndef FMOVD_WORKS
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.long 0x80000
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#else
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.long 0x180000
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#endif
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.double 2147483648
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#endif /* __SH4A__ */
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ENDFUNC(GLOBAL(udivsi3_i4))
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#endif /* ! __SH4__ */
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#endif
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#endif /* L_udivsi3_i4 */
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#ifdef L_udivsi3
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/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
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