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configure.ac: Add Visium support.

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* configure.ac: Add Visium support.
	* configure: Regenerate.
libgcc/
	* config.host: Add Visium support.
	* config/visium: New directory.
gcc/
	* config.gcc: Add Visium support.
	* configure.ac: Likewise.
	* configure: Regenerate.
	* doc/extend.texi (interrupt attribute): Add Visium.
	* doc/invoke.texi: Document Visium options.
	* doc/install.texi: Document Visium target.
	* doc/md.texi: Document Visium constraints.
	* common/config/visium: New directory.
	* config/visium: Likewise.
gcc/testsuite/
	* lib/target-supports.exp (check_profiling_available): Return 0 for
	Visium.
	(check_effective_target_tls_runtime): Likewise.
	(check_effective_target_logical_op_short_circuit): Return 1 for Visium.
	* gcc.dg/20020312-2.c: Adjust for Visium.
	* gcc.dg/tls/thr-cse-1.c: Likewise
	* gcc.dg/tree-ssa/20040204-1.c: Likewise
	* gcc.dg/tree-ssa/loop-1.c: Likewise.
	* gcc.dg/weak/typeof-2.c: Likewise.

From-SVN: r219219
This commit is contained in:
Eric Botcazou 2015-01-06 08:50:12 +00:00 committed by Eric Botcazou
parent 9bd59e280c
commit 0969ec7d5d
48 changed files with 11829 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
ChangeLog
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@ -1,3 +1,8 @@
2015-01-06 Eric Botcazou <ebotcazou@adacore.com>
* configure.ac: Add Visium support.
* configure: Regenerate.
2015-01-04 Andreas Schwab <schwab@linux-m68k.org>
* configure.ac: Use OBJCOPY for OBJCOPY_FOR_TARGET.

4
configure vendored
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@ -3317,6 +3317,10 @@ case "${target}" in
# for explicit misaligned loads.
noconfigdirs="$noconfigdirs target-libssp"
;;
visium-*-*)
# No hosted I/O support.
noconfigdirs="$noconfigdirs target-libssp"
;;
esac
# Disable libstdc++-v3 for some systems.

4
configure.ac
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@ -667,6 +667,10 @@ case "${target}" in
# for explicit misaligned loads.
noconfigdirs="$noconfigdirs target-libssp"
;;
visium-*-*)
# No hosted I/O support.
noconfigdirs="$noconfigdirs target-libssp"
;;
esac
# Disable libstdc++-v3 for some systems.

12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2015-01-06 Eric Botcazou <ebotcazou@adacore.com>
* config.gcc: Add Visium support.
* configure.ac: Likewise.
* configure: Regenerate.
* doc/extend.texi (interrupt attribute): Add Visium.
* doc/invoke.texi: Document Visium options.
* doc/install.texi: Document Visium target.
* doc/md.texi: Document Visium constraints.
* common/config/visium: New directory.
* config/visium: Likewise.
2015-01-05 Segher Boessenkool <segher@kernel.crashing.org>
* simplify-rtx.c (simplify_binary_operation_1): Handle more cases

38
gcc/common/config/visium/visium-common.c Normal file
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/* Common hooks for Visium.
Copyright (C) 2002-2015 Free Software Foundation, Inc.
Contributed by C.Nettleton,J.P.Parkes and P.Garbett.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
/* Set default optimization options. */
static const struct default_options visium_option_optimization_table[] =
{
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE visium_option_optimization_table
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

4
gcc/config.gcc
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@ -2888,6 +2888,10 @@ vax-*-openbsd*)
extra_options="${extra_options} openbsd.opt"
use_collect2=yes
;;
visium-*-elf*)
tm_file="dbxelf.h elfos.h ${tm_file} visium/elf.h newlib-stdint.h"
tmake_file="visium/t-visium visium/t-crtstuff"
;;
xstormy16-*-elf)
# For historical reasons, the target files omit the 'x'.
tm_file="dbxelf.h elfos.h newlib-stdint.h stormy16/stormy16.h"

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gcc/config/visium/constraints.md Normal file
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;; Constraint definitions for Visium.
;; Copyright (C) 2006-2015 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Register constraints
(define_register_constraint "b" "MDB"
"EAM register mdb")
(define_register_constraint "c" "MDC"
"EAM register mdc")
(define_register_constraint "f" "TARGET_FPU ? FP_REGS : NO_REGS"
"Floating point register")
(define_register_constraint "k" "SIBCALL_REGS"
"Register for sibcall optimization")
(define_register_constraint "l" "LOW_REGS"
"General register, but not r29, r30 and r31")
(define_register_constraint "t" "R1"
"Register r1")
(define_register_constraint "u" "R2"
"Register r2")
(define_register_constraint "v" "R3"
"Register r3")
;; Immediate integer operand constraints
(define_constraint "J"
"Integer constant in the range 0 .. 65535 (16-bit immediate)"
(and (match_code "const_int")
(match_test "0 <= ival && ival <= 65535")))
(define_constraint "K"
"Integer constant in the range 1 .. 31 (5-bit immediate)"
(and (match_code "const_int")
(match_test "1 <= ival && ival <= 31")))
(define_constraint "L"
"Integer constant in the range -65535 .. -1 (16-bit negative immediate)"
(and (match_code "const_int")
(match_test "-65535 <= ival && ival <= -1")))
(define_constraint "M"
"Integer constant -1"
(and (match_code "const_int")
(match_test "ival == -1")))
(define_constraint "O"
"Integer constant 0"
(and (match_code "const_int")
(match_test "ival == 0")))
(define_constraint "P"
"Integer constant 32"
(and (match_code "const_int")
(match_test "ival == 32")))
;; Immediate FP operand constraints
(define_constraint "G"
"Floating-point constant 0.0"
(and (match_code "const_double")
(match_test "op == CONST0_RTX (mode)")))

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gcc/config/visium/elf.h Normal file
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@ -0,0 +1,25 @@
/* ELF-specific defines for Visium.
Copyright (C) 2005-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Turn on DWARF-2 frame unwinding. */
#define INCOMING_FRAME_SP_OFFSET 0
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM)
#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)

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gcc/config/visium/gr5.md Normal file
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;; Scheduling description for GR5.
;; Copyright (C) 2013-2015 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; GR5 is a single-issue processor.
;; CPU execution units:
;;
;; issue Only one instruction can be issued on a given cycle.
;; There is no need to model the CPU pipeline in any
;; more detail than this.
;;
;; mem Memory Unit: all accesses to memory.
;;
;; eam Extended Arithmetic Module: multiply, divide and
;; 64-bit shifts.
;;
;; fp_slot[0|1|2|3] The 4 FIFO slots of the floating-point unit. Only
;; the instruction at slot 0 can execute, but an FP
;; instruction can issue if any of the slots is free.
(define_automaton "gr5,gr5_fpu")
(define_cpu_unit "gr5_issue" "gr5")
(define_cpu_unit "gr5_mem" "gr5")
(define_cpu_unit "gr5_eam" "gr5")
(define_cpu_unit "gr5_fp_slot0,gr5_fp_slot1,gr5_fp_slot2,gr5_fp_slot3" "gr5_fpu")
;; The CPU instructions which write to general registers and so do not totally
;; complete until they reach the store stage of the pipeline. This is not the
;; complete storage register class: mem_reg, eam_reg and fpu_reg are excluded
;; since we must keep the reservation sets non-overlapping.
(define_insn_reservation "gr5_storage_register" 1
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "imm_reg,arith,arith2,logic,call"))
"gr5_issue")
(define_insn_reservation "gr5_read_mem" 1
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "mem_reg"))
"gr5_issue + gr5_mem")
;; The latency of 2 and the reservation of gr5_mem on the second cycle ensures
;; that no reads will be scheduled on the second cycle, which would otherwise
;; stall the pipeline for 1 cycle.
(define_insn_reservation "gr5_write_mem" 2
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "reg_mem"))
"gr5_issue, gr5_mem")
;; Try to avoid the pipeline hazard of addressing off a register that has
;; not yet been stored.
(define_bypass 2 "gr5_storage_register" "gr5_read_mem" "gr5_hazard_bypass_p")
(define_bypass 2 "gr5_storage_register" "gr5_write_mem" "gr5_hazard_bypass_p")
(define_bypass 2 "gr5_read_mem" "gr5_read_mem" "gr5_hazard_bypass_p")
(define_bypass 2 "gr5_read_mem" "gr5_write_mem" "gr5_hazard_bypass_p")
;; Other CPU instructions complete by the process stage.
(define_insn_reservation "gr5_cpu_other" 1
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "abs_branch,branch,cmp,ret,rfi,dsi,nop"))
"gr5_issue")
;; EAM instructions.
(define_insn_reservation "gr5_write_eam" 1
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "reg_eam"))
"gr5_issue")
(define_reservation "gr5_issue_eam" "(gr5_issue + gr5_eam)")
(define_insn_reservation "gr5_read_eam" 1
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "eam_reg"))
"gr5_issue_eam")
;; Try to avoid the pipeline hazard of addressing off a register that has
;; not yet been stored.
(define_bypass 2 "gr5_read_eam" "gr5_read_mem" "gr5_hazard_bypass_p")
(define_bypass 2 "gr5_read_eam" "gr5_write_mem" "gr5_hazard_bypass_p")
(define_insn_reservation "gr5_shiftdi" 1
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "shiftdi"))
"gr5_issue_eam")
(define_insn_reservation "gr5_mul" 3
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "mul"))
"gr5_issue_eam, gr5_eam*2")
(define_insn_reservation "gr5_div" 34
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "div"))
"gr5_issue_eam, gr5_eam*33")
(define_insn_reservation "gr5_divd" 66
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "divd"))
"gr5_issue_eam, gr5_eam*65")
;; FPU instructions.
(define_reservation "gr5_fp_slotany" "(gr5_fp_slot0 | gr5_fp_slot1 | gr5_fp_slot2 | gr5_fp_slot3)")
(define_insn_reservation "gr5_fp_other" 1
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "fp_reg,reg_fp,fcmp"))
"gr5_issue")
(define_insn_reservation "gr5_fp_1cycle" 2
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "fmove,ftoi"))
"gr5_issue + gr5_fp_slotany, gr5_fp_slot0")
(define_insn_reservation "gr5_fp_2cycle" 3
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "itof"))
"gr5_issue + gr5_fp_slotany, gr5_fp_slot0*2")
(define_insn_reservation "gr5_fp_3cycle" 4
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "fp"))
"gr5_issue + gr5_fp_slotany, gr5_fp_slot0*3")
(define_insn_reservation "gr5_fp_30cycle" 31
(and (eq_attr "cpu" "gr5")
(eq_attr "type" "fdiv,fsqrt"))
"gr5_issue + gr5_fp_slotany, gr5_fp_slot0*30")

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;; Scheduling description for GR6.
;; Copyright (C) 2013-2015 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; GR6 is a dual-issue, superscalar, out-of-order processor.
;;
;; The GR6 pipeline has 3 major components:
;; 1. The FETCH/DECODE/DISPATCH stages, an in-order front-end,
;; 2. The PROCESS stage, which is the out-of-order core,
;; 3. The STORE stage, an in-order register storage stage.
;;
;; The front-end and the back-end (PROCESS + STORE) are connected through a set
;; of reservation stations which, among other things, serve as buffers for the
;; decoded instructions. The reservation stations are attached to a specific
;; execution unit of the PROCESS stage and the DISPATCH stage is responsible
;; for dispatching the decoded instructions to the appropriate stations. Most
;; execution units have multiple reservation stations, thus making it possible
;; to dispatch two instructions per unit on a given cycle, but only one of them
;; can be executed on the next cycle.
;;
;; Since the core executes the instructions out of order, the most important
;; consideration for performance tuning is to make sure that enough decoded
;; instructions are ready for execution in the PROCESS stage while not stalling
;; the front-end, i.e while not trying to dispatch a decoded instruction to an
;; execution unit whose reservation stations are full. Therefore, we do not
;; model the reservation stations (which is equivalent to pretending that there
;; is only one of them for each execution unit) but only the execution unit,
;; thus preserving some margin in case the unit itself stalls unexpectedly.
;; CPU execution units:
;;
;; inst[1|2] The front-end: 2 instructions can be issued on a given
;; cycle by the FETCH/DECODE/DISPATCH stages, except for
;; the Block Move instructions.
;;
;; mov Move Execution Unit: immediate moves into registers.
;;
;; alu[1|2] The 2 Arithmetic and Logic Units: other instructions
;; operating on the registers.
;;
;; bru Branch Resolution Unit: all branches.
;;
;; mem_wr Memory Write Unit: all writes to memory.
;;
;; mem_rd Memory Read Unit: all reads from memory.
;;
;; mem_eam EAM interface: reads and writes from and to the EAM
;; and reads from the FP registers.
;;
;; eam Extended Arithmetic Module: multiply, divide and
;; 64-bit shifts.
;;
;; fpcu Floating-Point Compare Unit: FP comparisons.
;;
;; fpu[1|2|3|4] The 4 Floating-Point Units: all other instructions
;; operating on the FP registers.
(define_automaton "gr6,gr6_fpu")
(define_cpu_unit "gr6_inst1, gr6_inst2" "gr6")
(define_cpu_unit "gr6_mov" "gr6")
(define_cpu_unit "gr6_alu1,gr6_alu2" "gr6")
(define_cpu_unit "gr6_bru" "gr6")
(define_cpu_unit "gr6_mem_wr,gr6_mem_rd,gr6_mem_eam" "gr6")
(define_cpu_unit "gr6_eam" "gr6")
(define_cpu_unit "gr6_fpcu" "gr6")
(define_cpu_unit "gr6_fpu1,gr6_fpu2,gr6_fpu3,gr6_fpu4" "gr6_fpu")
(define_reservation "gr6_issue" "(gr6_inst1 | gr6_inst2)")
(define_reservation "gr6_single_issue" "gr6_inst1 + gr6_inst2")
(define_insn_reservation "gr6_immediate" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "imm_reg"))
"gr6_issue + gr6_mov")
(define_insn_reservation "gr6_alu" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "arith,arith2,logic,cmp"))
"gr6_issue + (gr6_alu1 | gr6_alu2)")
(define_insn_reservation "gr6_branch" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "abs_branch,branch,call,ret,rfi"))
"gr6_issue + gr6_bru")
(define_insn_reservation "gr6_block_move" 16
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "bmi"))
"gr6_single_issue*16")
(define_insn_reservation "gr6_cpu_other" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "dsi,nop"))
"gr6_issue")
(define_insn_reservation "gr6_write_mem" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "reg_mem"))
"gr6_issue + gr6_mem_wr")
(define_insn_reservation "gr6_read_mem" 6
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "mem_reg"))
"gr6_issue + gr6_mem_rd, nothing*5")
;; EAM instructions.
(define_insn_reservation "gr6_write_eam" 2
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "reg_eam"))
"gr6_issue + gr6_mem_eam, nothing")
(define_reservation "gr6_issue_eam" "gr6_issue + gr6_mem_eam + gr6_eam")
(define_insn_reservation "gr6_read_eam" 2
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "eam_reg"))
"gr6_issue_eam, nothing")
(define_insn_reservation "gr6_shiftdi" 2
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "shiftdi"))
"gr6_issue_eam, gr6_eam")
(define_insn_reservation "gr6_mul" 3
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "mul"))
"gr6_issue_eam, gr6_eam*2")
(define_insn_reservation "gr6_div" 34
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "div"))
"gr6_issue_eam, gr6_eam*33")
(define_insn_reservation "gr6_divd" 66
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "divd"))
"gr6_issue_eam, gr6_eam*65")
;; FPU instructions.
(define_insn_reservation "gr6_read_fp" 2
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "fp_reg"))
"gr6_issue + gr6_mem_eam, nothing")
(define_insn_reservation "gr6_cmp_fp" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "fcmp"))
"gr6_issue + gr6_fpcu")
(define_insn_reservation "gr6_fp_1cycle" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "fmove,ftoi,itof"))
"gr6_issue + gr6_fpu1")
(define_insn_reservation "gr6_fp_3cycle" 3
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "fp"))
"gr6_issue + gr6_fpu2, nothing*2")
(define_insn_reservation "gr6_fp_17cycle" 17
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "fdiv,fsqrt"))
"gr6_issue + gr6_fpu3, gr6_fpu3*14, nothing*2")
(define_insn_reservation "gr6_write_fp" 1
(and (eq_attr "cpu" "gr6")
(eq_attr "type" "reg_fp"))
"gr6_issue + gr6_fpu4")

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;; Predicate definitions for Visium.
;; Copyright (C) 2005-2015 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Return true if OP is the constant 0.
(define_predicate "const0_operand"
(and (match_code "const_int,const_double")
(match_test "op == CONST0_RTX (mode)")))
;; Return true if OP is a constant in the range 1 .. 31.
(define_predicate "const_shift_operand"
(and (match_code "const_int")
(match_test "1 <= INTVAL (op) && INTVAL (op) <= 31")))
;; Return true if OP is either a register or the constant 0.
(define_predicate "reg_or_0_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "const0_operand")))
;; Return true if OP is either a register or a constant in the range 1 .. 31.
(define_predicate "reg_or_shift_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "const_shift_operand")))
;; Return true if OP is either a register or the constant 32.
(define_predicate "reg_or_32_operand"
(ior (match_operand 0 "register_operand")
(and (match_code "const_int")
(match_test "INTVAL (op) == 32"))))
;; Return true if OP is a general register.
(define_predicate "gpc_reg_operand"
(match_operand 0 "register_operand")
{
if (GET_CODE (op) == SUBREG)
{
op = SUBREG_REG (op);
if (GET_CODE (op) != REG)
return 1;
}
unsigned int regno = REGNO (op);
return (regno >= FIRST_PSEUDO_REGISTER
|| TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], regno));
})
;; Return true if OP is the MDB register.
(define_predicate "mdb_reg_operand"
(match_operand 0 "register_operand")
{
unsigned int regno = reg_or_subreg_regno (op);
return (regno == MDB_REGNUM);
})
;; Return true if OP is the MDC register.
(define_predicate "mdc_reg_operand"
(match_operand 0 "register_operand")
{
unsigned int regno = reg_or_subreg_regno (op);
return (regno == MDC_REGNUM);
})
;; Return true if OP is an rvalue which is not an EAM register.
(define_predicate "non_eam_src_operand"
(match_operand 0 "general_operand")
{
unsigned int regno = reg_or_subreg_regno (op);
return (regno != MDB_REGNUM && regno != MDC_REGNUM);
})
;; Return true if OP is an lvalue which is not an EAM register.
(define_predicate "non_eam_dst_operand"
(match_operand 0 "nonimmediate_operand")
{
unsigned int regno = reg_or_subreg_regno (op);
return (regno != MDB_REGNUM && regno != MDC_REGNUM);
})
;; Return true if OP is a floating-point register.
(define_predicate "fp_reg_operand"
(match_code "reg")
{
unsigned int regno = REGNO (op);
return (regno >= FIRST_PSEUDO_REGISTER || FP_REGISTER_P (regno));
})
;; Return true if OP is a floating-point register or the constant 0.
(define_predicate "fp_reg_or_0_operand"
(ior (match_operand 0 "fp_reg_operand")
(match_operand 0 "const0_operand")))
;; Return true if OP can be used as the second operand in a 32-bit or 64-bit
;; add or subtract instruction. Note that adding a negative constant may be
;; transformed into subtracting a positive constant, and vice versa.
(define_predicate "add_operand"
(ior (match_operand 0 "gpc_reg_operand")
(and (match_code "const_int")
(match_test ("INTVAL (op) >= -65535 && INTVAL (op) <= 65535")))))
;; Return true if OP is (or could be) outside the range 0 .. 65535, which is
;; the range of the immediate operands, but accept -1 for NOT.
(define_predicate "large_immediate_operand"
(ior (match_code "const,label_ref,symbol_ref")
(and (match_code "const_int")
(match_test ("INTVAL (op) < -1 || INTVAL (op) > 65535")))))
;; Return true if OP is a valid FP comparison operator.
(define_predicate "visium_fp_comparison_operator"
(match_code "eq,ne,ordered,unordered,unlt,unle,ungt,unge,lt,le,gt,ge"))
;; Return true if OP is a valid comparison operator for CC_BTSTmode.
(define_special_predicate "visium_btst_operator"
(match_code "eq,ne"))
;; Return true if OP is a valid comparison operator for CC_NOOVmode.
(define_special_predicate "visium_noov_operator"
(match_code "eq,ne,ge,lt"))
;; Return true if OP is a valid comparison operator for a branch. This allows
;; the use of MATCH_OPERATOR to recognize all the branch insns.
(define_predicate "visium_branch_operator"
(match_operand 0 "comparison_operator")
{
enum rtx_code code = GET_CODE (op);
/* These 2 comparison codes are not supported. */
if (code == UNEQ || code == LTGT)
return false;
enum machine_mode cc_mode = GET_MODE (XEXP (op, 0));
if (cc_mode == CC_NOOVmode)
return visium_noov_operator (op, mode);
if (cc_mode == CC_BTSTmode)
return visium_btst_operator (op, mode);
return true;
})
;; Return true if OP is a valid comparison operator for an integer cstore.
(define_predicate "visium_int_cstore_operator"
(match_code "eq,ne,ltu,gtu,leu,geu"))
;; Return true if OP is a valid comparison operator for an FP cstore.
(define_predicate "visium_fp_cstore_operator"
(match_code "lt,gt,unge,unle"))

21
gcc/config/visium/t-visium Normal file
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@ -0,0 +1,21 @@
# Multilibs for Visium.
# Copyright (C) 2012-2015 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
MULTILIB_OPTIONS = mcpu=gr6
MULTILIB_DIRNAMES = gr6

37
gcc/config/visium/visium-modes.def Normal file
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@ -0,0 +1,37 @@
/* Machine description for Visium.
Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Add any extra modes needed to represent the condition code.
On the Visium, we have a "no-overflow" mode which is used when arithmetic
instructions set the condition code. Different branches are used in this
case for some operations.
We also have a "bit-test" mode which is used when the bit-test instruction
sets the condition code.
We also have two modes to indicate that the condition code is set by the
the floating-point unit. One for comparisons which generate an exception
if the result is unordered (CCFPEmode) and one for comparisons which never
generate such an exception (CCFPmode). */
CC_MODE (CC_NOOV);
CC_MODE (CC_BTST);
CC_MODE (CCFP);
CC_MODE (CCFPE);

30
gcc/config/visium/visium-opts.h Normal file
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@ -0,0 +1,30 @@
/* Definitions for option handling for Visium.
Copyright (C) 2005-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef VISIUM_OPTS_H
#define VISIUM_OPTS_H
/* Processor type.
These must match the values for the cpu attribute in visium.md. */
enum processor_type {
PROCESSOR_GR5,
PROCESSOR_GR6
};
#endif

66
gcc/config/visium/visium-protos.h Normal file
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@ -0,0 +1,66 @@
/* Prototypes of target machine for Visium.
Copyright (C) 2002-2015 Free Software Foundation, Inc.
Contributed by C.Nettleton,J.P.Parkes and P.Garbett.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_VISIUM_PROTOS_H
#define GCC_VISIUM_PROTOS_H
extern unsigned int visium_data_alignment (tree, unsigned int);
extern void visium_init_expanders (void);
extern int visium_interrupt_function_p (void);
extern bool visium_can_use_return_insn_p (void);
extern void visium_expand_prologue (void);
extern void visium_expand_epilogue (void);
extern int visium_epilogue_uses (int);
extern void visium_profile_hook (void);
extern int visium_hard_regno_rename_ok (unsigned int, unsigned int);
extern int visium_initial_elimination_offset (int from, int to);
#ifdef RTX_CODE
extern void prepare_move_operands (rtx *, enum machine_mode);
extern bool ok_for_simple_move_operands (rtx *, enum machine_mode);
extern bool ok_for_simple_move_strict_operands (rtx *, enum machine_mode);
extern bool ok_for_simple_arith_logic_operands (rtx *, enum machine_mode);
extern void visium_initialize_trampoline (rtx, rtx, rtx);
extern int empty_delay_slot (rtx_insn *);
extern int gr5_hazard_bypass_p (rtx_insn *, rtx_insn *);
extern rtx visium_return_addr_rtx (int, rtx);
extern rtx visium_eh_return_handler_rtx (void);
extern rtx visium_dynamic_chain_address (rtx);
extern rtx visium_legitimize_reload_address (rtx, enum machine_mode, int, int,
int);
extern enum machine_mode visium_select_cc_mode (enum rtx_code, rtx, rtx);
extern void visium_split_cbranch (enum rtx_code, rtx, rtx, rtx);
extern const char *output_ubranch (rtx, rtx_insn *);
extern const char *output_cbranch (rtx, enum rtx_code, enum machine_mode, int,
rtx_insn *);
extern void notice_update_cc (rtx, rtx);
extern void print_operand (FILE *, rtx, int);
extern void print_operand_address (FILE *, rtx);
extern void split_double_move (rtx *, enum machine_mode);
extern void visium_expand_copysign (rtx *, enum machine_mode);
extern void visium_expand_int_cstore (rtx *, enum machine_mode);
extern void visium_expand_fp_cstore (rtx *, enum machine_mode);
extern void visium_split_cstore (enum rtx_code, rtx, rtx,
enum rtx_code, rtx, rtx);
extern int visium_expand_block_move (rtx *);
extern int visium_expand_block_set (rtx *);
extern unsigned int reg_or_subreg_regno (rtx);
#endif /* RTX_CODE */
#endif

4085
gcc/config/visium/visium.c Normal file
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File diff suppressed because it is too large Load Diff

1739
gcc/config/visium/visium.h Normal file
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File diff suppressed because it is too large Load Diff

2749
gcc/config/visium/visium.md Normal file
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File diff suppressed because it is too large Load Diff

82
gcc/config/visium/visium.opt Normal file
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@ -0,0 +1,82 @@
; Options for Visium.
; Copyright (C) 2005-2015 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published
; by the Free Software Foundation; either version 3, or (at your
; option) any later version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>. */
HeaderInclude
config/visium/visium-opts.h
mdebug
Target RejectNegative
Link with libc.a and libdebug.a
msim
Target RejectNegative
Link with libc.a and libsim.a
mfpu
Target Report Mask(FPU)
Use hardware FP (default)
mhard-float
Target RejectNegative Mask(FPU) MaskExists
Use hardware FP
msoft-float
Target RejectNegative InverseMask(FPU)
Do not use hardware FP
mcpu=
Target RejectNegative Joined Var(visium_cpu_and_features) Enum(visium_processor_type) Init(PROCESSOR_GR5)
Use features of and schedule code for given CPU
mtune=
Target RejectNegative Joined Var(visium_cpu) Enum(visium_processor_type) Init(PROCESSOR_GR5)
Schedule code for given CPU
Enum
Name(visium_processor_type) Type(enum processor_type)
EnumValue
Enum(visium_processor_type) String(mcm) Value(PROCESSOR_GR5)
EnumValue
Enum(visium_processor_type) String(gr5) Value(PROCESSOR_GR5)
EnumValue
Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6)
msv-mode
Target Mask(SV_MODE)
Generate code for the supervisor mode (default)
muser-mode
Target InverseMask(SV_MODE)
Generate code for the user mode
menable-trampolines
Target RejectNegative
Only retained for backward compatibility.
Mask(MCM)
; Generate code for the MCM
Mask(BMI)
; Generate the Block Move Instructions
Mask(FPU_IEEE)
; Generate code for an IEEE-compliant FPU

2
gcc/configure vendored
View File

@ -26502,7 +26502,7 @@ esac
case "$cpu_type" in
aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
| mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
| xstormy16 | xtensa)
| visium | xstormy16 | xtensa)
insn="nop"
;;
ia64 | s390)

2
gcc/configure.ac
View File

@ -4442,7 +4442,7 @@ esac
case "$cpu_type" in
aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
| mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
| xstormy16 | xtensa)
| visium | xstormy16 | xtensa)
insn="nop"
;;
ia64 | s390)

11
gcc/doc/extend.texi
View File

@ -2935,12 +2935,11 @@ least version 2.20.1), and GNU C library (at least version 2.11.1).
@item interrupt
@cindex interrupt handler functions
Use this attribute on the ARC, ARM, AVR, CR16, Epiphany, M32C, M32R/D,
m68k, MeP, MIPS, MSP430, RL78, RX and Xstormy16 ports to indicate that
the specified function is an
interrupt handler. The compiler generates function entry and exit
sequences suitable for use in an interrupt handler when this attribute
is present. With Epiphany targets it may also generate a special section with
code to initialize the interrupt vector table.
m68k, MeP, MIPS, MSP430, RL78, RX, Visium and Xstormy16 ports to indicate
that the specified function is an interrupt handler. The compiler generates
function entry and exit sequences suitable for use in an interrupt handler
when this attribute is present. With Epiphany targets it may also generate
a special section with code to initialize the interrupt vector table.
Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
and SH processors can be specified via the @code{interrupt_handler} attribute.

10
gcc/doc/install.texi
View File

@ -3349,6 +3349,8 @@ information have to.
@item
@uref{#tilepro-x-linux,,tilepro-*-linux*}
@item
@uref{#visium-x-elf, visium-*-elf}
@item
@uref{#x-x-vxworks,,*-*-vxworks*}
@item
@uref{#x86-64-x-x,,x86_64-*-*, amd64-*-*}
@ -4647,6 +4649,14 @@ port requires binutils-2.23 or newer.
The TILEPro processor running GNU/Linux. This port requires
binutils-2.22 or newer.
@html
<hr />
@end html
@anchor{visium-x-elf}
@heading visium-*-elf
CDS VISIUMcore processor.
This configuration is intended for embedded systems.
@html
<hr />
@end html

76
gcc/doc/invoke.texi
View File

@ -1064,6 +1064,10 @@ See RS/6000 and PowerPC Options.
@emph{VAX Options}
@gccoptlist{-mg -mgnu -munix}
@emph{Visium Options}
@gccoptlist{-mdebug -msim -mfpu -mno-fpu -mhard-float -msoft-float @gol
-mcpu=@var{cpu-type} -mtune=@var{cpu-type} -msv-mode -muser-mode}
@emph{VMS Options}
@gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64 @gol
-mpointer-size=@var{size}}
@ -11936,6 +11940,7 @@ platform.
* TILEPro Options::
* V850 Options::
* VAX Options::
* Visium Options::
* VMS Options::
* VxWorks Options::
* x86-64 Options::
@ -22606,6 +22611,77 @@ GNU assembler is being used.
Output code for G-format floating-point numbers instead of D-format.
@end table
@node Visium Options
@subsection Visium Options
@cindex Visium options
@table @gcctabopt
@item -mdebug
@opindex mdebug
A program which performs file I/O and is destined to run on an MCM target
should be linked with this option. It causes the libraries libc.a and
libdebug.a to be linked. The program should be run on the target under
the control of the GDB remote debugging stub.
@item -msim
@opindex msim
A program which performs file I/O and is destined to run on the simulator
should be linked with option. This causes libraries libc.a and libsim.a to
be linked.
@item -mfpu
@itemx -mhard-float
@opindex mfpu
@opindex mhard-float
Generate code containing floating-point instructions. This is the
default.
@item -mno-fpu
@itemx -msoft-float
@opindex mno-fpu
@opindex msoft-float
Generate code containing library calls for floating-point.
@option{-msoft-float} changes the calling convention in the output file;
therefore, it is only useful if you compile @emph{all} of a program with
this option. In particular, you need to compile @file{libgcc.a}, the
library that comes with GCC, with @option{-msoft-float} in order for
this to work.
@item -mcpu=@var{cpu_type}
@opindex mcpu
Set the instruction set, register set, and instruction scheduling parameters
for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
@samp{mcm}, @samp{gr5} and @samp{gr6}.
@samp{mcm} is a synonym of @samp{gr5} present for backward compatibility.
By default (unless configured otherwise), GCC generates code for the GR5
variant of the Visium architecture.
With @option{-mcpu=gr6}, GCC generates code for the GR6 variant of the Visium
architecture. The only difference from GR5 code is that the compiler will
generate block move instructions.
@item -mtune=@var{cpu_type}
@opindex mtune
Set the instruction scheduling parameters for machine type @var{cpu_type},
but do not set the instruction set or register set that the option
@option{-mcpu=@var{cpu_type}} would.
@item -msv-mode
@opindex msv-mode
Generate code for the supervisor mode, where there are no restrictions on
the access to general registers. This is the default.
@item -muser-mode
@opindex muser-mode
Generate code for the user mode, where the access to some general registers
is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this
mode; on the GR6, only registers r29 to r31 are affected.
@end table
@node VMS Options
@subsection VMS Options

50
gcc/doc/md.texi
View File

@ -3972,6 +3972,56 @@ A 2-element vector constant with identical elements.
@end table
@item Visium---@file{config/visium/constraints.md}
@table @code
@item b
EAM register @code{mdb}
@item c
EAM register @code{mdc}
@item f
Floating point register
@ifset INTERNALS
@item k
Register for sibcall optimization
@end ifset
@item l
General register, but not @code{r29}, @code{r30} and @code{r31}
@item t
Register @code{r1}
@item u
Register @code{r2}
@item v
Register @code{r3}
@item G
Floating-point constant 0.0
@item J
Integer constant in the range 0 .. 65535 (16-bit immediate)
@item K
Integer constant in the range 1 .. 31 (5-bit immediate)
@item L
Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
@item M
Integer constant @minus{}1
@item O
Integer constant 0
@item P
Integer constant 32
@end table
@item Xtensa---@file{config/xtensa/constraints.md}
@table @code
@item a

12
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,15 @@
2015-01-06 Eric Botcazou <ebotcazou@adacore.com>
* lib/target-supports.exp (check_profiling_available): Return 0 for
Visium.
(check_effective_target_tls_runtime): Likewise.
(check_effective_target_logical_op_short_circuit): Return 1 for Visium.
* gcc.dg/20020312-2.c: Adjust for Visium.
* gcc.dg/tls/thr-cse-1.c: Likewise
* gcc.dg/tree-ssa/20040204-1.c: Likewise
* gcc.dg/tree-ssa/loop-1.c: Likewise.
* gcc.dg/weak/typeof-2.c: Likewise.
2015-01-05 Radovan Obradovic <radovan.obradovic@imgtec.com>
PR rtl-optimization/64287

2
gcc/testsuite/gcc.dg/20020312-2.c
View File

@ -80,6 +80,8 @@ extern void abort (void);
/* No pic register. */
#elif defined(__vax__)
/* No pic register. */
#elif defined(__VISIUM__)
/* No pic register. */
#elif defined(__xstormy16__)
/* No pic register. */
#elif defined(__XTENSA__)

4
gcc/testsuite/gcc.dg/tls/thr-cse-1.c
View File

@ -18,11 +18,11 @@ int foo (int b, int c, int d)
return a;
}
/* { dg-final { scan-assembler-not "emutls_get_address.*emutls_get_address.*" { target { ! { "*-wrs-vxworks" "*-*-darwin8" "hppa*-*-hpux*" "spu-*-*" "i?86-*-mingw*" "x86_64-*-mingw*" } } } } } */
/* { dg-final { scan-assembler-not "emutls_get_address.*emutls_get_address.*" { target { ! { "*-wrs-vxworks" "*-*-darwin8" "hppa*-*-hpux*" "spu-*-*" "i?86-*-mingw*" "x86_64-*-mingw*" visium-*-* } } } } } */
/* { dg-final { scan-assembler-not "call\tL___emutls_get_address.stub.*call\tL___emutls_get_address.stub.*" { target "*-*-darwin8" } } } */
/* { dg-final { scan-assembler-not "(b,l|bl) __emutls_get_address.*(b,l|bl) __emutls_get_address.*" { target "hppa*-*-hpux*" } } } */
/* { dg-final { scan-assembler-not "(brsl|brasl)\t__emutls_get_address.*(brsl|brasl)\t__emutls_get_address.*" { target spu-*-* } } } */
/* { dg-final { scan-assembler-not "tls_lookup.*tls_lookup.*" { target *-wrs-vxworks } } } */
/* { dg-final { scan-assembler-not "call\t___emutls_get_address.*call\t___emutls_get_address" { target "i?86-*-mingw*" } } } */
/* { dg-final { scan-assembler-not "call\t__emutls_get_address.*call\t__emutls_get_address" { target "x86_64-*-mingw*" } } } */
/* { dg-final { scan-assembler-not "%l __emutls_get_address.*%l __emutls_get_address" { target visium-*-* } } } */

2
gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c
View File

@ -33,5 +33,5 @@ void test55 (int x, int y)
that the && should be emitted (based on BRANCH_COST). Fix this
by teaching dom to look through && and register all components
as true. */
/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* sparc*-*-* spu-*-* x86_64-*-*" } } } } */
/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* sparc*-*-* spu-*-* visium-*-* x86_64-*-*" } } } } */
/* { dg-final { cleanup-tree-dump "optimized" } } */

3
gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
View File

@ -49,7 +49,7 @@ int xxx(void)
/* CRIS keeps the address in a register. */
/* m68k sometimes puts the address in a register, depending on CPU and PIC. */
/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* } } } */
/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* } } } */
/* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */
/* { dg-final { scan-assembler-times "= foo" 5 { target ia64*-*-* } } } */
/* { dg-final { scan-assembler-times "call\[ \t\]*_foo" 5 { target i?86-*-mingw* i?86-*-cygwin* } } } */
@ -57,3 +57,4 @@ int xxx(void)
/* { dg-final { scan-assembler-times "jsr|bsrf|blink\ttr?,r18" 5 { target sh*-*-* } } } */
/* { dg-final { scan-assembler-times "Jsr \\\$r" 5 { target cris-*-* } } } */
/* { dg-final { scan-assembler-times "\[jb\]sr" 5 { target fido-*-* m68k-*-* } } } */
/* { dg-final { scan-assembler-times "bra *tr,r\[1-9\]*,r21" 5 { target visium-*-* } } } */

2
gcc/testsuite/gcc.dg/weak/typeof-2.c
View File

@ -48,4 +48,6 @@ int bar3 (int x)
// { dg-final { if [string match m68k-*-* $target_triplet ] {return} } }
// Likewise for moxie targets.
// { dg-final { if [string match moxie-*-* $target_triplet ] {return} } }
// Likewise for Visium targets.
// { dg-final { if [string match visium-*-* $target_triplet ] {return} } }
// { dg-final { scan-assembler "baz3.*baz3.*baz3.*baz3.*baz3.*baz3" } }

6
gcc/testsuite/lib/target-supports.exp
View File

@ -538,6 +538,7 @@ proc check_profiling_available { test_what } {
|| [istarget powerpc-*-elf]
|| [istarget rx-*-*]
|| [istarget tic6x-*-elf]
|| [istarget visium-*-*]
|| [istarget xstormy16-*]
|| [istarget xtensa*-*-elf]
|| [istarget *-*-rtems*]
@ -707,9 +708,9 @@ proc check_effective_target_tls_emulated {} {
# Return 1 if TLS executables can run correctly, 0 otherwise.
proc check_effective_target_tls_runtime {} {
# MSP430 runtime does not have TLS support, but just
# The runtime does not have TLS support, but just
# running the test below is insufficient to show this.
if { [istarget msp430-*-*] } {
if { [istarget msp430-*-*] || [istarget visium-*-*] } {
return 0
}
return [check_runtime tls_runtime {
@ -6085,6 +6086,7 @@ proc check_effective_target_logical_op_short_circuit {} {
|| [istarget s390*-*-*]
|| [istarget powerpc*-*-*]
|| [istarget nios2*-*-*]
|| [istarget visium-*-*]
|| [check_effective_target_arm_cortex_m] } {
return 1
}

5
libgcc/ChangeLog
View File

@ -1,3 +1,8 @@
2015-01-06 Eric Botcazou <ebotcazou@adacore.com>
* config.host: Add Visium support.
* config/visium: New directory.
2015-01-05 Jakub Jelinek <jakub@redhat.com>
Update copyright years.

4
libgcc/config.host
View File

@ -1235,6 +1235,10 @@ vax-*-netbsdelf*)
;;
vax-*-openbsd*)
;;
visium-*-elf*)
extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
tmake_file="visium/t-visium t-fdpbit"
;;
xstormy16-*-elf)
tmake_file="stormy16/t-stormy16 t-fdpbit"
;;

46
libgcc/config/visium/crti.S Normal file
View File

@ -0,0 +1,46 @@
/* crti.S for Visium.
Copyright (C) 2005-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.file "crti.o"
.ident "GNU C crti.o"
.section .init
.globl __init
.type __init,@function
__init:
subi r23,8
nop
write.l (r23),r22
write.l 1(r23),r21
move.l r22,r23
.section .fini
.globl __fini
.type __fini,@function
__fini:
subi r23,8
nop
write.l (r23),r22
write.l 1(r23),r21
move.l r22,r23

40
libgcc/config/visium/crtn.S Normal file
View File

@ -0,0 +1,40 @@
/* crtn.S for Visium.
Copyright (C) 2005-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.file "crtn.o"
.ident "GNU C crtn.o"
.section .init
move.l r23,r22
read.l r22,(r22)
read.l r21,1(r23)
bra tr,r21,r0
addi r23,8
.section .fini
move.l r23,r22
read.l r22,(r22)
read.l r21,1(r23)
bra tr,r21,r0
addi r23,8

25
libgcc/config/visium/divdi3.c Normal file
View File

@ -0,0 +1,25 @@
/* Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#define L_divdi3
#include "lib2funcs.c"

323
libgcc/config/visium/lib2funcs.c Normal file
View File

@ -0,0 +1,323 @@
/* Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "tconfig.h"
#include "tsystem.h"
#include "coretypes.h"
#include "tm.h"
#include "libgcc_tm.h"
#ifdef HAVE_GAS_HIDDEN
#define ATTRIBUTE_HIDDEN __attribute__ ((__visibility__ ("hidden")))
#else
#define ATTRIBUTE_HIDDEN
#endif
/* Work out the largest "word" size that we can deal with on this target. */
#if MIN_UNITS_PER_WORD > 4
# define LIBGCC2_MAX_UNITS_PER_WORD 8
#elif (MIN_UNITS_PER_WORD > 2 \
|| (MIN_UNITS_PER_WORD > 1 && __SIZEOF_LONG_LONG__ > 4))
# define LIBGCC2_MAX_UNITS_PER_WORD 4
#else
# define LIBGCC2_MAX_UNITS_PER_WORD MIN_UNITS_PER_WORD
#endif
/* Work out what word size we are using for this compilation.
The value can be set on the command line. */
#ifndef LIBGCC2_UNITS_PER_WORD
#define LIBGCC2_UNITS_PER_WORD LIBGCC2_MAX_UNITS_PER_WORD
#endif
#if LIBGCC2_UNITS_PER_WORD <= LIBGCC2_MAX_UNITS_PER_WORD
#include "libgcc2.h"
/* umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
word product in HIGH_PROD and LOW_PROD. */
#undef umul_ppmm
#define umul_ppmm(wh, wl, u, v) \
do { \
/* Generate multu instruction. */ \
UDWtype __t = (UDWtype)(u) * (UDWtype)(v); \
(wl) = (UWtype)__t; \
(wh) = (UWtype)(__t >> W_TYPE_SIZE); \
} while (0)
/* sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
and is lost. */
#undef sub_ddmmss
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.l %0,%2,%4\n\t" \
"subc.l %1,%3,%5" \
: "=&r" (sl), "=r" (sh) \
: "r" (al), "r" (ah), "r" (bl), "r" (bh))
/* udiv_qqrnnd(high_quotient, low_quotient, remainder, high_numerator,
low_numerator, denominator) divides a UDWtype, composed by the UWtype
HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
in QUOTIENT and the remainder in REMAINDER. */
#define udiv_qqrnnd(qh, ql, r, nh, nl, d) \
__asm__ ("writemd %3,%4\n\t" \
"divdu %5\n\t" \
"readmda %0\n\t" \
"readmdb %1\n\t" \
"readmdc %2" \
: "=r" (ql), "=r" (qh), "=r" (r) \
: "r" (nl), "r" (nh), "r" (d) \
: "mdb", "mdc")
#if (defined (L_udivdi3) || defined (L_divdi3) || \
defined (L_umoddi3) || defined (L_moddi3))
#define L_udivmoddi4
#endif
#ifdef L_udivmoddi4
#if (defined (L_udivdi3) || defined (L_divdi3) || \
defined (L_umoddi3) || defined (L_moddi3))
static inline __attribute__ ((__always_inline__))
#endif
UDWtype
__udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp)
{
const DWunion nn = {.ll = n};
const DWunion dd = {.ll = d};
DWunion rr;
UWtype d0, d1, n0, n1, n2;
UWtype q0, q1;
UWtype b, bm;
d0 = dd.s.low;
d1 = dd.s.high;
n0 = nn.s.low;
n1 = nn.s.high;
if (d1 == 0)
{
/* qq = NN / 0d */
if (d0 == 0)
d0 = 1 / d0; /* Divide intentionally by zero. */
udiv_qqrnnd (q1, q0, n0, n1, n0, d0);
/* Remainder in n0. */
if (rp != 0)
{
rr.s.low = n0;
rr.s.high = 0;
*rp = rr.ll;
}
}
else
{
if (d1 > n1)
{
/* 00 = nn / DD */
q0 = 0;
q1 = 0;
/* Remainder in n1n0. */
if (rp != 0)
{
rr.s.low = n0;
rr.s.high = n1;
*rp = rr.ll;
}
}
else
{
/* 0q = NN / dd */
count_leading_zeros (bm, d1);
if (bm == 0)
{
/* From (n1 >= d1) /\ (the most significant bit of d1 is set),
conclude (the most significant bit of n1 is set) /\ (the
quotient digit q0 = 0 or 1).
This special case is necessary, not an optimization. */
/* The condition on the next line takes advantage of that
n1 >= d1 (true due to program flow). */
if (n1 > d1 || n0 >= d0)
{
q0 = 1;
sub_ddmmss (n1, n0, n1, n0, d1, d0);
}
else
q0 = 0;
q1 = 0;
if (rp != 0)
{
rr.s.low = n0;
rr.s.high = n1;
*rp = rr.ll;
}
}
else
{
UWtype m1, m0;
/* Normalize. */
b = W_TYPE_SIZE - bm;
d1 = (d1 << bm) | (d0 >> b);
d0 = d0 << bm;
n2 = n1 >> b;
n1 = (n1 << bm) | (n0 >> b);
n0 = n0 << bm;
udiv_qqrnnd (q1, q0, n1, n2, n1, d1);
umul_ppmm (m1, m0, q0, d0);
if (m1 > n1 || (m1 == n1 && m0 > n0))
{
q0--;
sub_ddmmss (m1, m0, m1, m0, d1, d0);
}
/* Remainder in (n1n0 - m1m0) >> bm. */
if (rp != 0)
{
sub_ddmmss (n1, n0, n1, n0, m1, m0);
rr.s.low = (n1 << b) | (n0 >> bm);
rr.s.high = n1 >> bm;
*rp = rr.ll;
}
}
}
}
const DWunion ww = {{.low = q0, .high = q1}};
return ww.ll;
}
#endif
#ifdef L_divdi3
DWtype
__divdi3 (DWtype u, DWtype v)
{
Wtype c = 0;
DWunion uu = {.ll = u};
DWunion vv = {.ll = v};
DWtype w;
if (uu.s.high < 0)
c = ~c,
uu.ll = -uu.ll;
if (vv.s.high < 0)
c = ~c,
vv.ll = -vv.ll;
w = __udivmoddi4 (uu.ll, vv.ll, (UDWtype *) 0);
if (c)
w = -w;
return w;
}
#endif
#ifdef L_moddi3
DWtype
__moddi3 (DWtype u, DWtype v)
{
Wtype c = 0;
DWunion uu = {.ll = u};
DWunion vv = {.ll = v};
DWtype w;
if (uu.s.high < 0)
c = ~c,
uu.ll = -uu.ll;
if (vv.s.high < 0)
vv.ll = -vv.ll;
(void) __udivmoddi4 (uu.ll, vv.ll, (UDWtype*)&w);
if (c)
w = -w;
return w;
}
#endif
#ifdef L_umoddi3
UDWtype
__umoddi3 (UDWtype u, UDWtype v)
{
UDWtype w;
(void) __udivmoddi4 (u, v, &w);
return w;
}
#endif
#ifdef L_udivdi3
UDWtype
__udivdi3 (UDWtype n, UDWtype d)
{
return __udivmoddi4 (n, d, (UDWtype *) 0);
}
#endif
#ifdef L_set_trampoline_parity
#undef int
extern void __set_trampoline_parity (UWtype *);
static inline UWtype
parity_bit (UWtype x)
{
x ^= x << 16;
x ^= x << 8;
x ^= x << 4;
x ^= x << 2;
x ^= x << 1;
return x & ((UWtype) 1 << (W_TYPE_SIZE - 1));
}
void
__set_trampoline_parity (UWtype *addr)
{
int i;
for (i = 0; i < (TRAMPOLINE_SIZE * BITS_PER_UNIT) / W_TYPE_SIZE; i++)
addr[i] |= parity_bit (addr[i]);
}
#endif
#endif /* LIBGCC2_UNITS_PER_WORD <= MIN_UNITS_PER_WORD */

862
libgcc/config/visium/memcpy.c Normal file
View File

@ -0,0 +1,862 @@
/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This file must be kept in sync with newlib/libc/machine/visium/memcpy.c */
#include <stddef.h>
#include "memcpy.h"
#define INST_BARRIER __asm__ __volatile__ ("":::"memory");
#define MOVE_32_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
m3 = in [7]; \
out [4] = m0; \
out [5] = m1; \
out [6] = m2; \
out [7] = m3; \
INST_BARRIER \
m0 = in [8]; \
m1 = in [9]; \
m2 = in [10]; \
m3 = in [11]; \
out [8] = m0; \
out [9] = m1; \
out [10] = m2; \
out [11] = m3; \
INST_BARRIER \
m0 = in [12]; \
m1 = in [13]; \
m2 = in [14]; \
m3 = in [15]; \
out [12] = m0; \
out [13] = m1; \
out [14] = m2; \
out [15] = m3; \
INST_BARRIER \
m0 = in [16]; \
m1 = in [17]; \
m2 = in [18]; \
m3 = in [19]; \
out [16] = m0; \
out [17] = m1; \
out [18] = m2; \
out [19] = m3; \
INST_BARRIER \
m0 = in [20]; \
m1 = in [21]; \
m2 = in [22]; \
m3 = in [23]; \
out [20] = m0; \
out [21] = m1; \
out [22] = m2; \
out [23] = m3; \
INST_BARRIER \
m0 = in [24]; \
m1 = in [25]; \
m2 = in [26]; \
m3 = in [27]; \
out [24] = m0; \
out [25] = m1; \
out [26] = m2; \
out [27] = m3; \
INST_BARRIER \
m0 = in [28]; \
m1 = in [29]; \
m2 = in [30]; \
m3 = in [31]; \
out [28] = m0; \
out [29] = m1; \
out [30] = m2; \
out [31] = m3; \
INST_BARRIER \
in += 32; \
out += 32; \
} while(0)
#define MOVE_16_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
m3 = in [7]; \
out [4] = m0; \
out [5] = m1; \
out [6] = m2; \
out [7] = m3; \
INST_BARRIER \
m0 = in [8]; \
m1 = in [9]; \
m2 = in [10]; \
m3 = in [11]; \
out [8] = m0; \
out [9] = m1; \
out [10] = m2; \
out [11] = m3; \
INST_BARRIER \
m0 = in [12]; \
m1 = in [13]; \
m2 = in [14]; \
m3 = in [15]; \
out [12] = m0; \
out [13] = m1; \
out [14] = m2; \
out [15] = m3; \
INST_BARRIER \
in += 16; \
out += 16; \
} while(0)
#define MOVE_12_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
m3 = in [7]; \
out [4] = m0; \
out [5] = m1; \
out [6] = m2; \
out [7] = m3; \
INST_BARRIER \
m0 = in [8]; \
m1 = in [9]; \
m2 = in [10]; \
m3 = in [11]; \
out [8] = m0; \
out [9] = m1; \
out [10] = m2; \
out [11] = m3; \
INST_BARRIER \
in += 12; \
out += 12; \
} while(0)
#define MOVE_11_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
m3 = in [7]; \
out [4] = m0; \
out [5] = m1; \
out [6] = m2; \
out [7] = m3; \
INST_BARRIER \
m0 = in [8]; \
m1 = in [9]; \
m2 = in [10]; \
out [8] = m0; \
out [9] = m1; \
out [10] = m2; \
INST_BARRIER \
in += 11; \
out += 11; \
} while(0)
#define MOVE_10_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
m3 = in [7]; \
out [4] = m0; \
m0 = in [8]; \
out [5] = m1; \
m1 = in [9]; \
out [6] = m2; \
out [7] = m3; \
out [8] = m0; \
out [9] = m1; \
INST_BARRIER \
in += 10; \
out += 10; \
} while(0)
#define MOVE_9_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
m3 = in [7]; \
out [4] = m0; \
out [5] = m1; \
out [6] = m2; \
out [7] = m3; \
INST_BARRIER \
m0 = in [8]; \
out [8] = m0; \
in += 9; \
out += 9; \
} while(0)
#define MOVE_8_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
m3 = in [7]; \
out [4] = m0; \
out [5] = m1; \
out [6] = m2; \
out [7] = m3; \
INST_BARRIER \
in += 8; \
out += 8; \
} while(0)
#define MOVE_7_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
m0 = in [4]; \
m1 = in [5]; \
m2 = in [6]; \
out [4] = m0; \
out [5] = m1; \
out [6] = m2; \
INST_BARRIER \
in += 7; \
out += 7; \
} while(0)
#define MOVE_6_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
INST_BARRIER \
m0 = in [4]; \
out [1] = m1; \
INST_BARRIER \
m1 = in [5]; \
out [2] = m2; \
out [3] = m3; \
out [4] = m0; \
out [5] = m1; \
INST_BARRIER \
in += 6; \
out += 6; \
} while(0)
#define MOVE_5_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
INST_BARRIER \
out [0] = m0; \
m0 = in [4]; \
INST_BARRIER \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
out [4] = m0; \
INST_BARRIER \
in += 5; \
out += 5; \
} while(0)
#define MOVE_4_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
m3 = in [3]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
out [3] = m3; \
INST_BARRIER \
in += 4; \
out += 4; \
} while(0)
#define MOVE_3_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
m2 = in [2]; \
out [0] = m0; \
out [1] = m1; \
out [2] = m2; \
INST_BARRIER \
in += 3; \
out += 3; \
} while(0)
#define MOVE_2_OBJECTS(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
m1 = in [1]; \
out [0] = m0; \
out [1] = m1; \
INST_BARRIER \
in += 2; \
out += 2; \
} while(0)
#define MOVE_1_OBJECT(in,out) \
do { \
INST_BARRIER \
m0 = in [0]; \
out [0] = m0; \
INST_BARRIER \
in += 1; \
out += 1; \
} while(0)
static inline void
__int_memcpy (void *__restrict s1, const void *__restrict s2, size_t n)
{
int value = n;
int loop_var;
const int *in = s2;
int *out = s1;
int count;
int m0,m1,m2,m3;
/* This code currently give a stall for any value with a 1->2 in the low 5
bits, i.e. 1,2, 33,34 ? not acceptable! */
switch (value & 0x1f)
{
case 0:
break;
case 1:
MOVE_1_OBJECT (in, out);
break;
case 2:
MOVE_2_OBJECTS (in, out);
break;
case 3:
MOVE_3_OBJECTS (in, out);
break;
case 4:
MOVE_4_OBJECTS (in, out);
break;
case 5:
MOVE_5_OBJECTS (in, out);
break;
case 6:
MOVE_6_OBJECTS (in, out);
break;
case 7:
MOVE_7_OBJECTS (in, out);
break;
case 8:
MOVE_8_OBJECTS (in, out);
break;
case 9:
MOVE_9_OBJECTS (in, out);
break;
case 10:
MOVE_10_OBJECTS (in, out);
break;
case 11:
MOVE_11_OBJECTS (in, out);
break;
case 12:
MOVE_12_OBJECTS (in, out);
break;
case 13:
MOVE_9_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 14:
MOVE_12_OBJECTS (in, out);
MOVE_2_OBJECTS (in, out);
break;
case 15:
MOVE_11_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 16:
MOVE_16_OBJECTS (in, out);
break;
case 17:
MOVE_11_OBJECTS (in, out);
MOVE_6_OBJECTS (in, out);
break;
case 18:
MOVE_9_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
break;
case 19:
MOVE_16_OBJECTS (in, out);
MOVE_3_OBJECTS (in, out);
break;
case 20:
MOVE_16_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 21:
MOVE_16_OBJECTS (in, out);
MOVE_5_OBJECTS (in, out);
break;
case 22:
MOVE_16_OBJECTS (in, out);
MOVE_6_OBJECTS (in, out);
break;
case 23:
MOVE_16_OBJECTS (in, out);
MOVE_7_OBJECTS (in, out);
break;
case 24:
MOVE_16_OBJECTS (in, out);
MOVE_8_OBJECTS (in, out);
break;
case 25:
MOVE_16_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
break;
case 26:
MOVE_16_OBJECTS (in, out);
MOVE_10_OBJECTS (in, out);
break;
case 27:
MOVE_16_OBJECTS (in, out);
MOVE_11_OBJECTS (in, out);
break;
case 28:
MOVE_16_OBJECTS (in, out);
MOVE_8_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 29:
MOVE_16_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 30:
MOVE_16_OBJECTS (in, out);
MOVE_12_OBJECTS (in, out);
MOVE_2_OBJECTS (in, out);
break;
case 31:
MOVE_16_OBJECTS (in, out);
MOVE_11_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
}
/* This loop governs the asmptoptic behaviour of this algorithm, for long
word copies. */
count = value >> 5;
for (loop_var = 0; loop_var < count; loop_var++)
MOVE_32_OBJECTS (in, out);
}
static inline void
__shrt_int_memcpy (void *__restrict s1, const void *__restrict s2, size_t n)
{
int value = n;
int loop_var;
const short int *in = s2;
int short *out = s1;
int count;
int m0,m1,m2,m3;
/* This code currently give a stall for any value with a 1->2 in the low 5
bits, i.e. 1,2, 33,34 ? not acceptable! */
switch (value & 0x1f)
{
case 0:
break;
case 1:
MOVE_1_OBJECT (in, out);
break;
case 2:
MOVE_2_OBJECTS (in, out);
break;
case 3:
MOVE_3_OBJECTS (in, out);
break;
case 4:
MOVE_4_OBJECTS (in, out);
break;
case 5:
MOVE_5_OBJECTS (in, out);
break;
case 6:
MOVE_6_OBJECTS (in, out);
break;
case 7:
MOVE_7_OBJECTS (in, out);
break;
case 8:
MOVE_8_OBJECTS (in, out);
break;
case 9:
MOVE_9_OBJECTS (in, out);
break;
case 10:
MOVE_10_OBJECTS (in, out);
break;
case 11:
MOVE_11_OBJECTS (in, out);
break;
case 12:
MOVE_12_OBJECTS (in, out);
break;
case 13:
MOVE_9_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 14:
MOVE_12_OBJECTS (in, out);
MOVE_2_OBJECTS (in, out);
break;
case 15:
MOVE_11_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 16:
MOVE_16_OBJECTS (in, out);
break;
case 17:
MOVE_11_OBJECTS (in, out);
MOVE_6_OBJECTS (in, out);
break;
case 18:
MOVE_9_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
break;
case 19:
MOVE_16_OBJECTS (in, out);
MOVE_3_OBJECTS (in, out);
break;
case 20:
MOVE_16_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 21:
MOVE_16_OBJECTS (in, out);
MOVE_5_OBJECTS (in, out);
break;
case 22:
MOVE_16_OBJECTS (in, out);
MOVE_6_OBJECTS (in, out);
break;
case 23:
MOVE_16_OBJECTS (in, out);
MOVE_7_OBJECTS (in, out);
break;
case 24:
MOVE_16_OBJECTS (in, out);
MOVE_8_OBJECTS (in, out);
break;
case 25:
MOVE_16_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
break;
case 26:
MOVE_16_OBJECTS (in, out);
MOVE_10_OBJECTS (in, out);
break;
case 27:
MOVE_16_OBJECTS (in, out);
MOVE_11_OBJECTS (in, out);
break;
case 28:
MOVE_16_OBJECTS (in, out);
MOVE_8_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 29:
MOVE_16_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 30:
MOVE_16_OBJECTS (in, out);
MOVE_12_OBJECTS (in, out);
MOVE_2_OBJECTS (in, out);
break;
case 31:
MOVE_16_OBJECTS (in, out);
MOVE_11_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
}
/* This loop governs the asmptoptic behaviour of this algorithm, for long
word copies. */
count = value >> 5;
for (loop_var = 0; loop_var < count; loop_var++)
MOVE_32_OBJECTS (in, out);
}
static inline void
__byte_memcpy (void *__restrict s1, const void *__restrict s2, size_t n)
{
int value = n;
int loop_var;
const char *in = s2;
char *out = s1;
int count;
int m0,m1,m2,m3;
/* This code currently give a stall for any value with a 1->2 in the low 5
bits, i.e. 1,2, 33,34 ? not acceptable! */
switch (value & 0x1f)
{
case 0:
break;
case 1:
MOVE_1_OBJECT (in, out);
break;
case 2:
MOVE_2_OBJECTS (in, out);
break;
case 3:
MOVE_3_OBJECTS (in, out);
break;
case 4:
MOVE_4_OBJECTS (in, out);
break;
case 5:
MOVE_5_OBJECTS (in, out);
break;
case 6:
MOVE_6_OBJECTS (in, out);
break;
case 7:
MOVE_7_OBJECTS (in, out);
break;
case 8:
MOVE_8_OBJECTS (in, out);
break;
case 9:
MOVE_9_OBJECTS (in, out);
break;
case 10:
MOVE_10_OBJECTS (in, out);
break;
case 11:
MOVE_11_OBJECTS (in, out);
break;
case 12:
MOVE_12_OBJECTS (in, out);
break;
case 13:
MOVE_9_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 14:
MOVE_12_OBJECTS (in, out);
MOVE_2_OBJECTS (in, out);
break;
case 15:
MOVE_11_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 16:
MOVE_16_OBJECTS (in, out);
break;
case 17:
MOVE_11_OBJECTS (in, out);
MOVE_6_OBJECTS (in, out);
break;
case 18:
MOVE_9_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
break;
case 19:
MOVE_16_OBJECTS (in, out);
MOVE_3_OBJECTS (in, out);
break;
case 20:
MOVE_16_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 21:
MOVE_16_OBJECTS (in, out);
MOVE_5_OBJECTS (in, out);
break;
case 22:
MOVE_16_OBJECTS (in, out);
MOVE_6_OBJECTS (in, out);
break;
case 23:
MOVE_16_OBJECTS (in, out);
MOVE_7_OBJECTS (in, out);
break;
case 24:
MOVE_16_OBJECTS (in, out);
MOVE_8_OBJECTS (in, out);
break;
case 25:
MOVE_16_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
break;
case 26:
MOVE_16_OBJECTS (in, out);
MOVE_10_OBJECTS (in, out);
break;
case 27:
MOVE_16_OBJECTS (in, out);
MOVE_11_OBJECTS (in, out);
break;
case 28:
MOVE_16_OBJECTS (in, out);
MOVE_8_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 29:
MOVE_16_OBJECTS (in, out);
MOVE_9_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
case 30:
MOVE_16_OBJECTS (in, out);
MOVE_12_OBJECTS (in, out);
MOVE_2_OBJECTS (in, out);
break;
case 31:
MOVE_16_OBJECTS (in, out);
MOVE_11_OBJECTS (in, out);
MOVE_4_OBJECTS (in, out);
break;
}
/* This loop governs the asmptoptic behaviour of this algorithm, for long
word copies. */
count = value >> 5;
for (loop_var = 0; loop_var < count; loop_var++)
MOVE_32_OBJECTS (in, out);
}
/* Exposed interface. */
#ifndef __VISIUM_ARCH_BMI__
void
__long_int_memcpy (void *__restrict s1, const void *__restrict s2, size_t n)
{
__int_memcpy (s1, s2, n);
}
#endif /* !__VISIUM_ARCH_BMI__ */
void
__wrd_memcpy (void *__restrict s1, const void *__restrict s2, size_t n)
{
__shrt_int_memcpy (s1, s2, n);
}
void
__byt_memcpy (void *__restrict s1, const void *__restrict s2, size_t n)
{
__byte_memcpy (s1, s2, n);
}

33
libgcc/config/visium/memcpy.h Normal file
View File

@ -0,0 +1,33 @@
/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Specialized variants of memcpy called directly from compiled code. */
extern void
__long_int_memcpy (void *__restrict s1, const void *__restrict s2, size_t n);
extern void
__wrd_memcpy (void *__restrict s1, const void *__restrict s2, size_t n);
extern void
__byt_memcpy (void *__restrict s1, const void *__restrict s2, size_t n);

664
libgcc/config/visium/memset.c Normal file
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@ -0,0 +1,664 @@
/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This file must be kept in sync with newlib/libc/machine/visium/memset.c */
#include <stddef.h>
#include "memset.h"
#define SET_32_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out [7] = m0; \
out [8] = m0; \
out [9] = m0; \
out [10] = m0; \
out [11] = m0; \
out [12] = m0; \
out [13] = m0; \
out [14] = m0; \
out [15] = m0; \
out [16] = m0; \
out [17] = m0; \
out [18] = m0; \
out [19] = m0; \
out [20] = m0; \
out [21] = m0; \
out [22] = m0; \
out [23] = m0; \
out [24] = m0; \
out [25] = m0; \
out [26] = m0; \
out [27] = m0; \
out [28] = m0; \
out [29] = m0; \
out [30] = m0; \
out [31] = m0; \
out += 32; \
} while(0)
#define SET_16_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out [7] = m0; \
out [8] = m0; \
out [9] = m0; \
out [10] = m0; \
out [11] = m0; \
out [12] = m0; \
out [13] = m0; \
out [14] = m0; \
out [15] = m0; \
out += 16; \
} while(0)
#define SET_12_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out [7] = m0; \
out [8] = m0; \
out [9] = m0; \
out [10] = m0; \
out [11] = m0; \
out += 12; \
} while(0)
#define SET_11_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out [7] = m0; \
out [8] = m0; \
out [9] = m0; \
out [10] = m0; \
out += 11; \
} while(0)
#define SET_10_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out [7] = m0; \
out [8] = m0; \
out [9] = m0; \
out += 10; \
} while(0)
#define SET_9_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out [7] = m0; \
out [8] = m0; \
out += 9; \
} while(0)
#define SET_8_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out [7] = m0; \
out += 8; \
} while(0)
#define SET_7_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out [6] = m0; \
out += 7; \
} while(0)
#define SET_6_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out [5] = m0; \
out += 6; \
} while(0)
#define SET_5_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out [4] = m0; \
out += 5; \
} while(0)
#define SET_4_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out [3] = m0; \
out += 4; \
} while(0)
#define SET_3_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out [2] = m0; \
out += 3; \
} while(0)
#define SET_2_OBJECTS(out) \
do { \
out [0] = m0; \
out [1] = m0; \
out += 2; \
} while(0)
#define SET_1_OBJECT(out) \
do { \
out [0] = m0; \
out += 1; \
} while(0)
static inline void
__int_memset (void *__restrict s1, int val, size_t n)
{
int value = n;
int loop_var;
int *out = s1;
int count;
int m0 = val;
/* This code currently give a stall for any value with a 1->2 in the low 5
bits, i.e. 1,2, 33,34 ? not acceptable! */
switch (value & 0x1f)
{
case 0:
break;
case 1:
SET_1_OBJECT (out);
break;
case 2:
SET_2_OBJECTS (out);
break;
case 3:
SET_3_OBJECTS (out);
break;
case 4:
SET_4_OBJECTS (out);
break;
case 5:
SET_5_OBJECTS (out);
break;
case 6:
SET_6_OBJECTS (out);
break;
case 7:
SET_7_OBJECTS (out);
break;
case 8:
SET_8_OBJECTS (out);
break;
case 9:
SET_9_OBJECTS (out);
break;
case 10:
SET_10_OBJECTS (out);
break;
case 11:
SET_11_OBJECTS (out);
break;
case 12:
SET_12_OBJECTS (out);
break;
case 13:
SET_9_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 14:
SET_12_OBJECTS (out);
SET_2_OBJECTS (out);
break;
case 15:
SET_11_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 16:
SET_16_OBJECTS (out);
break;
case 17:
SET_11_OBJECTS (out);
SET_6_OBJECTS (out);
break;
case 18:
SET_9_OBJECTS (out);
SET_9_OBJECTS (out);
break;
case 19:
SET_16_OBJECTS (out);
SET_3_OBJECTS (out);
break;
case 20:
SET_16_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 21:
SET_16_OBJECTS (out);
SET_5_OBJECTS (out);
break;
case 22:
SET_16_OBJECTS (out);
SET_6_OBJECTS (out);
break;
case 23:
SET_16_OBJECTS (out);
SET_7_OBJECTS (out);
break;
case 24:
SET_16_OBJECTS (out);
SET_8_OBJECTS (out);
break;
case 25:
SET_16_OBJECTS (out);
SET_9_OBJECTS (out);
break;
case 26:
SET_16_OBJECTS (out);
SET_10_OBJECTS (out);
break;
case 27:
SET_16_OBJECTS (out);
SET_11_OBJECTS (out);
break;
case 28:
SET_16_OBJECTS (out);
SET_8_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 29:
SET_16_OBJECTS (out);
SET_9_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 30:
SET_16_OBJECTS (out);
SET_12_OBJECTS (out);
SET_2_OBJECTS (out);
break;
case 31:
SET_16_OBJECTS (out);
SET_11_OBJECTS (out);
SET_4_OBJECTS (out);
break;
}
/* This loop governs the asmptoptic behaviour of this algorithm, for long
word copies. */
count = value >> 5;
for (loop_var = 0; loop_var < count; loop_var++)
SET_32_OBJECTS (out);
}
static inline void
__short_int_memset (void *__restrict s1, int val, size_t n)
{
int value = n;
int loop_var;
int short *out = s1;
int count;
int m0 = val;
/* This code currently give a stall for any value with a 1->2 in the low 5
bits, i.e. 1,2, 33,34 ? not acceptable! */
switch (value & 0x1f)
{
case 0:
break;
case 1:
SET_1_OBJECT (out);
break;
case 2:
SET_2_OBJECTS (out);
break;
case 3:
SET_3_OBJECTS (out);
break;
case 4:
SET_4_OBJECTS (out);
break;
case 5:
SET_5_OBJECTS (out);
break;
case 6:
SET_6_OBJECTS (out);
break;
case 7:
SET_7_OBJECTS (out);
break;
case 8:
SET_8_OBJECTS (out);
break;
case 9:
SET_9_OBJECTS (out);
break;
case 10:
SET_10_OBJECTS (out);
break;
case 11:
SET_11_OBJECTS (out);
break;
case 12:
SET_12_OBJECTS (out);
break;
case 13:
SET_9_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 14:
SET_12_OBJECTS (out);
SET_2_OBJECTS (out);
break;
case 15:
SET_11_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 16:
SET_16_OBJECTS (out);
break;
case 17:
SET_11_OBJECTS (out);
SET_6_OBJECTS (out);
break;
case 18:
SET_9_OBJECTS (out);
SET_9_OBJECTS (out);
break;
case 19:
SET_16_OBJECTS (out);
SET_3_OBJECTS (out);
break;
case 20:
SET_16_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 21:
SET_16_OBJECTS (out);
SET_5_OBJECTS (out);
break;
case 22:
SET_16_OBJECTS (out);
SET_6_OBJECTS (out);
break;
case 23:
SET_16_OBJECTS (out);
SET_7_OBJECTS (out);
break;
case 24:
SET_16_OBJECTS (out);
SET_8_OBJECTS (out);
break;
case 25:
SET_16_OBJECTS (out);
SET_9_OBJECTS (out);
break;
case 26:
SET_16_OBJECTS (out);
SET_10_OBJECTS (out);
break;
case 27:
SET_16_OBJECTS (out);
SET_11_OBJECTS (out);
break;
case 28:
SET_16_OBJECTS (out);
SET_8_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 29:
SET_16_OBJECTS (out);
SET_9_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 30:
SET_16_OBJECTS (out);
SET_12_OBJECTS (out);
SET_2_OBJECTS (out);
break;
case 31:
SET_16_OBJECTS (out);
SET_11_OBJECTS (out);
SET_4_OBJECTS (out);
break;
}
/* This loop governs the asmptoptic behaviour of this algorithm, for long
word copies. */
count = value >> 5;
for (loop_var = 0; loop_var < count; loop_var++)
SET_32_OBJECTS (out);
}
static inline void
__byte_memset (void *__restrict s1, int val, size_t n)
{
int value = n;
int loop_var;
char *out = s1;
int count;
int m0 = val;
/* This code currently give a stall for any value with a 1->2 in the low 5
bits, i.e. 1,2, 33,34 ? not acceptable! */
switch (value & 0x1f)
{
case 0:
break;
case 1:
SET_1_OBJECT (out);
break;
case 2:
SET_2_OBJECTS (out);
break;
case 3:
SET_3_OBJECTS (out);
break;
case 4:
SET_4_OBJECTS (out);
break;
case 5:
SET_5_OBJECTS (out);
break;
case 6:
SET_6_OBJECTS (out);
break;
case 7:
SET_7_OBJECTS (out);
break;
case 8:
SET_8_OBJECTS (out);
break;
case 9:
SET_9_OBJECTS (out);
break;
case 10:
SET_10_OBJECTS (out);
break;
case 11:
SET_11_OBJECTS (out);
break;
case 12:
SET_12_OBJECTS (out);
break;
case 13:
SET_9_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 14:
SET_12_OBJECTS (out);
SET_2_OBJECTS (out);
break;
case 15:
SET_11_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 16:
SET_16_OBJECTS (out);
break;
case 17:
SET_11_OBJECTS (out);
SET_6_OBJECTS (out);
break;
case 18:
SET_9_OBJECTS (out);
SET_9_OBJECTS (out);
break;
case 19:
SET_16_OBJECTS (out);
SET_3_OBJECTS (out);
break;
case 20:
SET_16_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 21:
SET_16_OBJECTS (out);
SET_5_OBJECTS (out);
break;
case 22:
SET_16_OBJECTS (out);
SET_6_OBJECTS (out);
break;
case 23:
SET_16_OBJECTS (out);
SET_7_OBJECTS (out);
break;
case 24:
SET_16_OBJECTS (out);
SET_8_OBJECTS (out);
break;
case 25:
SET_16_OBJECTS (out);
SET_9_OBJECTS (out);
break;
case 26:
SET_16_OBJECTS (out);
SET_10_OBJECTS (out);
break;
case 27:
SET_16_OBJECTS (out);
SET_11_OBJECTS (out);
break;
case 28:
SET_16_OBJECTS (out);
SET_8_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 29:
SET_16_OBJECTS (out);
SET_9_OBJECTS (out);
SET_4_OBJECTS (out);
break;
case 30:
SET_16_OBJECTS (out);
SET_12_OBJECTS (out);
SET_2_OBJECTS (out);
break;
case 31:
SET_16_OBJECTS (out);
SET_11_OBJECTS (out);
SET_4_OBJECTS (out);
break;
}
/* This loop governs the asmptoptic behaviour of this algorithm, for long
word copies. */
count = value >> 5;
for (loop_var = 0; loop_var < count; loop_var++)
SET_32_OBJECTS (out);
}
/* Exposed interface. */
void
__long_int_memset (void *__restrict s, int c, size_t n)
{
int ic = (c << 24) + ((char) c << 16) + ((char) c << 8) + (char) c;
__int_memset (s, ic, n);
}
void
__wrd_memset (void *__restrict s, int c, size_t n)
{
int sc = ((c << 8) + (char) c);
__short_int_memset (s, sc, n);
}
void
__byt_memset (void *__restrict s, int c, size_t n)
{
__byte_memset (s, c, n);
}

33
libgcc/config/visium/memset.h Normal file
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@ -0,0 +1,33 @@
/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Specialized variants of memset called directly from compiled code. */
extern void
__long_int_memset (void *__restrict s, int c, size_t n);
extern void
__wrd_memset (void *__restrict s, int c, size_t n);
extern void
__byt_memset (void *__restrict s, int c, size_t n);

25
libgcc/config/visium/moddi3.c Normal file
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@ -0,0 +1,25 @@
/* Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#define L_moddi3
#include "lib2funcs.c"

25
libgcc/config/visium/set_trampoline_parity.c Normal file
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@ -0,0 +1,25 @@
/* Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#define L_set_trampoline_parity
#include "lib2funcs.c"

29
libgcc/config/visium/t-visium Normal file
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@ -0,0 +1,29 @@
# Copyright (C) 2003-2015 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
LIB2FUNCS_EXCLUDE += _divdi3 _moddi3 _udivdi3 _umoddi3 _udivmoddi4
LIB2ADD += \
$(srcdir)/config/visium/divdi3.c \
$(srcdir)/config/visium/moddi3.c \
$(srcdir)/config/visium/udivdi3.c \
$(srcdir)/config/visium/umoddi3.c \
$(srcdir)/config/visium/udivmoddi4.c \
$(srcdir)/config/visium/memcpy.c \
$(srcdir)/config/visium/memset.c \
$(srcdir)/config/visium/set_trampoline_parity.c

25
libgcc/config/visium/udivdi3.c Normal file
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@ -0,0 +1,25 @@
/* Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#define L_udivdi3
#include "lib2funcs.c"

25
libgcc/config/visium/udivmoddi4.c Normal file
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@ -0,0 +1,25 @@
/* Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#define L_udivmoddi4
#include "lib2funcs.c"

25
libgcc/config/visium/umoddi3.c Normal file
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@ -0,0 +1,25 @@
/* Copyright (C) 2014-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#define L_umoddi3
#include "lib2funcs.c"