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toplev.c (dump_file_index): Move SSA dumps just after first jump dump.
* toplev.c (dump_file_index): Move SSA dumps just after first
jump dump.
(dump_file): Corresponding changes.
(rest_of_compilation): Move SSA path to just after the first
jump pass.
* doc/gcc.texi (Passes): Update due to movement of SSA path.
* doc/invoke.texi: Update dump file #s as they were completely
out of date with reality.
From-SVN: r43704
This commit is contained in:
Jeffrey A Law
Jeff Law
parent
918a61248d
commit
0826f1d89f
@ -1,3 +1,14 @@
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Mon Jul 2 14:20:13 2001 Jeffrey A Law (law@cygnus.com)
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* toplev.c (dump_file_index): Move SSA dumps just after first
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jump dump.
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(dump_file): Corresponding changes.
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(rest_of_compilation): Move SSA path to just after the first
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jump pass.
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* doc/gcc.texi (Passes): Update due to movement of SSA path.
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* doc/invoke.texi: Update dump file #s as they were completely
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out of date with reality.
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2001-07-02 Geoffrey Keating <geoffk@redhat.com>
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* doc/tm.texi (Frame Layout): Document STACK_PUSH_CODE.
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@ -3372,6 +3372,7 @@ The option @option{-dj} causes a debugging dump of the RTL code after
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this pass is run for the first time. This dump file's name is made by
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appending @samp{.jump} to the input file name.
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@cindex register use analysis
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@item
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Register scan. This pass finds the first and last use of each
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@ -3387,20 +3388,6 @@ the second conditional test. The source code for this pass is in
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@file{jump.c}. This optimization is only performed if
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@option{-fthread-jumps} is enabled.
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@cindex common subexpression elimination
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@cindex constant propagation
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@item
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Common subexpression elimination. This pass also does constant
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propagation. Its source files are @file{cse.c}, and @file{cselib.c}.
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If constant propagation causes conditional jumps to become
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unconditional or to become no-ops, jump optimization is run again when
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CSE is finished.
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@opindex ds
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The option @option{-ds} causes a debugging dump of the RTL code after
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this pass. This dump file's name is made by appending @samp{.cse} to
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the input file name.
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@cindex SSA optimizations
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@cindex Single Static Assignment optimizations
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@opindex fssa
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@ -3435,6 +3422,21 @@ The option @option{-dX} causes a debugging dump of the RTL code after
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this pass. This dump file's name is made by appending @samp{.ssadce} to
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the input file name.
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@end itemize
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@cindex common subexpression elimination
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@cindex constant propagation
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@item
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Common subexpression elimination. This pass also does constant
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propagation. Its source files are @file{cse.c}, and @file{cselib.c}.
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If constant propagation causes conditional jumps to become
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unconditional or to become no-ops, jump optimization is run again when
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CSE is finished.
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@opindex ds
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The option @option{-ds} causes a debugging dump of the RTL code after
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this pass. This dump file's name is made by appending @samp{.cse} to
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the input file name.
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@cindex global common subexpression elimination
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@cindex constant propagation
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@cindex copy propagation
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@ -2856,101 +2856,105 @@ Here are the possible letters for use in @var{letters}, and their meanings:
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Annotate the assembler output with miscellaneous debugging information.
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@item b
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@opindex db
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Dump after computing branch probabilities, to @file{@var{file}.11.bp}.
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Dump after computing branch probabilities, to @file{@var{file}.13.bp}.
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@item B
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@opindex dB
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Dump after block reordering, to @file{@var{file}.26.bbro}.
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Dump after block reordering, to @file{@var{file}.27.bbro}.
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@item c
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@opindex dc
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Dump after instruction combination, to the file @file{@var{file}.14.combine}.
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Dump after instruction combination, to the file @file{@var{file}.15.combine}.
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@item C
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@opindex dC
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Dump after the first if conversion, to the file @file{@var{file}.15.ce}.
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Dump after the first if conversion, to the file @file{@var{file}.16.ce}.
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@item d
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@opindex dd
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Dump after delayed branch scheduling, to @file{@var{file}.29.dbr}.
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Dump after delayed branch scheduling, to @file{@var{file}.30.dbr}.
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@item D
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@opindex dD
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Dump all macro definitions, at the end of preprocessing, in addition to
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normal output.
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@item e
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@opindex de
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Dump after SSA optimizations, to @file{@var{file}.05.ssa} and
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Dump after SSA optimizations, to @file{@var{file}.04.ssa} and
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@file{@var{file}.06.ussa}.
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@item E
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@opindex dE
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Dump after the second if conversion, to @file{@var{file}.24.ce2}.
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Dump after the second if conversion, to @file{@var{file}.25.ce2}.
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@item f
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@opindex df
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Dump after life analysis, to @file{@var{file}.13.life}.
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Dump after life analysis, to @file{@var{file}.14.life}.
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@item F
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@opindex dF
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Dump after purging @code{ADDRESSOF} codes, to @file{@var{file}.04.addressof}.
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Dump after purging @code{ADDRESSOF} codes, to @file{@var{file}.08.addressof}.
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@item g
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@opindex dg
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Dump after global register allocation, to @file{@var{file}.19.greg}.
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Dump after global register allocation, to @file{@var{file}.20.greg}.
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@item h
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@opindex dh
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Dump after finalization of EH handling code, to @file{@var{file}.02.eh}.
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@item o
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@item o
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@opindex do
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Dump after post-reload CSE and other optimizations, to @file{@var{file}.20.postreload}.
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Dump after post-reload CSE and other optimizations, to @file{@var{file}.21.postreload}.
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@item G
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@opindex dG
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Dump after GCSE, to @file{@var{file}.08.gcse}.
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Dump after GCSE, to @file{@var{file}.09.gcse}.
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@item i
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@opindex di
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Dump after sibling call optimizations, to @file{@var{file}.01.sibling}.
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@item j
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@opindex dj
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Dump after the first jump optimization, to @file{@var{file}.02.jump}.
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Dump after the first jump optimization, to @file{@var{file}.03.jump}.
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@item J
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@opindex dJ
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Dump after the last jump optimization, to @file{@var{file}.27.jump2}.
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Dump after the last jump optimization, to @file{@var{file}.28.jump2}.
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@item k
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@opindex dk
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Dump after conversion from registers to stack, to @file{@var{file}.29.stack}.
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Dump after conversion from registers to stack, to @file{@var{file}.31.stack}.
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@item l
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@opindex dl
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Dump after local register allocation, to @file{@var{file}.18.lreg}.
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Dump after local register allocation, to @file{@var{file}.19.lreg}.
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@item L
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@opindex dL
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Dump after loop optimization, to @file{@var{file}.09.loop}.
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Dump after loop optimization, to @file{@var{file}.10.loop}.
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@item M
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@opindex dM
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Dump after performing the machine dependent reorganisation pass, to
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@file{@var{file}.28.mach}.
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@file{@var{file}.29.mach}.
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@item n
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@opindex dn
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Dump after register renumbering, to @file{@var{file}.23.rnreg}.
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Dump after register renumbering, to @file{@var{file}.24.rnreg}.
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@item N
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@opindex dN
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Dump after the register move pass, to @file{@var{file}.16.regmove}.
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Dump after the register move pass, to @file{@var{file}.17.regmove}.
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@item r
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@opindex dr
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Dump after RTL generation, to @file{@var{file}.00.rtl}.
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@item R
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@opindex dR
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Dump after the second instruction scheduling pass, to
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@file{@var{file}.25.sched2}.
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@file{@var{file}.26.sched2}.
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@item s
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@opindex ds
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Dump after CSE (including the jump optimization that sometimes follows
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CSE), to @file{@var{file}.03.cse}.
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CSE), to @file{@var{file}.07.cse}.
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@item S
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@opindex dS
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Dump after the first instruction scheduling pass, to
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@file{@var{file}.17.sched}.
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@file{@var{file}.18.sched}.
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@item t
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@opindex dt
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Dump after the second CSE pass (including the jump optimization that
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sometimes follows CSE), to @file{@var{file}.10.cse2}.
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sometimes follows CSE), to @file{@var{file}.11.cse2}.
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@item w
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@opindex dw
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Dump after the second flow pass, to @file{@var{file}.21.flow2}.
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Dump after the second flow pass, to @file{@var{file}.22.flow2}.
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@item X
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@opindex dX
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Dump after SSA aggressive dead code elimination, to @file{@var{file}.06.ssadce}.
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Dump after SSA aggressive dead code elimination, to @file{@var{file}.05.ssadce}.
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@item z
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@opindex dz
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Dump after the peephole pass, to @file{@var{file}.22.peephole2}.
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Dump after the peephole pass, to @file{@var{file}.23.peephole2}.
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@item a
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@opindex da
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Produce all the dumps listed above.
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115
gcc/toplev.c
115
gcc/toplev.c
@ -253,11 +253,11 @@ enum dump_file_index
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DFI_sibling,
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DFI_eh,
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DFI_jump,
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DFI_cse,
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DFI_addressof,
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DFI_ssa,
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DFI_ssa_dce,
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DFI_ussa,
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DFI_cse,
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DFI_addressof,
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DFI_gcse,
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DFI_loop,
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DFI_cse2,
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@ -299,11 +299,11 @@ struct dump_file_info dump_file[DFI_MAX] =
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{ "sibling", 'i', 0, 0, 0 },
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{ "eh", 'h', 0, 0, 0 },
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{ "jump", 'j', 0, 0, 0 },
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{ "cse", 's', 0, 0, 0 },
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{ "addressof", 'F', 0, 0, 0 },
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{ "ssa", 'e', 1, 0, 0 },
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{ "ssadce", 'X', 1, 0, 0 },
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{ "ussa", 'e', 1, 0, 0 }, /* Yes, duplicate enable switch. */
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{ "cse", 's', 0, 0, 0 },
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{ "addressof", 'F', 0, 0, 0 },
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{ "gcse", 'G', 1, 0, 0 },
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{ "loop", 'L', 1, 0, 0 },
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{ "cse2", 't', 1, 0, 0 },
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@ -2947,6 +2947,61 @@ rest_of_compilation (decl)
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goto exit_rest_of_compilation;
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}
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/* Long term, this should probably move before the jump optimizer too,
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but I didn't want to disturb the rtl_dump_and_exit and related
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stuff at this time. */
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if (optimize > 0 && flag_ssa)
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{
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/* Convert to SSA form. */
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timevar_push (TV_TO_SSA);
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open_dump_file (DFI_ssa, decl);
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find_basic_blocks (insns, max_reg_num (), rtl_dump_file);
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cleanup_cfg ();
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convert_to_ssa ();
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close_dump_file (DFI_ssa, print_rtl_with_bb, insns);
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timevar_pop (TV_TO_SSA);
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/* The SSA implementation uses basic block numbers in its phi
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nodes. Thus, changing the control-flow graph or the basic
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blocks, e.g., calling find_basic_blocks () or cleanup_cfg (),
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may cause problems. */
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if (flag_ssa_dce)
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{
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/* Remove dead code. */
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timevar_push (TV_SSA_DCE);
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open_dump_file (DFI_ssa_dce, decl);
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insns = get_insns ();
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ssa_eliminate_dead_code();
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close_dump_file (DFI_ssa_dce, print_rtl_with_bb, insns);
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timevar_pop (TV_SSA_DCE);
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}
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/* Convert from SSA form. */
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timevar_push (TV_FROM_SSA);
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open_dump_file (DFI_ussa, decl);
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convert_from_ssa ();
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/* New registers have been created. Rescan their usage. */
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reg_scan (insns, max_reg_num (), 1);
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/* Life analysis used in SSA adds log_links but these
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shouldn't be there until the flow stage, so clear
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them away. */
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clear_log_links (insns);
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close_dump_file (DFI_ussa, print_rtl_with_bb, insns);
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timevar_pop (TV_FROM_SSA);
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ggc_collect ();
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}
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timevar_push (TV_JUMP);
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if (optimize > 0)
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@ -3045,58 +3100,6 @@ rest_of_compilation (decl)
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ggc_collect ();
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if (optimize > 0 && flag_ssa)
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{
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/* Convert to SSA form. */
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timevar_push (TV_TO_SSA);
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open_dump_file (DFI_ssa, decl);
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find_basic_blocks (insns, max_reg_num (), rtl_dump_file);
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cleanup_cfg ();
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convert_to_ssa ();
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close_dump_file (DFI_ssa, print_rtl_with_bb, insns);
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timevar_pop (TV_TO_SSA);
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/* The SSA implementation uses basic block numbers in its phi
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nodes. Thus, changing the control-flow graph or the basic
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blocks, e.g., calling find_basic_blocks () or cleanup_cfg (),
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may cause problems. */
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if (flag_ssa_dce)
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{
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/* Remove dead code. */
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timevar_push (TV_SSA_DCE);
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open_dump_file (DFI_ssa_dce, decl);
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insns = get_insns ();
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ssa_eliminate_dead_code();
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close_dump_file (DFI_ssa_dce, print_rtl_with_bb, insns);
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timevar_pop (TV_SSA_DCE);
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}
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/* Convert from SSA form. */
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timevar_push (TV_FROM_SSA);
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open_dump_file (DFI_ussa, decl);
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convert_from_ssa ();
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/* New registers have been created. Rescan their usage. */
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reg_scan (insns, max_reg_num (), 1);
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/* Life analysis used in SSA adds log_links but these
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shouldn't be there until the flow stage, so clear
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them away. */
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clear_log_links (insns);
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close_dump_file (DFI_ussa, print_rtl_with_bb, insns);
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timevar_pop (TV_FROM_SSA);
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ggc_collect ();
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}
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/* Perform global cse. */
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if (optimize > 0 && flag_gcse)
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