buildroot/board/spike/riscv64
Julien Olivain dc819438f6 board/spike/riscv64/start.sh: add buildroot host dir in PATH
commit 0d0f84d200
added the missing host-dtc dependency to riscv-isa-sim.

The spike simulator calls the dtc binary at its startup. The host dtc
command needs to be in the PATH at that time.

This commit add the buildroot host binary directory into the PATH of the
start.sh helper script. It make sure spike will use the buildroot dtc
version. This commit fixes this start.sh script on host not providing
the dtc command. Since the "spike" binary is now in the PATH, the
binary name is also simplified.

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2022-01-13 20:38:49 +01:00
..
readme.txt configs/spike_riscv64: new defconfig 2022-01-11 22:58:52 +01:00
start.sh board/spike/riscv64/start.sh: add buildroot host dir in PATH 2022-01-13 20:38:49 +01:00

Linux on Spike RISC-V ISA simulator
===================================

This configuration provides a minimal working setup to run a Linux
kernel in the Spike RISC-V ISA simulator.

The Spike ISA simulator can be an interresting alternative to Qemu, in
some specific cases. For example: simulating new instructions (see [1]),
simulating riscv-openocd/gdb debug sessions (see [2], [3]), or
generating an accurate per-instruction log of execution (see
riscv-isa-sim spike -l option)...

To run Buildroot Linux in Spike, use the commands:

    make spike_riscv64_defconfig
    make
    ./board/spike/riscv64/start.sh

The boot is made with the standard RISC-V OpenSBI boot loader. In
order to keep the simulation simple, the rootfs is passed as an initrd
ramfs.

Note: at the time of this writing, Spike v1.1.0 and OpenSBI v1.0 does
not support console input emulation for 32bit RISC-V systems. A 32bit
Linux system can boot and reach the login, but it's not possible to
login. See [4].


[1].
https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction

[2].
https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-gdb

[3].
https://github.com/riscv/riscv-openocd

[4].
https://github.com/riscv-software-src/opensbi/blob/v1.0/lib/utils/sys/htif.c#L127