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Modern ARC cores (those sporting MMU of version 3 and 4) allow selection of different page sizes (4, 8 or 16 kB) during ASIC design creation. And it's important to build a toolchain with page size setting that matches hardware. Otherwise user-space applications will fail on execution due to unexpected data layout/alignment etc. [Thomas: slightly improve help text, fix indentation of help text.] Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Anton Kolesov <akolesov@synopsys.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Arnout Vandecappelle <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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Config.in | ||
Config.in.aarch64 | ||
Config.in.arc | ||
Config.in.arm | ||
Config.in.bfin | ||
Config.in.m68k | ||
Config.in.microblaze | ||
Config.in.mips | ||
Config.in.nios2 | ||
Config.in.powerpc | ||
Config.in.sh | ||
Config.in.sparc | ||
Config.in.x86 | ||
Config.in.xtensa |