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d08ccb40f5
Take the conditions currently specified in the gcc version choice. Also, the conditions explained in the commit log for78c2a9f7were not all properly applied, especially the a57-a53 combo needs gcc-6, but78c2a9f7forgot to add the condition to gcc-4.9. gcc-4.9 was excluded for cortex-a17 and a72, but the CodeSourcery external toolchain, which uses 4.8, was not excluded for those two cores. Now it is. Remove the arch condition from gcc and the external toolchains. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
613 lines
18 KiB
Plaintext
613 lines
18 KiB
Plaintext
# arm cpu features
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config BR2_ARM_CPU_HAS_NEON
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bool
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# for some cores, NEON support is optional
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config BR2_ARM_CPU_MAYBE_HAS_NEON
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bool
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# for some cores, VFPv2 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV2
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bool
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config BR2_ARM_CPU_HAS_VFPV2
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bool
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# for some cores, VFPv3 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV3
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bool
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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config BR2_ARM_CPU_HAS_VFPV3
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bool
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select BR2_ARM_CPU_HAS_VFPV2
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# for some cores, VFPv4 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV4
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bool
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select BR2_ARM_CPU_MAYBE_HAS_VFPV3
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config BR2_ARM_CPU_HAS_VFPV4
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bool
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select BR2_ARM_CPU_HAS_VFPV3
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config BR2_ARM_CPU_HAS_FP_ARMV8
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bool
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select BR2_ARM_CPU_HAS_VFPV4
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config BR2_ARM_CPU_HAS_ARM
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bool
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config BR2_ARM_CPU_HAS_THUMB
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bool
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config BR2_ARM_CPU_HAS_THUMB2
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bool
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config BR2_ARM_CPU_ARMV4
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bool
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config BR2_ARM_CPU_ARMV5
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bool
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config BR2_ARM_CPU_ARMV6
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bool
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config BR2_ARM_CPU_ARMV7A
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bool
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config BR2_ARM_CPU_ARMV7M
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bool
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config BR2_ARM_CPU_ARMV8
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bool
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choice
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prompt "Target Architecture Variant"
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default BR2_arm926t
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help
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Specific CPU variant to use
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config BR2_arm920t
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bool "arm920t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm922t
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bool "arm922t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm926t
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bool "arm926t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1136j_s
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bool "arm1136j-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1136jf_s
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bool "arm1136jf-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1176jz_s
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bool "arm1176jz-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1176jzf_s
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bool "arm1176jzf-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm11mpcore
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bool "mpcore"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a5
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bool "cortex-A5"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_MAYBE_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a7
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bool "cortex-A7"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a8
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bool "cortex-A8"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV3
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a9
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bool "cortex-A9"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_MAYBE_HAS_VFPV3
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a12
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bool "cortex-A12"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a15
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bool "cortex-A15"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a15_a7
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bool "cortex-A15/A7 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a17
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bool "cortex-A17"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a17_a7
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bool "cortex-A17/A7 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a53
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bool "cortex-A53"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a57
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bool "cortex-A57"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a57_a53
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bool "cortex-A57/A53 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_cortex_a72
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bool "cortex-A72"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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config BR2_cortex_a72_a53
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bool "cortex-A72/A53 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_cortex_m3
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bool "cortex-M3"
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7M
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_m4
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bool "cortex-M4"
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7M
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depends on !BR2_ARCH_IS_64
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config BR2_fa526
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bool "fa526/626"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_pj4
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bool "pj4"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV3
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_strongarm
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bool "strongarm sa110/sa1100"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_xscale
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bool "xscale"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_iwmmxt
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bool "iwmmxt"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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endchoice
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config BR2_ARM_ENABLE_NEON
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bool "Enable NEON SIMD extension support"
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depends on BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_HAS_NEON
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help
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For some CPU cores, the NEON SIMD extension is optional.
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Select this option if you are certain your particular
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implementation has NEON support and you want to use it.
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config BR2_ARM_ENABLE_VFP
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bool "Enable VFP extension support"
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depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
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select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
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select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
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help
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For some CPU cores, the VFP extension is optional. Select
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this option if you are certain your particular
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implementation has VFP support and you want to use it.
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choice
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prompt "Target ABI"
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depends on BR2_arm || BR2_armeb
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default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
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default BR2_ARM_EABI
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help
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Application Binary Interface to use. The Application Binary
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Interface describes the calling conventions (how arguments
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are passed to functions, how the return value is passed, how
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system calls are made, etc.).
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config BR2_ARM_EABI
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bool "EABI"
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help
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The EABI is currently the standard ARM ABI, which is used in
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most projects. It supports both the 'soft' floating point
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model (in which floating point instructions are emulated in
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software) and the 'softfp' floating point model (in which
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floating point instructions are executed using an hardware
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floating point unit, but floating point arguments to
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functions are passed in integer registers).
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The 'softfp' floating point model is link-compatible with
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the 'soft' floating point model, i.e you can link a library
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built 'soft' with some other code built 'softfp'.
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However, passing the floating point arguments in integer
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registers is a bit inefficient, so if your ARM processor has
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a floating point unit, and you don't have pre-compiled
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'soft' or 'softfp' code, using the EABIhf ABI will provide
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better floating point performances.
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If your processor does not have a floating point unit, then
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you must use this ABI.
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config BR2_ARM_EABIHF
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bool "EABIhf"
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depends on BR2_ARM_CPU_HAS_VFPV2
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help
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The EABIhf is an extension of EABI which supports the 'hard'
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floating point model. This model uses the floating point
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unit to execute floating point instructions, and passes
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floating point arguments in floating point registers.
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It is more efficient than EABI for floating point related
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workload. However, it does not allow to link against code
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that has been pre-built for the 'soft' or 'softfp' floating
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point models.
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If your processor has a floating point unit, and you don't
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depend on existing pre-compiled code, this option is most
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likely the best choice.
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endchoice
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choice
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prompt "Floating point strategy"
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default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
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default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
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default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
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default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
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default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
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config BR2_ARM_SOFT_FLOAT
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bool "Soft float"
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depends on BR2_ARM_EABI
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select BR2_SOFT_FLOAT
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help
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This option allows to use software emulated floating
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point. It should be used for ARM cores that do not include a
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Vector Floating Point unit, such as ARMv5 cores (ARM926 for
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example) or certain ARMv6 cores.
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config BR2_ARM_FPU_VFPV2
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bool "VFPv2"
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depends on BR2_ARM_CPU_HAS_VFPV2
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help
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This option allows to use the VFPv2 floating point unit, as
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available in some ARMv5 processors (ARM926EJ-S) and some
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ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
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MPCore).
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Note that this option is also safe to use for newer cores
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such as Cortex-A, because the VFPv3 and VFPv4 units are
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backward compatible with VFPv2.
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config BR2_ARM_FPU_VFPV3
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bool "VFPv3"
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depends on BR2_ARM_CPU_HAS_VFPV3
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help
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This option allows to use the VFPv3 floating point unit, as
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available in some ARMv7 processors (Cortex-A{8, 9}). This
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option requires a VFPv3 unit that has 32 double-precision
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registers, which is not necessarily the case in all SOCs
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based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
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instead, which is guaranteed to work on all Cortex-A{8, 9}.
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Note that this option is also safe to use for newer cores
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that have a VFPv4 unit, because VFPv4 is backward compatible
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with VFPv3. They must of course also have 32
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double-precision registers.
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config BR2_ARM_FPU_VFPV3D16
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bool "VFPv3-D16"
|
|
depends on BR2_ARM_CPU_HAS_VFPV3
|
|
help
|
|
This option allows to use the VFPv3 floating point unit, as
|
|
available in some ARMv7 processors (Cortex-A{8, 9}). This
|
|
option requires a VFPv3 unit that has 16 double-precision
|
|
registers, which is generally the case in all SOCs based on
|
|
Cortex-A{8, 9}, even though VFPv3 is technically optional on
|
|
Cortex-A9. This is the safest option for those cores.
|
|
|
|
Note that this option is also safe to use for newer cores
|
|
such that have a VFPv4 unit, because the VFPv4 is backward
|
|
compatible with VFPv3.
|
|
|
|
config BR2_ARM_FPU_VFPV4
|
|
bool "VFPv4"
|
|
depends on BR2_ARM_CPU_HAS_VFPV4
|
|
help
|
|
This option allows to use the VFPv4 floating point unit, as
|
|
available in some ARMv7 processors (Cortex-A{5, 7, 12,
|
|
15}). This option requires a VFPv4 unit that has 32
|
|
double-precision registers, which is not necessarily the
|
|
case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
|
|
unsure, you should probably use VFPv4-D16 instead.
|
|
|
|
Note that if you want binary code that works on all ARMv7
|
|
cores, including the earlier Cortex-A{8, 9}, you should
|
|
instead select VFPv3.
|
|
|
|
config BR2_ARM_FPU_VFPV4D16
|
|
bool "VFPv4-D16"
|
|
depends on BR2_ARM_CPU_HAS_VFPV4
|
|
help
|
|
This option allows to use the VFPv4 floating point unit, as
|
|
available in some ARMv7 processors (Cortex-A{5, 7, 12,
|
|
15}). This option requires a VFPv4 unit that has 16
|
|
double-precision registers, which is always available on
|
|
Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
|
|
Cortex-A7.
|
|
|
|
Note that if you want binary code that works on all ARMv7
|
|
cores, including the earlier Cortex-A{8, 9}, you should
|
|
instead select VFPv3-D16.
|
|
|
|
config BR2_ARM_FPU_NEON
|
|
bool "NEON"
|
|
depends on BR2_ARM_CPU_HAS_NEON
|
|
help
|
|
This option allows to use the NEON SIMD unit, as available
|
|
in some ARMv7 processors, as a floating-point unit. It
|
|
should however be noted that using NEON for floating point
|
|
operations doesn't provide a complete compatibility with the
|
|
IEEE 754.
|
|
|
|
config BR2_ARM_FPU_NEON_VFPV4
|
|
bool "NEON/VFPv4"
|
|
depends on BR2_ARM_CPU_HAS_VFPV4
|
|
depends on BR2_ARM_CPU_HAS_NEON
|
|
help
|
|
This option allows to use both the VFPv4 and the NEON SIMD
|
|
units for floating point operations. Note that some ARMv7
|
|
cores do not necessarily have VFPv4 and/or NEON support, for
|
|
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
|
|
NEON is optional.
|
|
|
|
config BR2_ARM_FPU_FP_ARMV8
|
|
bool "FP-ARMv8"
|
|
depends on BR2_ARM_CPU_HAS_FP_ARMV8
|
|
help
|
|
This option allows to use the ARMv8 floating point unit.
|
|
|
|
config BR2_ARM_FPU_NEON_FP_ARMV8
|
|
bool "NEON/FP-ARMv8"
|
|
depends on BR2_ARM_CPU_HAS_FP_ARMV8
|
|
depends on BR2_ARM_CPU_HAS_NEON
|
|
help
|
|
This option allows to use both the ARMv8 floating point unit
|
|
and the NEON SIMD unit for floating point operations.
|
|
|
|
endchoice
|
|
|
|
choice
|
|
prompt "ARM instruction set"
|
|
depends on BR2_arm || BR2_armeb
|
|
|
|
config BR2_ARM_INSTRUCTIONS_ARM
|
|
bool "ARM"
|
|
depends on BR2_ARM_CPU_HAS_ARM
|
|
help
|
|
This option instructs the compiler to generate regular ARM
|
|
instructions, that are all 32 bits wide.
|
|
|
|
config BR2_ARM_INSTRUCTIONS_THUMB
|
|
bool "Thumb"
|
|
depends on BR2_ARM_CPU_HAS_THUMB
|
|
# Thumb-1 and VFP are not compatible
|
|
depends on BR2_ARM_SOFT_FLOAT
|
|
help
|
|
This option instructions the compiler to generate Thumb
|
|
instructions, which allows to mix 16 bits instructions and
|
|
32 bits instructions. This generally provides a much smaller
|
|
compiled binary size.
|
|
|
|
comment "Thumb1 is not compatible with VFP"
|
|
depends on BR2_ARM_CPU_HAS_THUMB
|
|
depends on !BR2_ARM_SOFT_FLOAT
|
|
|
|
config BR2_ARM_INSTRUCTIONS_THUMB2
|
|
bool "Thumb2"
|
|
depends on BR2_ARM_CPU_HAS_THUMB2
|
|
help
|
|
This option instructions the compiler to generate Thumb2
|
|
instructions, which allows to mix 16 bits instructions and
|
|
32 bits instructions. This generally provides a much smaller
|
|
compiled binary size.
|
|
|
|
endchoice
|
|
|
|
config BR2_ARCH
|
|
default "arm" if BR2_arm
|
|
default "armeb" if BR2_armeb
|
|
default "aarch64" if BR2_aarch64
|
|
default "aarch64_be" if BR2_aarch64_be
|
|
|
|
config BR2_ENDIAN
|
|
default "LITTLE" if (BR2_arm || BR2_aarch64)
|
|
default "BIG" if (BR2_armeb || BR2_aarch64_be)
|
|
|
|
config BR2_GCC_TARGET_CPU
|
|
default "arm920t" if BR2_arm920t
|
|
default "arm922t" if BR2_arm922t
|
|
default "arm926ej-s" if BR2_arm926t
|
|
default "arm1136j-s" if BR2_arm1136j_s
|
|
default "arm1136jf-s" if BR2_arm1136jf_s
|
|
default "arm1176jz-s" if BR2_arm1176jz_s
|
|
default "arm1176jzf-s" if BR2_arm1176jzf_s
|
|
default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
|
|
default "mpcorenovfp" if BR2_arm11mpcore
|
|
default "cortex-a5" if BR2_cortex_a5
|
|
default "cortex-a7" if BR2_cortex_a7
|
|
default "cortex-a8" if BR2_cortex_a8
|
|
default "cortex-a9" if BR2_cortex_a9
|
|
default "cortex-a12" if BR2_cortex_a12
|
|
default "cortex-a15" if BR2_cortex_a15
|
|
default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7
|
|
default "cortex-a17" if BR2_cortex_a17
|
|
default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7
|
|
default "cortex-m3" if BR2_cortex_m3
|
|
default "cortex-m4" if BR2_cortex_m4
|
|
default "fa526" if BR2_fa526
|
|
default "marvell-pj4" if BR2_pj4
|
|
default "strongarm" if BR2_strongarm
|
|
default "xscale" if BR2_xscale
|
|
default "iwmmxt" if BR2_iwmmxt
|
|
default "cortex-a53" if BR2_cortex_a53
|
|
default "cortex-a57" if BR2_cortex_a57
|
|
default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53
|
|
default "cortex-a72" if BR2_cortex_a72
|
|
default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53
|
|
|
|
config BR2_GCC_TARGET_ABI
|
|
default "aapcs-linux" if BR2_arm || BR2_armeb
|
|
default "lp64" if BR2_aarch64 || BR2_aarch64_be
|
|
|
|
config BR2_GCC_TARGET_FPU
|
|
depends on BR2_arm || BR2_armeb
|
|
default "vfp" if BR2_ARM_FPU_VFPV2
|
|
default "vfpv3" if BR2_ARM_FPU_VFPV3
|
|
default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
|
|
default "vfpv4" if BR2_ARM_FPU_VFPV4
|
|
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
|
|
default "neon" if BR2_ARM_FPU_NEON
|
|
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
|
|
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
|
|
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
|
|
|
|
config BR2_GCC_TARGET_FLOAT_ABI
|
|
default "soft" if BR2_ARM_SOFT_FLOAT
|
|
default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
|
|
default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
|
|
|
|
config BR2_GCC_TARGET_MODE
|
|
default "arm" if BR2_ARM_INSTRUCTIONS_ARM
|
|
default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
|
|
|
|
config BR2_READELF_ARCH_NAME
|
|
default "ARM" if BR2_arm || BR2_armeb
|
|
default "AArch64" if BR2_aarch64 || BR2_aarch64_be
|