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c37189b35e
In order to prepare the addition of ARM64 cores, add the blind BR2_ARM_CPU_ARMV8 option. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
517 lines
15 KiB
Plaintext
517 lines
15 KiB
Plaintext
# arm cpu features
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config BR2_ARM_CPU_HAS_NEON
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bool
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# for some cores, NEON support is optional
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config BR2_ARM_CPU_MAYBE_HAS_NEON
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bool
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# for some cores, VFPv2 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV2
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bool
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config BR2_ARM_CPU_HAS_VFPV2
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bool
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# for some cores, VFPv3 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV3
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bool
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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config BR2_ARM_CPU_HAS_VFPV3
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bool
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select BR2_ARM_CPU_HAS_VFPV2
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# for some cores, VFPv4 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV4
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bool
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select BR2_ARM_CPU_MAYBE_HAS_VFPV3
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config BR2_ARM_CPU_HAS_VFPV4
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bool
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select BR2_ARM_CPU_HAS_VFPV3
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config BR2_ARM_CPU_HAS_ARM
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bool
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config BR2_ARM_CPU_HAS_THUMB
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bool
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config BR2_ARM_CPU_HAS_THUMB2
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bool
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config BR2_ARM_CPU_ARMV4
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bool
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config BR2_ARM_CPU_ARMV5
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bool
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config BR2_ARM_CPU_ARMV6
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bool
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config BR2_ARM_CPU_ARMV7A
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bool
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config BR2_ARM_CPU_ARMV7M
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bool
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config BR2_ARM_CPU_ARMV8
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bool
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choice
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prompt "Target Architecture Variant"
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default BR2_arm926t
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help
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Specific CPU variant to use
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config BR2_arm920t
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bool "arm920t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm922t
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bool "arm922t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm926t
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bool "arm926t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1136j_s
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bool "arm1136j-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1136jf_s
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bool "arm1136jf-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1176jz_s
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bool "arm1176jz-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm1176jzf_s
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bool "arm1176jzf-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_arm11mpcore
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bool "mpcore"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a5
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bool "cortex-A5"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_MAYBE_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a7
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bool "cortex-A7"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a8
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bool "cortex-A8"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV3
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a9
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bool "cortex-A9"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_MAYBE_HAS_VFPV3
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a12
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bool "cortex-A12"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a15
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bool "cortex-A15"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_a17
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bool "cortex-A17"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_m3
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bool "cortex-M3"
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7M
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depends on !BR2_ARCH_IS_64
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config BR2_cortex_m4
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bool "cortex-M4"
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7M
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depends on !BR2_ARCH_IS_64
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config BR2_fa526
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bool "fa526/626"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_pj4
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bool "pj4"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV3
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_strongarm
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bool "strongarm sa110/sa1100"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_xscale
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bool "xscale"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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config BR2_iwmmxt
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bool "iwmmxt"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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depends on !BR2_ARCH_IS_64
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endchoice
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config BR2_ARM_ENABLE_NEON
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bool "Enable NEON SIMD extension support"
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depends on BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_HAS_NEON
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help
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For some CPU cores, the NEON SIMD extension is optional.
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Select this option if you are certain your particular
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implementation has NEON support and you want to use it.
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config BR2_ARM_ENABLE_VFP
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bool "Enable VFP extension support"
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depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
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select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
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select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
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help
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For some CPU cores, the VFP extension is optional. Select
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this option if you are certain your particular
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implementation has VFP support and you want to use it.
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choice
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prompt "Target ABI"
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depends on BR2_arm || BR2_armeb
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default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
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default BR2_ARM_EABI
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help
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Application Binary Interface to use. The Application Binary
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Interface describes the calling conventions (how arguments
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are passed to functions, how the return value is passed, how
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system calls are made, etc.).
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config BR2_ARM_EABI
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bool "EABI"
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help
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The EABI is currently the standard ARM ABI, which is used in
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most projects. It supports both the 'soft' floating point
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model (in which floating point instructions are emulated in
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software) and the 'softfp' floating point model (in which
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floating point instructions are executed using an hardware
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floating point unit, but floating point arguments to
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functions are passed in integer registers).
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The 'softfp' floating point model is link-compatible with
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the 'soft' floating point model, i.e you can link a library
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built 'soft' with some other code built 'softfp'.
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However, passing the floating point arguments in integer
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registers is a bit inefficient, so if your ARM processor has
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a floating point unit, and you don't have pre-compiled
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'soft' or 'softfp' code, using the EABIhf ABI will provide
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better floating point performances.
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If your processor does not have a floating point unit, then
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you must use this ABI.
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config BR2_ARM_EABIHF
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bool "EABIhf"
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depends on BR2_ARM_CPU_HAS_VFPV2
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help
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The EABIhf is an extension of EABI which supports the 'hard'
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floating point model. This model uses the floating point
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unit to execute floating point instructions, and passes
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floating point arguments in floating point registers.
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It is more efficient than EABI for floating point related
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workload. However, it does not allow to link against code
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that has been pre-built for the 'soft' or 'softfp' floating
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point models.
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If your processor has a floating point unit, and you don't
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depend on existing pre-compiled code, this option is most
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likely the best choice.
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endchoice
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choice
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prompt "Floating point strategy"
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depends on BR2_ARM_EABI || BR2_ARM_EABIHF
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default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
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default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
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default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
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default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
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config BR2_ARM_SOFT_FLOAT
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bool "Soft float"
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depends on BR2_ARM_EABI
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select BR2_SOFT_FLOAT
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help
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This option allows to use software emulated floating
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point. It should be used for ARM cores that do not include a
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Vector Floating Point unit, such as ARMv5 cores (ARM926 for
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example) or certain ARMv6 cores.
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config BR2_ARM_FPU_VFPV2
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bool "VFPv2"
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depends on BR2_ARM_CPU_HAS_VFPV2
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help
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This option allows to use the VFPv2 floating point unit, as
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available in some ARMv5 processors (ARM926EJ-S) and some
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ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
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MPCore).
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Note that this option is also safe to use for newer cores
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such as Cortex-A, because the VFPv3 and VFPv4 units are
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backward compatible with VFPv2.
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config BR2_ARM_FPU_VFPV3
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bool "VFPv3"
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depends on BR2_ARM_CPU_HAS_VFPV3
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help
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This option allows to use the VFPv3 floating point unit, as
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available in some ARMv7 processors (Cortex-A{8, 9}). This
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option requires a VFPv3 unit that has 32 double-precision
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registers, which is not necessarily the case in all SOCs
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based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
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instead, which is guaranteed to work on all Cortex-A{8, 9}.
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Note that this option is also safe to use for newer cores
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that have a VFPv4 unit, because VFPv4 is backward compatible
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with VFPv3. They must of course also have 32
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double-precision registers.
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config BR2_ARM_FPU_VFPV3D16
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bool "VFPv3-D16"
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depends on BR2_ARM_CPU_HAS_VFPV3
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help
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This option allows to use the VFPv3 floating point unit, as
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available in some ARMv7 processors (Cortex-A{8, 9}). This
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option requires a VFPv3 unit that has 16 double-precision
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registers, which is generally the case in all SOCs based on
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Cortex-A{8, 9}, even though VFPv3 is technically optional on
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Cortex-A9. This is the safest option for those cores.
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Note that this option is also safe to use for newer cores
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such that have a VFPv4 unit, because the VFPv4 is backward
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compatible with VFPv3.
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config BR2_ARM_FPU_VFPV4
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bool "VFPv4"
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depends on BR2_ARM_CPU_HAS_VFPV4
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help
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This option allows to use the VFPv4 floating point unit, as
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available in some ARMv7 processors (Cortex-A{5, 7, 12,
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15}). This option requires a VFPv4 unit that has 32
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double-precision registers, which is not necessarily the
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case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
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unsure, you should probably use VFPv4-D16 instead.
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Note that if you want binary code that works on all ARMv7
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cores, including the earlier Cortex-A{8, 9}, you should
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instead select VFPv3.
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config BR2_ARM_FPU_VFPV4D16
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bool "VFPv4-D16"
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depends on BR2_ARM_CPU_HAS_VFPV4
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help
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This option allows to use the VFPv4 floating point unit, as
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available in some ARMv7 processors (Cortex-A{5, 7, 12,
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15}). This option requires a VFPv4 unit that has 16
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double-precision registers, which is always available on
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Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
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Cortex-A7.
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Note that if you want binary code that works on all ARMv7
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cores, including the earlier Cortex-A{8, 9}, you should
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instead select VFPv3-D16.
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config BR2_ARM_FPU_NEON
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bool "NEON"
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depends on BR2_ARM_CPU_HAS_NEON
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help
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This option allows to use the NEON SIMD unit, as available
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in some ARMv7 processors, as a floating-point unit. It
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should however be noted that using NEON for floating point
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operations doesn't provide a complete compatibility with the
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IEEE 754.
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config BR2_ARM_FPU_NEON_VFPV4
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bool "NEON/VFPv4"
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depends on BR2_ARM_CPU_HAS_VFPV4
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depends on BR2_ARM_CPU_HAS_NEON
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help
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This option allows to use both the VFPv4 and the NEON SIMD
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units for floating point operations. Note that some ARMv7
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cores do not necessarily have VFPv4 and/or NEON support, for
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example on Cortex-A5 and Cortex-A7, support for VFPv4 and
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NEON is optional.
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endchoice
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choice
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prompt "ARM instruction set"
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depends on BR2_arm || BR2_armeb
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config BR2_ARM_INSTRUCTIONS_ARM
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bool "ARM"
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depends on BR2_ARM_CPU_HAS_ARM
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help
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This option instructs the compiler to generate regular ARM
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instructions, that are all 32 bits wide.
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config BR2_ARM_INSTRUCTIONS_THUMB
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bool "Thumb"
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depends on BR2_ARM_CPU_HAS_THUMB
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# Thumb-1 and VFP are not compatible
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depends on BR2_ARM_SOFT_FLOAT
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help
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This option instructions the compiler to generate Thumb
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instructions, which allows to mix 16 bits instructions and
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32 bits instructions. This generally provides a much smaller
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compiled binary size.
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comment "Thumb1 is not compatible with VFP"
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depends on BR2_ARM_CPU_HAS_THUMB
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depends on !BR2_ARM_SOFT_FLOAT
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config BR2_ARM_INSTRUCTIONS_THUMB2
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bool "Thumb2"
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depends on BR2_ARM_CPU_HAS_THUMB2
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help
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This option instructions the compiler to generate Thumb2
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instructions, which allows to mix 16 bits instructions and
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32 bits instructions. This generally provides a much smaller
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compiled binary size.
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endchoice
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config BR2_ARCH
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default "arm" if BR2_arm
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default "armeb" if BR2_armeb
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default "aarch64" if BR2_aarch64
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default "aarch64_be" if BR2_aarch64_be
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config BR2_ENDIAN
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default "LITTLE" if (BR2_arm || BR2_aarch64)
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default "BIG" if (BR2_armeb || BR2_aarch64_be)
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config BR2_GCC_TARGET_CPU
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default "arm920t" if BR2_arm920t
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default "arm922t" if BR2_arm922t
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default "arm926ej-s" if BR2_arm926t
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default "arm1136j-s" if BR2_arm1136j_s
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default "arm1136jf-s" if BR2_arm1136jf_s
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default "arm1176jz-s" if BR2_arm1176jz_s
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default "arm1176jzf-s" if BR2_arm1176jzf_s
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default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
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default "mpcorenovfp" if BR2_arm11mpcore
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default "cortex-a5" if BR2_cortex_a5
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default "cortex-a7" if BR2_cortex_a7
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default "cortex-a8" if BR2_cortex_a8
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default "cortex-a9" if BR2_cortex_a9
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default "cortex-a12" if BR2_cortex_a12
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default "cortex-a15" if BR2_cortex_a15
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default "cortex-a17" if BR2_cortex_a17
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default "cortex-m3" if BR2_cortex_m3
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default "cortex-m4" if BR2_cortex_m4
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default "fa526" if BR2_fa526
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default "marvell-pj4" if BR2_pj4
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default "strongarm" if BR2_strongarm
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default "xscale" if BR2_xscale
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default "iwmmxt" if BR2_iwmmxt
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config BR2_GCC_TARGET_ABI
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default "aapcs-linux" if BR2_arm || BR2_armeb
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config BR2_GCC_TARGET_FPU
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depends on BR2_arm || BR2_armeb
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default "vfp" if BR2_ARM_FPU_VFPV2
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default "vfpv3" if BR2_ARM_FPU_VFPV3
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default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
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default "vfpv4" if BR2_ARM_FPU_VFPV4
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default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
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default "neon" if BR2_ARM_FPU_NEON
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default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
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config BR2_GCC_TARGET_FLOAT_ABI
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default "soft" if BR2_ARM_SOFT_FLOAT
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default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
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default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
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config BR2_GCC_TARGET_MODE
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default "arm" if BR2_ARM_INSTRUCTIONS_ARM
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default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
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