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0b630b5bf3
The Neoverse N1 CPU was supported in GCC earlier through the codename Ares [1]. [1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=37cf0ddecfd1eb5c6852a44135af5a92e5103931 Build tested: https://gitlab.com/kubu93/buildroot/pipelines/60318953 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> [Romain: rename BR2_ares to BR2_neoverse_n1] Signed-off-by: Romain Naour <romain.naour@gmail.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> [Arnout: 'aka' instead of 'alias'] Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
935 lines
28 KiB
Plaintext
935 lines
28 KiB
Plaintext
# arm cpu features
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config BR2_ARM_CPU_HAS_NEON
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bool
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# for some cores, NEON support is optional
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config BR2_ARM_CPU_MAYBE_HAS_NEON
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bool
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# For some cores, the FPU is optional
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config BR2_ARM_CPU_MAYBE_HAS_FPU
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bool
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config BR2_ARM_CPU_HAS_FPU
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bool
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# for some cores, VFPv2 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV2
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bool
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select BR2_ARM_CPU_MAYBE_HAS_FPU
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config BR2_ARM_CPU_HAS_VFPV2
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bool
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select BR2_ARM_CPU_HAS_FPU
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# for some cores, VFPv3 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV3
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bool
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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config BR2_ARM_CPU_HAS_VFPV3
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bool
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select BR2_ARM_CPU_HAS_VFPV2
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# for some cores, VFPv4 is optional
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config BR2_ARM_CPU_MAYBE_HAS_VFPV4
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bool
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select BR2_ARM_CPU_MAYBE_HAS_VFPV3
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config BR2_ARM_CPU_HAS_VFPV4
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bool
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select BR2_ARM_CPU_HAS_VFPV3
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# FPv4 is always optional
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config BR2_ARM_CPU_MAYBE_HAS_FPV4
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bool
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select BR2_ARM_CPU_MAYBE_HAS_FPU
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config BR2_ARM_CPU_HAS_FPV4
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bool
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select BR2_ARM_CPU_HAS_FPU
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# FPv5 is always optional
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config BR2_ARM_CPU_MAYBE_HAS_FPV5
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bool
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select BR2_ARM_CPU_MAYBE_HAS_FPV4
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config BR2_ARM_CPU_HAS_FPV5
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bool
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select BR2_ARM_CPU_HAS_FPV4
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config BR2_ARM_CPU_HAS_FP_ARMV8
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bool
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select BR2_ARM_CPU_HAS_VFPV4
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config BR2_ARM_CPU_HAS_ARM
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bool
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config BR2_ARM_CPU_HAS_THUMB
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bool
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config BR2_ARM_CPU_HAS_THUMB2
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bool
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config BR2_ARM_CPU_ARMV4
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bool
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config BR2_ARM_CPU_ARMV5
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bool
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config BR2_ARM_CPU_ARMV6
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bool
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config BR2_ARM_CPU_ARMV7A
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bool
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config BR2_ARM_CPU_ARMV7M
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bool
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config BR2_ARM_CPU_ARMV8A
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bool
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choice
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prompt "Target Architecture Variant"
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default BR2_cortex_a53 if BR2_ARCH_IS_64
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default BR2_arm926t
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help
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Specific CPU variant to use
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if !BR2_ARCH_IS_64
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comment "armv4 cores"
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config BR2_arm920t
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bool "arm920t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_arm922t
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bool "arm922t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_fa526
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bool "fa526/626"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_strongarm
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bool "strongarm sa110/sa1100"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV4
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select BR2_ARCH_HAS_MMU_OPTIONAL
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comment "armv5 cores"
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config BR2_arm926t
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bool "arm926t"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_iwmmxt
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bool "iwmmxt"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_xscale
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bool "xscale"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV5
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select BR2_ARCH_HAS_MMU_OPTIONAL
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comment "armv6 cores"
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config BR2_arm1136j_s
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bool "arm1136j-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_arm1136jf_s
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bool "arm1136jf-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_arm1176jz_s
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bool "arm1176jz-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_arm1176jzf_s
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bool "arm1176jzf-s"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_arm11mpcore
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bool "mpcore"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_VFPV2
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select BR2_ARM_CPU_HAS_THUMB
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select BR2_ARM_CPU_ARMV6
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select BR2_ARCH_HAS_MMU_OPTIONAL
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comment "armv7a cores"
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config BR2_cortex_a5
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bool "cortex-A5"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_MAYBE_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a7
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bool "cortex-A7"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a8
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bool "cortex-A8"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV3
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a9
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bool "cortex-A9"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_MAYBE_HAS_NEON
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select BR2_ARM_CPU_MAYBE_HAS_VFPV3
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a12
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bool "cortex-A12"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a15
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bool "cortex-A15"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a15_a7
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bool "cortex-A15/A7 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_cortex_a17
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bool "cortex-A17"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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config BR2_cortex_a17_a7
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bool "cortex-A17/A7 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_VFPV4
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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config BR2_pj4
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bool "pj4"
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_VFPV3
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select BR2_ARM_CPU_ARMV7A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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comment "armv7m cores"
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config BR2_cortex_m3
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bool "cortex-M3"
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_ARMV7M
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config BR2_cortex_m4
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bool "cortex-M4"
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_MAYBE_HAS_FPV4
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select BR2_ARM_CPU_ARMV7M
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config BR2_cortex_m7
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bool "cortex-M7"
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_MAYBE_HAS_FPV5
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select BR2_ARM_CPU_ARMV7M
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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endif # !BR2_ARCH_IS_64
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comment "armv8 cores"
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config BR2_cortex_a32
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bool "cortex-A32"
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depends on !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_ARM
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select BR2_ARM_CPU_HAS_NEON
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select BR2_ARM_CPU_HAS_THUMB2
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_cortex_a35
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bool "cortex-A35"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_cortex_a53
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bool "cortex-A53"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a57
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bool "cortex-A57"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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config BR2_cortex_a57_a53
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bool "cortex-A57/A53 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_cortex_a72
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bool "cortex-A72"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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config BR2_cortex_a72_a53
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bool "cortex-A72/A53 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_cortex_a73
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bool "cortex-A73"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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config BR2_cortex_a73_a35
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bool "cortex-A73/A35 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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config BR2_cortex_a73_a53
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bool "cortex-A73/A53 big.LITTLE"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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config BR2_emag
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bool "emag"
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depends on BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
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config BR2_exynos_m1
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bool "exynos-m1"
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select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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config BR2_falkor
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bool "falkor"
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depends on BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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config BR2_phecda
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bool "phecda"
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depends on BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
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config BR2_qdf24xx
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bool "qdf24xx"
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depends on BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
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select BR2_ARM_CPU_ARMV8A
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select BR2_ARCH_HAS_MMU_OPTIONAL
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_thunderx
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bool "thunderx (aka octeontx)"
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depends on BR2_ARCH_IS_64
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select BR2_ARM_CPU_HAS_FP_ARMV8
|
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select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
|
|
config BR2_thunderxt81
|
|
bool "thunderxt81 (aka octeontx81)"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
|
|
config BR2_thunderxt83
|
|
bool "thunderxt83 (aka octeontx83)"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
|
|
config BR2_thunderxt88
|
|
bool "thunderxt88"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
|
|
config BR2_thunderxt88p1
|
|
bool "thunderxt88p1"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
|
|
config BR2_xgene1
|
|
bool "xgene1"
|
|
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
|
|
|
|
comment "armv8.1a cores"
|
|
config BR2_thunderx2t99
|
|
bool "thunderx2t99"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
|
|
config BR2_thunderx2t99p1
|
|
bool "thunderx2t99p1"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
|
|
config BR2_vulcan
|
|
bool "vulcan"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
|
|
|
|
comment "armv8.2a cores"
|
|
config BR2_cortex_a55
|
|
bool "cortex-A55"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
|
|
config BR2_cortex_a75
|
|
bool "cortex-A75"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
|
|
config BR2_cortex_a75_a55
|
|
bool "cortex-A75/A55 big.LITTLE"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
|
|
config BR2_cortex_a76
|
|
bool "cortex-A76"
|
|
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
config BR2_cortex_a76_a55
|
|
bool "cortex-A76/A55 big.LITTLE"
|
|
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
config BR2_neoverse_n1
|
|
bool "neoverse-N1 (aka ares)"
|
|
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
config BR2_tsv110
|
|
bool "tsv110"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
|
|
comment "armv8.4a cores"
|
|
config BR2_saphira
|
|
bool "saphira"
|
|
depends on BR2_ARCH_IS_64
|
|
select BR2_ARM_CPU_HAS_FP_ARMV8
|
|
select BR2_ARM_CPU_ARMV8A
|
|
select BR2_ARCH_HAS_MMU_OPTIONAL
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
|
|
endchoice
|
|
|
|
config BR2_ARM_ENABLE_NEON
|
|
bool "Enable NEON SIMD extension support"
|
|
depends on BR2_ARM_CPU_MAYBE_HAS_NEON
|
|
select BR2_ARM_CPU_HAS_NEON
|
|
help
|
|
For some CPU cores, the NEON SIMD extension is optional.
|
|
Select this option if you are certain your particular
|
|
implementation has NEON support and you want to use it.
|
|
|
|
config BR2_ARM_ENABLE_VFP
|
|
bool "Enable VFP extension support"
|
|
depends on BR2_ARM_CPU_MAYBE_HAS_FPU
|
|
select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5
|
|
select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4
|
|
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
|
|
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
|
|
select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
|
|
help
|
|
For some CPU cores, the VFP extension is optional. Select
|
|
this option if you are certain your particular
|
|
implementation has VFP support and you want to use it.
|
|
|
|
choice
|
|
prompt "Target ABI"
|
|
default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU
|
|
default BR2_ARM_EABI
|
|
depends on BR2_arm || BR2_armeb
|
|
help
|
|
Application Binary Interface to use. The Application Binary
|
|
Interface describes the calling conventions (how arguments
|
|
are passed to functions, how the return value is passed, how
|
|
system calls are made, etc.).
|
|
|
|
config BR2_ARM_EABI
|
|
bool "EABI"
|
|
help
|
|
The EABI is currently the standard ARM ABI, which is used in
|
|
most projects. It supports both the 'soft' floating point
|
|
model (in which floating point instructions are emulated in
|
|
software) and the 'softfp' floating point model (in which
|
|
floating point instructions are executed using an hardware
|
|
floating point unit, but floating point arguments to
|
|
functions are passed in integer registers).
|
|
|
|
The 'softfp' floating point model is link-compatible with
|
|
the 'soft' floating point model, i.e you can link a library
|
|
built 'soft' with some other code built 'softfp'.
|
|
|
|
However, passing the floating point arguments in integer
|
|
registers is a bit inefficient, so if your ARM processor has
|
|
a floating point unit, and you don't have pre-compiled
|
|
'soft' or 'softfp' code, using the EABIhf ABI will provide
|
|
better floating point performances.
|
|
|
|
If your processor does not have a floating point unit, then
|
|
you must use this ABI.
|
|
|
|
config BR2_ARM_EABIHF
|
|
bool "EABIhf"
|
|
depends on BR2_ARM_CPU_HAS_FPU
|
|
help
|
|
The EABIhf is an extension of EABI which supports the 'hard'
|
|
floating point model. This model uses the floating point
|
|
unit to execute floating point instructions, and passes
|
|
floating point arguments in floating point registers.
|
|
|
|
It is more efficient than EABI for floating point related
|
|
workload. However, it does not allow to link against code
|
|
that has been pre-built for the 'soft' or 'softfp' floating
|
|
point models.
|
|
|
|
If your processor has a floating point unit, and you don't
|
|
depend on existing pre-compiled code, this option is most
|
|
likely the best choice.
|
|
|
|
endchoice
|
|
|
|
choice
|
|
prompt "Floating point strategy"
|
|
default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
|
|
default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5
|
|
default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4
|
|
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
|
|
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
|
|
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
|
|
default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU
|
|
|
|
config BR2_ARM_SOFT_FLOAT
|
|
bool "Soft float"
|
|
depends on BR2_ARM_EABI
|
|
select BR2_SOFT_FLOAT
|
|
help
|
|
This option allows to use software emulated floating
|
|
point. It should be used for ARM cores that do not include a
|
|
Vector Floating Point unit, such as ARMv5 cores (ARM926 for
|
|
example) or certain ARMv6 cores.
|
|
|
|
config BR2_ARM_FPU_VFPV2
|
|
bool "VFPv2"
|
|
depends on BR2_ARM_CPU_HAS_VFPV2
|
|
help
|
|
This option allows to use the VFPv2 floating point unit, as
|
|
available in some ARMv5 processors (ARM926EJ-S) and some
|
|
ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
|
|
MPCore).
|
|
|
|
Note that this option is also safe to use for newer cores
|
|
such as Cortex-A, because the VFPv3 and VFPv4 units are
|
|
backward compatible with VFPv2.
|
|
|
|
config BR2_ARM_FPU_VFPV3
|
|
bool "VFPv3"
|
|
depends on BR2_ARM_CPU_HAS_VFPV3
|
|
help
|
|
This option allows to use the VFPv3 floating point unit, as
|
|
available in some ARMv7 processors (Cortex-A{8, 9}). This
|
|
option requires a VFPv3 unit that has 32 double-precision
|
|
registers, which is not necessarily the case in all SOCs
|
|
based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
|
|
instead, which is guaranteed to work on all Cortex-A{8, 9}.
|
|
|
|
Note that this option is also safe to use for newer cores
|
|
that have a VFPv4 unit, because VFPv4 is backward compatible
|
|
with VFPv3. They must of course also have 32
|
|
double-precision registers.
|
|
|
|
config BR2_ARM_FPU_VFPV3D16
|
|
bool "VFPv3-D16"
|
|
depends on BR2_ARM_CPU_HAS_VFPV3
|
|
help
|
|
This option allows to use the VFPv3 floating point unit, as
|
|
available in some ARMv7 processors (Cortex-A{8, 9}). This
|
|
option requires a VFPv3 unit that has 16 double-precision
|
|
registers, which is generally the case in all SOCs based on
|
|
Cortex-A{8, 9}, even though VFPv3 is technically optional on
|
|
Cortex-A9. This is the safest option for those cores.
|
|
|
|
Note that this option is also safe to use for newer cores
|
|
such that have a VFPv4 unit, because the VFPv4 is backward
|
|
compatible with VFPv3.
|
|
|
|
config BR2_ARM_FPU_VFPV4
|
|
bool "VFPv4"
|
|
depends on BR2_ARM_CPU_HAS_VFPV4
|
|
help
|
|
This option allows to use the VFPv4 floating point unit, as
|
|
available in some ARMv7 processors (Cortex-A{5, 7, 12,
|
|
15}). This option requires a VFPv4 unit that has 32
|
|
double-precision registers, which is not necessarily the
|
|
case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
|
|
unsure, you should probably use VFPv4-D16 instead.
|
|
|
|
Note that if you want binary code that works on all ARMv7
|
|
cores, including the earlier Cortex-A{8, 9}, you should
|
|
instead select VFPv3.
|
|
|
|
config BR2_ARM_FPU_VFPV4D16
|
|
bool "VFPv4-D16"
|
|
depends on BR2_ARM_CPU_HAS_VFPV4
|
|
help
|
|
This option allows to use the VFPv4 floating point unit, as
|
|
available in some ARMv7 processors (Cortex-A{5, 7, 12,
|
|
15}). This option requires a VFPv4 unit that has 16
|
|
double-precision registers, which is always available on
|
|
Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
|
|
Cortex-A7.
|
|
|
|
Note that if you want binary code that works on all ARMv7
|
|
cores, including the earlier Cortex-A{8, 9}, you should
|
|
instead select VFPv3-D16.
|
|
|
|
config BR2_ARM_FPU_NEON
|
|
bool "NEON"
|
|
depends on BR2_ARM_CPU_HAS_NEON
|
|
help
|
|
This option allows to use the NEON SIMD unit, as available
|
|
in some ARMv7 processors, as a floating-point unit. It
|
|
should however be noted that using NEON for floating point
|
|
operations doesn't provide a complete compatibility with the
|
|
IEEE 754.
|
|
|
|
config BR2_ARM_FPU_NEON_VFPV4
|
|
bool "NEON/VFPv4"
|
|
depends on BR2_ARM_CPU_HAS_VFPV4
|
|
depends on BR2_ARM_CPU_HAS_NEON
|
|
help
|
|
This option allows to use both the VFPv4 and the NEON SIMD
|
|
units for floating point operations. Note that some ARMv7
|
|
cores do not necessarily have VFPv4 and/or NEON support, for
|
|
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
|
|
NEON is optional.
|
|
|
|
config BR2_ARM_FPU_FPV4D16
|
|
bool "FPv4-D16"
|
|
depends on BR2_ARM_CPU_HAS_FPV4
|
|
help
|
|
This option allows to use the FPv4-SP (single precision)
|
|
floating point unit, as available in some ARMv7m processors
|
|
(Cortex-M4).
|
|
|
|
config BR2_ARM_FPU_FPV5D16
|
|
bool "FPv5-D16"
|
|
depends on BR2_ARM_CPU_HAS_FPV5
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
|
|
help
|
|
This option allows to use the FPv5-SP (single precision)
|
|
floating point unit, as available in some ARMv7m processors
|
|
(Cortex-M7).
|
|
|
|
Note that if you want binary code that works on the earlier
|
|
Cortex-M4, you should instead select FPv4-D16.
|
|
|
|
config BR2_ARM_FPU_FPV5DPD16
|
|
bool "FPv5-DP-D16"
|
|
depends on BR2_ARM_CPU_HAS_FPV5
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
|
|
help
|
|
This option allows to use the FPv5-DP (double precision)
|
|
floating point unit, as available in some ARMv7m processors
|
|
(Cortex-M7).
|
|
|
|
Note that if you want binary code that works on the earlier
|
|
Cortex-M4, you should instead select FPv4-D16.
|
|
|
|
config BR2_ARM_FPU_FP_ARMV8
|
|
bool "FP-ARMv8"
|
|
depends on BR2_ARM_CPU_HAS_FP_ARMV8
|
|
help
|
|
This option allows to use the ARMv8 floating point unit.
|
|
|
|
config BR2_ARM_FPU_NEON_FP_ARMV8
|
|
bool "NEON/FP-ARMv8"
|
|
depends on BR2_ARM_CPU_HAS_FP_ARMV8
|
|
depends on BR2_ARM_CPU_HAS_NEON
|
|
help
|
|
This option allows to use both the ARMv8 floating point unit
|
|
and the NEON SIMD unit for floating point operations.
|
|
|
|
endchoice
|
|
|
|
choice
|
|
prompt "ARM instruction set"
|
|
depends on BR2_arm || BR2_armeb
|
|
|
|
config BR2_ARM_INSTRUCTIONS_ARM
|
|
bool "ARM"
|
|
depends on BR2_ARM_CPU_HAS_ARM
|
|
help
|
|
This option instructs the compiler to generate regular ARM
|
|
instructions, that are all 32 bits wide.
|
|
|
|
config BR2_ARM_INSTRUCTIONS_THUMB
|
|
bool "Thumb"
|
|
depends on BR2_ARM_CPU_HAS_THUMB
|
|
# Thumb-1 and VFP are not compatible
|
|
depends on BR2_ARM_SOFT_FLOAT
|
|
help
|
|
This option instructions the compiler to generate Thumb
|
|
instructions, which allows to mix 16 bits instructions and
|
|
32 bits instructions. This generally provides a much smaller
|
|
compiled binary size.
|
|
|
|
comment "Thumb1 is not compatible with VFP"
|
|
depends on BR2_ARM_CPU_HAS_THUMB
|
|
depends on !BR2_ARM_SOFT_FLOAT
|
|
|
|
config BR2_ARM_INSTRUCTIONS_THUMB2
|
|
bool "Thumb2"
|
|
depends on BR2_ARM_CPU_HAS_THUMB2
|
|
help
|
|
This option instructions the compiler to generate Thumb2
|
|
instructions, which allows to mix 16 bits instructions and
|
|
32 bits instructions. This generally provides a much smaller
|
|
compiled binary size.
|
|
|
|
endchoice
|
|
|
|
config BR2_ARCH
|
|
default "arm" if BR2_arm
|
|
default "armeb" if BR2_armeb
|
|
default "aarch64" if BR2_aarch64
|
|
default "aarch64_be" if BR2_aarch64_be
|
|
|
|
config BR2_ENDIAN
|
|
default "LITTLE" if (BR2_arm || BR2_aarch64)
|
|
default "BIG" if (BR2_armeb || BR2_aarch64_be)
|
|
|
|
config BR2_GCC_TARGET_CPU
|
|
# armv4
|
|
default "arm920t" if BR2_arm920t
|
|
default "arm922t" if BR2_arm922t
|
|
default "fa526" if BR2_fa526
|
|
default "strongarm" if BR2_strongarm
|
|
# armv5
|
|
default "arm926ej-s" if BR2_arm926t
|
|
default "iwmmxt" if BR2_iwmmxt
|
|
default "xscale" if BR2_xscale
|
|
# armv6
|
|
default "arm1136j-s" if BR2_arm1136j_s
|
|
default "arm1136jf-s" if BR2_arm1136jf_s
|
|
default "arm1176jz-s" if BR2_arm1176jz_s
|
|
default "arm1176jzf-s" if BR2_arm1176jzf_s
|
|
default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
|
|
default "mpcorenovfp" if BR2_arm11mpcore
|
|
# armv7a
|
|
default "cortex-a5" if BR2_cortex_a5
|
|
default "cortex-a7" if BR2_cortex_a7
|
|
default "cortex-a8" if BR2_cortex_a8
|
|
default "cortex-a9" if BR2_cortex_a9
|
|
default "cortex-a12" if BR2_cortex_a12
|
|
default "cortex-a15" if BR2_cortex_a15
|
|
default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7
|
|
default "cortex-a17" if BR2_cortex_a17
|
|
default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7
|
|
default "marvell-pj4" if BR2_pj4
|
|
# armv7m
|
|
default "cortex-m3" if BR2_cortex_m3
|
|
default "cortex-m4" if BR2_cortex_m4
|
|
default "cortex-m7" if BR2_cortex_m7
|
|
# armv8a
|
|
default "cortex-a32" if BR2_cortex_a32
|
|
default "cortex-a35" if BR2_cortex_a35
|
|
default "cortex-a53" if BR2_cortex_a53
|
|
default "cortex-a57" if BR2_cortex_a57
|
|
default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53
|
|
default "cortex-a72" if BR2_cortex_a72
|
|
default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53
|
|
default "cortex-a73" if BR2_cortex_a73
|
|
default "cortex-a73.cortex-a35" if BR2_cortex_a73_a35
|
|
default "cortex-a73.cortex-a53" if BR2_cortex_a73_a53
|
|
default "emag" if BR2_emag
|
|
default "exynos-m1" if BR2_exynos_m1
|
|
default "falkor" if BR2_falkor
|
|
default "phecda" if BR2_phecda
|
|
default "qdf24xx" if BR2_qdf24xx
|
|
default "thunderx" if BR2_thunderx && !BR2_TOOLCHAIN_GCC_AT_LEAST_9
|
|
default "octeontx" if BR2_thunderx && BR2_TOOLCHAIN_GCC_AT_LEAST_9
|
|
default "thunderxt81" if BR2_thunderxt81 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9
|
|
default "octeontx81" if BR2_thunderxt81 && BR2_TOOLCHAIN_GCC_AT_LEAST_9
|
|
default "thunderxt83" if BR2_thunderxt83 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9
|
|
default "octeontx83" if BR2_thunderxt83 && BR2_TOOLCHAIN_GCC_AT_LEAST_9
|
|
default "thunderxt88" if BR2_thunderxt88
|
|
default "thunderxt88p1" if BR2_thunderxt88p1
|
|
default "xgene1" if BR2_xgene1
|
|
# armv8.1a
|
|
default "thunderx2t99" if BR2_thunderx2t99
|
|
default "thunderx2t99p1" if BR2_thunderx2t99p1
|
|
default "vulcan" if BR2_vulcan
|
|
# armv8.2a
|
|
default "cortex-a55" if BR2_cortex_a55
|
|
default "cortex-a75" if BR2_cortex_a75
|
|
default "cortex-a75.cortex-a55" if BR2_cortex_a75_a55
|
|
default "cortex-a76" if BR2_cortex_a76
|
|
default "cortex-a76.cortex-a55" if BR2_cortex_a76_a55
|
|
default "neoverse-n1" if BR2_neoverse_n1
|
|
default "tsv110" if BR2_tsv110
|
|
# armv8.4a
|
|
default "saphira" if BR2_saphira
|
|
|
|
config BR2_GCC_TARGET_ABI
|
|
default "aapcs-linux" if BR2_arm || BR2_armeb
|
|
default "lp64" if BR2_aarch64 || BR2_aarch64_be
|
|
|
|
config BR2_GCC_TARGET_FPU
|
|
default "vfp" if BR2_ARM_FPU_VFPV2
|
|
default "vfpv3" if BR2_ARM_FPU_VFPV3
|
|
default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
|
|
default "vfpv4" if BR2_ARM_FPU_VFPV4
|
|
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
|
|
default "neon" if BR2_ARM_FPU_NEON
|
|
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
|
|
default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16
|
|
default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16
|
|
default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16
|
|
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
|
|
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
|
|
depends on BR2_arm || BR2_armeb
|
|
|
|
config BR2_GCC_TARGET_FLOAT_ABI
|
|
default "soft" if BR2_ARM_SOFT_FLOAT
|
|
default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
|
|
default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
|
|
|
|
config BR2_GCC_TARGET_MODE
|
|
default "arm" if BR2_ARM_INSTRUCTIONS_ARM
|
|
default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
|
|
|
|
config BR2_READELF_ARCH_NAME
|
|
default "ARM" if BR2_arm || BR2_armeb
|
|
default "AArch64" if BR2_aarch64 || BR2_aarch64_be
|
|
|
|
# vim: ft=kconfig
|
|
# -*- mode:kconfig; -*-
|