Yann E. MORIN 09c6e28233 arch/arm: add option for FPv4 FPU ... The FPv4-SP FPU is a single-precision FPU with 16 double registers [0] [1]. It is only available for cortex-m4 cores, and is known to gcc as fpv4-sp-d16 (note that there is no leading 'v') since gcc-4.5 [2]. [0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4 [1] https://developer.arm.com/docs/ddi0439/latest/floating-point-unit [2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=639cb7b789a54bf78d6ae5e2644450f5eb1837a6 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>		2018-05-20 19:06:07 +02:00
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arch.mk.xtensa	arc/xtensa: store the Xtensa overlay in the per-package DL_DIR	2018-04-02 15:59:30 +02:00
Config.in	arch: drop BR2_BINFMT_FLAT_SEP_DATA support	2018-04-15 22:04:09 +02:00
Config.in.arc	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.arm	arch/arm: add option for FPv4 FPU	2018-05-20 19:06:07 +02:00
Config.in.csky	arch: add BR2_READELF_ARCH_NAME hidden config option	2017-03-20 22:22:17 +01:00
Config.in.m68k	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.microblaze	arch: add BR2_READELF_ARCH_NAME hidden config option	2017-03-20 22:22:17 +01:00
Config.in.mips	*/Config.in*: remove consecutive empty lines	2018-04-01 08:48:24 +02:00
Config.in.nios2	arch: add BR2_READELF_ARCH_NAME hidden config option	2017-03-20 22:22:17 +01:00
Config.in.or1k	arch: add BR2_READELF_ARCH_NAME hidden config option	2017-03-20 22:22:17 +01:00
Config.in.powerpc	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.sh	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.sparc	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.x86	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.xtensa	arch/Config.in*: re-wrap help text	2018-04-01 08:00:13 +02:00